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19#include "qemu/osdep.h"
20#include "qemu/log.h"
21#include "cpu.h"
22#include "tcg/tcg-op.h"
23#include "disas/disas.h"
24#include "exec/cpu_ldst.h"
25#include "exec/exec-all.h"
26#include "exec/helper-proto.h"
27#include "exec/helper-gen.h"
28
29#include "exec/translator.h"
30#include "exec/log.h"
31
32#include "instmap.h"
33#include "internals.h"
34
35
36static TCGv cpu_gpr[32], cpu_gprh[32], cpu_pc, cpu_vl, cpu_vstart;
37static TCGv_i64 cpu_fpr[32];
38static TCGv load_res;
39static TCGv load_val;
40
41static TCGv pm_mask;
42static TCGv pm_base;
43
44#include "exec/gen-icount.h"
45
46
47
48
49
50
51typedef enum {
52 EXT_NONE,
53 EXT_SIGN,
54 EXT_ZERO,
55} DisasExtend;
56
57typedef struct DisasContext {
58 DisasContextBase base;
59
60 target_ulong pc_succ_insn;
61 target_ulong priv_ver;
62 RISCVMXL misa_mxl_max;
63 RISCVMXL xl;
64 uint32_t misa_ext;
65 uint32_t opcode;
66 uint32_t mstatus_fs;
67 uint32_t mstatus_vs;
68 uint32_t mstatus_hs_fs;
69 uint32_t mstatus_hs_vs;
70 uint32_t mem_idx;
71
72
73
74
75
76 int frm;
77 RISCVMXL ol;
78 bool virt_enabled;
79 const RISCVCPUConfig *cfg_ptr;
80 bool hlsx;
81
82 bool vill;
83
84
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89
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91
92
93
94
95 int8_t lmul;
96 uint8_t sew;
97 uint8_t vta;
98 bool cfg_vta_all_1s;
99 target_ulong vstart;
100 bool vl_eq_vlmax;
101 uint8_t ntemp;
102 CPUState *cs;
103 TCGv zero;
104
105 TCGv temp[4];
106
107 TCGv_i64 ftemp[4];
108 uint8_t nftemp;
109
110 bool pm_mask_enabled;
111 bool pm_base_enabled;
112
113 TCGOp *insn_start;
114} DisasContext;
115
116static inline bool has_ext(DisasContext *ctx, uint32_t ext)
117{
118 return ctx->misa_ext & ext;
119}
120
121static bool always_true_p(DisasContext *ctx __attribute__((__unused__)))
122{
123 return true;
124}
125
126#define MATERIALISE_EXT_PREDICATE(ext) \
127 static bool has_ ## ext ## _p(DisasContext *ctx) \
128 { \
129 return ctx->cfg_ptr->ext_ ## ext ; \
130 }
131
132MATERIALISE_EXT_PREDICATE(XVentanaCondOps);
133
134#ifdef TARGET_RISCV32
135#define get_xl(ctx) MXL_RV32
136#elif defined(CONFIG_USER_ONLY)
137#define get_xl(ctx) MXL_RV64
138#else
139#define get_xl(ctx) ((ctx)->xl)
140#endif
141
142
143static inline int __attribute__((unused)) get_xlen(DisasContext *ctx)
144{
145 return 16 << get_xl(ctx);
146}
147
148
149#ifdef TARGET_RISCV32
150#define get_ol(ctx) MXL_RV32
151#else
152#define get_ol(ctx) ((ctx)->ol)
153#endif
154
155static inline int get_olen(DisasContext *ctx)
156{
157 return 16 << get_ol(ctx);
158}
159
160
161#ifdef TARGET_RISCV32
162#define get_xl_max(ctx) MXL_RV32
163#else
164#define get_xl_max(ctx) ((ctx)->misa_mxl_max)
165#endif
166
167
168
169
170
171
172
173static void gen_nanbox_s(TCGv_i64 out, TCGv_i64 in)
174{
175 tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(32, 32));
176}
177
178static void gen_nanbox_h(TCGv_i64 out, TCGv_i64 in)
179{
180 tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(16, 48));
181}
182
183
184
185
186
187
188
189
190
191static void gen_check_nanbox_h(TCGv_i64 out, TCGv_i64 in)
192{
193 TCGv_i64 t_max = tcg_const_i64(0xffffffffffff0000ull);
194 TCGv_i64 t_nan = tcg_const_i64(0xffffffffffff7e00ull);
195
196 tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan);
197 tcg_temp_free_i64(t_max);
198 tcg_temp_free_i64(t_nan);
199}
200
201static void gen_check_nanbox_s(TCGv_i64 out, TCGv_i64 in)
202{
203 TCGv_i64 t_max = tcg_constant_i64(0xffffffff00000000ull);
204 TCGv_i64 t_nan = tcg_constant_i64(0xffffffff7fc00000ull);
205
206 tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan);
207}
208
209static void decode_save_opc(DisasContext *ctx)
210{
211 assert(ctx->insn_start != NULL);
212 tcg_set_insn_start_param(ctx->insn_start, 1, ctx->opcode);
213 ctx->insn_start = NULL;
214}
215
216static void gen_set_pc_imm(DisasContext *ctx, target_ulong dest)
217{
218 if (get_xl(ctx) == MXL_RV32) {
219 dest = (int32_t)dest;
220 }
221 tcg_gen_movi_tl(cpu_pc, dest);
222}
223
224static void gen_set_pc(DisasContext *ctx, TCGv dest)
225{
226 if (get_xl(ctx) == MXL_RV32) {
227 tcg_gen_ext32s_tl(cpu_pc, dest);
228 } else {
229 tcg_gen_mov_tl(cpu_pc, dest);
230 }
231}
232
233static void generate_exception(DisasContext *ctx, int excp)
234{
235 gen_set_pc_imm(ctx, ctx->base.pc_next);
236 gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp));
237 ctx->base.is_jmp = DISAS_NORETURN;
238}
239
240static void gen_exception_illegal(DisasContext *ctx)
241{
242 tcg_gen_st_i32(tcg_constant_i32(ctx->opcode), cpu_env,
243 offsetof(CPURISCVState, bins));
244 generate_exception(ctx, RISCV_EXCP_ILLEGAL_INST);
245}
246
247static void gen_exception_inst_addr_mis(DisasContext *ctx)
248{
249 tcg_gen_st_tl(cpu_pc, cpu_env, offsetof(CPURISCVState, badaddr));
250 generate_exception(ctx, RISCV_EXCP_INST_ADDR_MIS);
251}
252
253static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
254{
255 if (translator_use_goto_tb(&ctx->base, dest)) {
256 tcg_gen_goto_tb(n);
257 gen_set_pc_imm(ctx, dest);
258 tcg_gen_exit_tb(ctx->base.tb, n);
259 } else {
260 gen_set_pc_imm(ctx, dest);
261 tcg_gen_lookup_and_goto_ptr();
262 }
263}
264
265
266
267
268
269
270
271
272
273static TCGv temp_new(DisasContext *ctx)
274{
275 assert(ctx->ntemp < ARRAY_SIZE(ctx->temp));
276 return ctx->temp[ctx->ntemp++] = tcg_temp_new();
277}
278
279static TCGv get_gpr(DisasContext *ctx, int reg_num, DisasExtend ext)
280{
281 TCGv t;
282
283 if (reg_num == 0) {
284 return ctx->zero;
285 }
286
287 switch (get_ol(ctx)) {
288 case MXL_RV32:
289 switch (ext) {
290 case EXT_NONE:
291 break;
292 case EXT_SIGN:
293 t = temp_new(ctx);
294 tcg_gen_ext32s_tl(t, cpu_gpr[reg_num]);
295 return t;
296 case EXT_ZERO:
297 t = temp_new(ctx);
298 tcg_gen_ext32u_tl(t, cpu_gpr[reg_num]);
299 return t;
300 default:
301 g_assert_not_reached();
302 }
303 break;
304 case MXL_RV64:
305 case MXL_RV128:
306 break;
307 default:
308 g_assert_not_reached();
309 }
310 return cpu_gpr[reg_num];
311}
312
313static TCGv get_gprh(DisasContext *ctx, int reg_num)
314{
315 assert(get_xl(ctx) == MXL_RV128);
316 if (reg_num == 0) {
317 return ctx->zero;
318 }
319 return cpu_gprh[reg_num];
320}
321
322static TCGv dest_gpr(DisasContext *ctx, int reg_num)
323{
324 if (reg_num == 0 || get_olen(ctx) < TARGET_LONG_BITS) {
325 return temp_new(ctx);
326 }
327 return cpu_gpr[reg_num];
328}
329
330static TCGv dest_gprh(DisasContext *ctx, int reg_num)
331{
332 if (reg_num == 0) {
333 return temp_new(ctx);
334 }
335 return cpu_gprh[reg_num];
336}
337
338static void gen_set_gpr(DisasContext *ctx, int reg_num, TCGv t)
339{
340 if (reg_num != 0) {
341 switch (get_ol(ctx)) {
342 case MXL_RV32:
343 tcg_gen_ext32s_tl(cpu_gpr[reg_num], t);
344 break;
345 case MXL_RV64:
346 case MXL_RV128:
347 tcg_gen_mov_tl(cpu_gpr[reg_num], t);
348 break;
349 default:
350 g_assert_not_reached();
351 }
352
353 if (get_xl_max(ctx) == MXL_RV128) {
354 tcg_gen_sari_tl(cpu_gprh[reg_num], cpu_gpr[reg_num], 63);
355 }
356 }
357}
358
359static void gen_set_gpri(DisasContext *ctx, int reg_num, target_long imm)
360{
361 if (reg_num != 0) {
362 switch (get_ol(ctx)) {
363 case MXL_RV32:
364 tcg_gen_movi_tl(cpu_gpr[reg_num], (int32_t)imm);
365 break;
366 case MXL_RV64:
367 case MXL_RV128:
368 tcg_gen_movi_tl(cpu_gpr[reg_num], imm);
369 break;
370 default:
371 g_assert_not_reached();
372 }
373
374 if (get_xl_max(ctx) == MXL_RV128) {
375 tcg_gen_movi_tl(cpu_gprh[reg_num], -(imm < 0));
376 }
377 }
378}
379
380static void gen_set_gpr128(DisasContext *ctx, int reg_num, TCGv rl, TCGv rh)
381{
382 assert(get_ol(ctx) == MXL_RV128);
383 if (reg_num != 0) {
384 tcg_gen_mov_tl(cpu_gpr[reg_num], rl);
385 tcg_gen_mov_tl(cpu_gprh[reg_num], rh);
386 }
387}
388
389static TCGv_i64 ftemp_new(DisasContext *ctx)
390{
391 assert(ctx->nftemp < ARRAY_SIZE(ctx->ftemp));
392 return ctx->ftemp[ctx->nftemp++] = tcg_temp_new_i64();
393}
394
395static TCGv_i64 get_fpr_hs(DisasContext *ctx, int reg_num)
396{
397 if (!ctx->cfg_ptr->ext_zfinx) {
398 return cpu_fpr[reg_num];
399 }
400
401 if (reg_num == 0) {
402 return tcg_constant_i64(0);
403 }
404 switch (get_xl(ctx)) {
405 case MXL_RV32:
406#ifdef TARGET_RISCV32
407 {
408 TCGv_i64 t = ftemp_new(ctx);
409 tcg_gen_ext_i32_i64(t, cpu_gpr[reg_num]);
410 return t;
411 }
412#else
413
414 case MXL_RV64:
415 return cpu_gpr[reg_num];
416#endif
417 default:
418 g_assert_not_reached();
419 }
420}
421
422static TCGv_i64 get_fpr_d(DisasContext *ctx, int reg_num)
423{
424 if (!ctx->cfg_ptr->ext_zfinx) {
425 return cpu_fpr[reg_num];
426 }
427
428 if (reg_num == 0) {
429 return tcg_constant_i64(0);
430 }
431 switch (get_xl(ctx)) {
432 case MXL_RV32:
433 {
434 TCGv_i64 t = ftemp_new(ctx);
435 tcg_gen_concat_tl_i64(t, cpu_gpr[reg_num], cpu_gpr[reg_num + 1]);
436 return t;
437 }
438#ifdef TARGET_RISCV64
439 case MXL_RV64:
440 return cpu_gpr[reg_num];
441#endif
442 default:
443 g_assert_not_reached();
444 }
445}
446
447static TCGv_i64 dest_fpr(DisasContext *ctx, int reg_num)
448{
449 if (!ctx->cfg_ptr->ext_zfinx) {
450 return cpu_fpr[reg_num];
451 }
452
453 if (reg_num == 0) {
454 return ftemp_new(ctx);
455 }
456
457 switch (get_xl(ctx)) {
458 case MXL_RV32:
459 return ftemp_new(ctx);
460#ifdef TARGET_RISCV64
461 case MXL_RV64:
462 return cpu_gpr[reg_num];
463#endif
464 default:
465 g_assert_not_reached();
466 }
467}
468
469
470static void gen_set_fpr_hs(DisasContext *ctx, int reg_num, TCGv_i64 t)
471{
472 if (!ctx->cfg_ptr->ext_zfinx) {
473 tcg_gen_mov_i64(cpu_fpr[reg_num], t);
474 return;
475 }
476 if (reg_num != 0) {
477 switch (get_xl(ctx)) {
478 case MXL_RV32:
479#ifdef TARGET_RISCV32
480 tcg_gen_extrl_i64_i32(cpu_gpr[reg_num], t);
481 break;
482#else
483
484 case MXL_RV64:
485 tcg_gen_mov_i64(cpu_gpr[reg_num], t);
486 break;
487#endif
488 default:
489 g_assert_not_reached();
490 }
491 }
492}
493
494static void gen_set_fpr_d(DisasContext *ctx, int reg_num, TCGv_i64 t)
495{
496 if (!ctx->cfg_ptr->ext_zfinx) {
497 tcg_gen_mov_i64(cpu_fpr[reg_num], t);
498 return;
499 }
500
501 if (reg_num != 0) {
502 switch (get_xl(ctx)) {
503 case MXL_RV32:
504#ifdef TARGET_RISCV32
505 tcg_gen_extr_i64_i32(cpu_gpr[reg_num], cpu_gpr[reg_num + 1], t);
506 break;
507#else
508 tcg_gen_ext32s_i64(cpu_gpr[reg_num], t);
509 tcg_gen_sari_i64(cpu_gpr[reg_num + 1], t, 32);
510 break;
511 case MXL_RV64:
512 tcg_gen_mov_i64(cpu_gpr[reg_num], t);
513 break;
514#endif
515 default:
516 g_assert_not_reached();
517 }
518 }
519}
520
521static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
522{
523 target_ulong next_pc;
524
525
526 next_pc = ctx->base.pc_next + imm;
527 if (!has_ext(ctx, RVC)) {
528 if ((next_pc & 0x3) != 0) {
529 gen_exception_inst_addr_mis(ctx);
530 return;
531 }
532 }
533
534 gen_set_gpri(ctx, rd, ctx->pc_succ_insn);
535 gen_goto_tb(ctx, 0, ctx->base.pc_next + imm);
536 ctx->base.is_jmp = DISAS_NORETURN;
537}
538
539
540static TCGv get_address(DisasContext *ctx, int rs1, int imm)
541{
542 TCGv addr = temp_new(ctx);
543 TCGv src1 = get_gpr(ctx, rs1, EXT_NONE);
544
545 tcg_gen_addi_tl(addr, src1, imm);
546 if (ctx->pm_mask_enabled) {
547 tcg_gen_and_tl(addr, addr, pm_mask);
548 } else if (get_xl(ctx) == MXL_RV32) {
549 tcg_gen_ext32u_tl(addr, addr);
550 }
551 if (ctx->pm_base_enabled) {
552 tcg_gen_or_tl(addr, addr, pm_base);
553 }
554 return addr;
555}
556
557#ifndef CONFIG_USER_ONLY
558
559
560
561
562
563static void mark_fs_dirty(DisasContext *ctx)
564{
565 TCGv tmp;
566
567 if (!has_ext(ctx, RVF)) {
568 return;
569 }
570
571 if (ctx->mstatus_fs != MSTATUS_FS) {
572
573 ctx->mstatus_fs = MSTATUS_FS;
574
575 tmp = tcg_temp_new();
576 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
577 tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS);
578 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
579 tcg_temp_free(tmp);
580 }
581
582 if (ctx->virt_enabled && ctx->mstatus_hs_fs != MSTATUS_FS) {
583
584 ctx->mstatus_hs_fs = MSTATUS_FS;
585
586 tmp = tcg_temp_new();
587 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs));
588 tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS);
589 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs));
590 tcg_temp_free(tmp);
591 }
592}
593#else
594static inline void mark_fs_dirty(DisasContext *ctx) { }
595#endif
596
597#ifndef CONFIG_USER_ONLY
598
599
600
601
602
603static void mark_vs_dirty(DisasContext *ctx)
604{
605 TCGv tmp;
606
607 if (ctx->mstatus_vs != MSTATUS_VS) {
608
609 ctx->mstatus_vs = MSTATUS_VS;
610
611 tmp = tcg_temp_new();
612 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
613 tcg_gen_ori_tl(tmp, tmp, MSTATUS_VS);
614 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
615 tcg_temp_free(tmp);
616 }
617
618 if (ctx->virt_enabled && ctx->mstatus_hs_vs != MSTATUS_VS) {
619
620 ctx->mstatus_hs_vs = MSTATUS_VS;
621
622 tmp = tcg_temp_new();
623 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs));
624 tcg_gen_ori_tl(tmp, tmp, MSTATUS_VS);
625 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs));
626 tcg_temp_free(tmp);
627 }
628}
629#else
630static inline void mark_vs_dirty(DisasContext *ctx) { }
631#endif
632
633static void gen_set_rm(DisasContext *ctx, int rm)
634{
635 if (ctx->frm == rm) {
636 return;
637 }
638 ctx->frm = rm;
639
640 if (rm == RISCV_FRM_ROD) {
641 gen_helper_set_rod_rounding_mode(cpu_env);
642 return;
643 }
644
645
646 decode_save_opc(ctx);
647 gen_helper_set_rounding_mode(cpu_env, tcg_constant_i32(rm));
648}
649
650static int ex_plus_1(DisasContext *ctx, int nf)
651{
652 return nf + 1;
653}
654
655#define EX_SH(amount) \
656 static int ex_shift_##amount(DisasContext *ctx, int imm) \
657 { \
658 return imm << amount; \
659 }
660EX_SH(1)
661EX_SH(2)
662EX_SH(3)
663EX_SH(4)
664EX_SH(12)
665
666#define REQUIRE_EXT(ctx, ext) do { \
667 if (!has_ext(ctx, ext)) { \
668 return false; \
669 } \
670} while (0)
671
672#define REQUIRE_32BIT(ctx) do { \
673 if (get_xl(ctx) != MXL_RV32) { \
674 return false; \
675 } \
676} while (0)
677
678#define REQUIRE_64BIT(ctx) do { \
679 if (get_xl(ctx) != MXL_RV64) { \
680 return false; \
681 } \
682} while (0)
683
684#define REQUIRE_128BIT(ctx) do { \
685 if (get_xl(ctx) != MXL_RV128) { \
686 return false; \
687 } \
688} while (0)
689
690#define REQUIRE_64_OR_128BIT(ctx) do { \
691 if (get_xl(ctx) == MXL_RV32) { \
692 return false; \
693 } \
694} while (0)
695
696#define REQUIRE_EITHER_EXT(ctx, A, B) do { \
697 if (!ctx->cfg_ptr->ext_##A && \
698 !ctx->cfg_ptr->ext_##B) { \
699 return false; \
700 } \
701} while (0)
702
703static int ex_rvc_register(DisasContext *ctx, int reg)
704{
705 return 8 + reg;
706}
707
708static int ex_rvc_shifti(DisasContext *ctx, int imm)
709{
710
711 return imm ? imm : 64;
712}
713
714
715#include "decode-insn32.c.inc"
716
717static bool gen_logic_imm_fn(DisasContext *ctx, arg_i *a,
718 void (*func)(TCGv, TCGv, target_long))
719{
720 TCGv dest = dest_gpr(ctx, a->rd);
721 TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
722
723 func(dest, src1, a->imm);
724
725 if (get_xl(ctx) == MXL_RV128) {
726 TCGv src1h = get_gprh(ctx, a->rs1);
727 TCGv desth = dest_gprh(ctx, a->rd);
728
729 func(desth, src1h, -(a->imm < 0));
730 gen_set_gpr128(ctx, a->rd, dest, desth);
731 } else {
732 gen_set_gpr(ctx, a->rd, dest);
733 }
734
735 return true;
736}
737
738static bool gen_logic(DisasContext *ctx, arg_r *a,
739 void (*func)(TCGv, TCGv, TCGv))
740{
741 TCGv dest = dest_gpr(ctx, a->rd);
742 TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
743 TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE);
744
745 func(dest, src1, src2);
746
747 if (get_xl(ctx) == MXL_RV128) {
748 TCGv src1h = get_gprh(ctx, a->rs1);
749 TCGv src2h = get_gprh(ctx, a->rs2);
750 TCGv desth = dest_gprh(ctx, a->rd);
751
752 func(desth, src1h, src2h);
753 gen_set_gpr128(ctx, a->rd, dest, desth);
754 } else {
755 gen_set_gpr(ctx, a->rd, dest);
756 }
757
758 return true;
759}
760
761static bool gen_arith_imm_fn(DisasContext *ctx, arg_i *a, DisasExtend ext,
762 void (*func)(TCGv, TCGv, target_long),
763 void (*f128)(TCGv, TCGv, TCGv, TCGv, target_long))
764{
765 TCGv dest = dest_gpr(ctx, a->rd);
766 TCGv src1 = get_gpr(ctx, a->rs1, ext);
767
768 if (get_ol(ctx) < MXL_RV128) {
769 func(dest, src1, a->imm);
770 gen_set_gpr(ctx, a->rd, dest);
771 } else {
772 if (f128 == NULL) {
773 return false;
774 }
775
776 TCGv src1h = get_gprh(ctx, a->rs1);
777 TCGv desth = dest_gprh(ctx, a->rd);
778
779 f128(dest, desth, src1, src1h, a->imm);
780 gen_set_gpr128(ctx, a->rd, dest, desth);
781 }
782 return true;
783}
784
785static bool gen_arith_imm_tl(DisasContext *ctx, arg_i *a, DisasExtend ext,
786 void (*func)(TCGv, TCGv, TCGv),
787 void (*f128)(TCGv, TCGv, TCGv, TCGv, TCGv, TCGv))
788{
789 TCGv dest = dest_gpr(ctx, a->rd);
790 TCGv src1 = get_gpr(ctx, a->rs1, ext);
791 TCGv src2 = tcg_constant_tl(a->imm);
792
793 if (get_ol(ctx) < MXL_RV128) {
794 func(dest, src1, src2);
795 gen_set_gpr(ctx, a->rd, dest);
796 } else {
797 if (f128 == NULL) {
798 return false;
799 }
800
801 TCGv src1h = get_gprh(ctx, a->rs1);
802 TCGv src2h = tcg_constant_tl(-(a->imm < 0));
803 TCGv desth = dest_gprh(ctx, a->rd);
804
805 f128(dest, desth, src1, src1h, src2, src2h);
806 gen_set_gpr128(ctx, a->rd, dest, desth);
807 }
808 return true;
809}
810
811static bool gen_arith(DisasContext *ctx, arg_r *a, DisasExtend ext,
812 void (*func)(TCGv, TCGv, TCGv),
813 void (*f128)(TCGv, TCGv, TCGv, TCGv, TCGv, TCGv))
814{
815 TCGv dest = dest_gpr(ctx, a->rd);
816 TCGv src1 = get_gpr(ctx, a->rs1, ext);
817 TCGv src2 = get_gpr(ctx, a->rs2, ext);
818
819 if (get_ol(ctx) < MXL_RV128) {
820 func(dest, src1, src2);
821 gen_set_gpr(ctx, a->rd, dest);
822 } else {
823 if (f128 == NULL) {
824 return false;
825 }
826
827 TCGv src1h = get_gprh(ctx, a->rs1);
828 TCGv src2h = get_gprh(ctx, a->rs2);
829 TCGv desth = dest_gprh(ctx, a->rd);
830
831 f128(dest, desth, src1, src1h, src2, src2h);
832 gen_set_gpr128(ctx, a->rd, dest, desth);
833 }
834 return true;
835}
836
837static bool gen_arith_per_ol(DisasContext *ctx, arg_r *a, DisasExtend ext,
838 void (*f_tl)(TCGv, TCGv, TCGv),
839 void (*f_32)(TCGv, TCGv, TCGv),
840 void (*f_128)(TCGv, TCGv, TCGv, TCGv, TCGv, TCGv))
841{
842 int olen = get_olen(ctx);
843
844 if (olen != TARGET_LONG_BITS) {
845 if (olen == 32) {
846 f_tl = f_32;
847 } else if (olen != 128) {
848 g_assert_not_reached();
849 }
850 }
851 return gen_arith(ctx, a, ext, f_tl, f_128);
852}
853
854static bool gen_shift_imm_fn(DisasContext *ctx, arg_shift *a, DisasExtend ext,
855 void (*func)(TCGv, TCGv, target_long),
856 void (*f128)(TCGv, TCGv, TCGv, TCGv, target_long))
857{
858 TCGv dest, src1;
859 int max_len = get_olen(ctx);
860
861 if (a->shamt >= max_len) {
862 return false;
863 }
864
865 dest = dest_gpr(ctx, a->rd);
866 src1 = get_gpr(ctx, a->rs1, ext);
867
868 if (max_len < 128) {
869 func(dest, src1, a->shamt);
870 gen_set_gpr(ctx, a->rd, dest);
871 } else {
872 TCGv src1h = get_gprh(ctx, a->rs1);
873 TCGv desth = dest_gprh(ctx, a->rd);
874
875 if (f128 == NULL) {
876 return false;
877 }
878 f128(dest, desth, src1, src1h, a->shamt);
879 gen_set_gpr128(ctx, a->rd, dest, desth);
880 }
881 return true;
882}
883
884static bool gen_shift_imm_fn_per_ol(DisasContext *ctx, arg_shift *a,
885 DisasExtend ext,
886 void (*f_tl)(TCGv, TCGv, target_long),
887 void (*f_32)(TCGv, TCGv, target_long),
888 void (*f_128)(TCGv, TCGv, TCGv, TCGv,
889 target_long))
890{
891 int olen = get_olen(ctx);
892 if (olen != TARGET_LONG_BITS) {
893 if (olen == 32) {
894 f_tl = f_32;
895 } else if (olen != 128) {
896 g_assert_not_reached();
897 }
898 }
899 return gen_shift_imm_fn(ctx, a, ext, f_tl, f_128);
900}
901
902static bool gen_shift_imm_tl(DisasContext *ctx, arg_shift *a, DisasExtend ext,
903 void (*func)(TCGv, TCGv, TCGv))
904{
905 TCGv dest, src1, src2;
906 int max_len = get_olen(ctx);
907
908 if (a->shamt >= max_len) {
909 return false;
910 }
911
912 dest = dest_gpr(ctx, a->rd);
913 src1 = get_gpr(ctx, a->rs1, ext);
914 src2 = tcg_constant_tl(a->shamt);
915
916 func(dest, src1, src2);
917
918 gen_set_gpr(ctx, a->rd, dest);
919 return true;
920}
921
922static bool gen_shift(DisasContext *ctx, arg_r *a, DisasExtend ext,
923 void (*func)(TCGv, TCGv, TCGv),
924 void (*f128)(TCGv, TCGv, TCGv, TCGv, TCGv))
925{
926 TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE);
927 TCGv ext2 = tcg_temp_new();
928 int max_len = get_olen(ctx);
929
930 tcg_gen_andi_tl(ext2, src2, max_len - 1);
931
932 TCGv dest = dest_gpr(ctx, a->rd);
933 TCGv src1 = get_gpr(ctx, a->rs1, ext);
934
935 if (max_len < 128) {
936 func(dest, src1, ext2);
937 gen_set_gpr(ctx, a->rd, dest);
938 } else {
939 TCGv src1h = get_gprh(ctx, a->rs1);
940 TCGv desth = dest_gprh(ctx, a->rd);
941
942 if (f128 == NULL) {
943 return false;
944 }
945 f128(dest, desth, src1, src1h, ext2);
946 gen_set_gpr128(ctx, a->rd, dest, desth);
947 }
948 tcg_temp_free(ext2);
949 return true;
950}
951
952static bool gen_shift_per_ol(DisasContext *ctx, arg_r *a, DisasExtend ext,
953 void (*f_tl)(TCGv, TCGv, TCGv),
954 void (*f_32)(TCGv, TCGv, TCGv),
955 void (*f_128)(TCGv, TCGv, TCGv, TCGv, TCGv))
956{
957 int olen = get_olen(ctx);
958 if (olen != TARGET_LONG_BITS) {
959 if (olen == 32) {
960 f_tl = f_32;
961 } else if (olen != 128) {
962 g_assert_not_reached();
963 }
964 }
965 return gen_shift(ctx, a, ext, f_tl, f_128);
966}
967
968static bool gen_unary(DisasContext *ctx, arg_r2 *a, DisasExtend ext,
969 void (*func)(TCGv, TCGv))
970{
971 TCGv dest = dest_gpr(ctx, a->rd);
972 TCGv src1 = get_gpr(ctx, a->rs1, ext);
973
974 func(dest, src1);
975
976 gen_set_gpr(ctx, a->rd, dest);
977 return true;
978}
979
980static bool gen_unary_per_ol(DisasContext *ctx, arg_r2 *a, DisasExtend ext,
981 void (*f_tl)(TCGv, TCGv),
982 void (*f_32)(TCGv, TCGv))
983{
984 int olen = get_olen(ctx);
985
986 if (olen != TARGET_LONG_BITS) {
987 if (olen == 32) {
988 f_tl = f_32;
989 } else {
990 g_assert_not_reached();
991 }
992 }
993 return gen_unary(ctx, a, ext, f_tl);
994}
995
996static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc)
997{
998 DisasContext *ctx = container_of(dcbase, DisasContext, base);
999 CPUState *cpu = ctx->cs;
1000 CPURISCVState *env = cpu->env_ptr;
1001
1002 return cpu_ldl_code(env, pc);
1003}
1004
1005
1006#include "insn_trans/trans_rvi.c.inc"
1007#include "insn_trans/trans_rvm.c.inc"
1008#include "insn_trans/trans_rva.c.inc"
1009#include "insn_trans/trans_rvf.c.inc"
1010#include "insn_trans/trans_rvd.c.inc"
1011#include "insn_trans/trans_rvh.c.inc"
1012#include "insn_trans/trans_rvv.c.inc"
1013#include "insn_trans/trans_rvb.c.inc"
1014#include "insn_trans/trans_rvzfh.c.inc"
1015#include "insn_trans/trans_rvk.c.inc"
1016#include "insn_trans/trans_privileged.c.inc"
1017#include "insn_trans/trans_svinval.c.inc"
1018#include "insn_trans/trans_xventanacondops.c.inc"
1019
1020
1021#include "decode-insn16.c.inc"
1022
1023#include "decode-XVentanaCondOps.c.inc"
1024
1025static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
1026{
1027
1028
1029
1030
1031 static const struct {
1032 bool (*guard_func)(DisasContext *);
1033 bool (*decode_func)(DisasContext *, uint32_t);
1034 } decoders[] = {
1035 { always_true_p, decode_insn32 },
1036 { has_XVentanaCondOps_p, decode_XVentanaCodeOps },
1037 };
1038
1039
1040 if (extract16(opcode, 0, 2) != 3) {
1041 if (!has_ext(ctx, RVC)) {
1042 gen_exception_illegal(ctx);
1043 } else {
1044 ctx->opcode = opcode;
1045 ctx->pc_succ_insn = ctx->base.pc_next + 2;
1046 if (decode_insn16(ctx, opcode)) {
1047 return;
1048 }
1049 }
1050 } else {
1051 uint32_t opcode32 = opcode;
1052 opcode32 = deposit32(opcode32, 16, 16,
1053 translator_lduw(env, &ctx->base,
1054 ctx->base.pc_next + 2));
1055 ctx->opcode = opcode32;
1056 ctx->pc_succ_insn = ctx->base.pc_next + 4;
1057
1058 for (size_t i = 0; i < ARRAY_SIZE(decoders); ++i) {
1059 if (decoders[i].guard_func(ctx) &&
1060 decoders[i].decode_func(ctx, opcode32)) {
1061 return;
1062 }
1063 }
1064 }
1065
1066 gen_exception_illegal(ctx);
1067}
1068
1069static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
1070{
1071 DisasContext *ctx = container_of(dcbase, DisasContext, base);
1072 CPURISCVState *env = cs->env_ptr;
1073 RISCVCPU *cpu = RISCV_CPU(cs);
1074 uint32_t tb_flags = ctx->base.tb->flags;
1075
1076 ctx->pc_succ_insn = ctx->base.pc_first;
1077 ctx->mem_idx = FIELD_EX32(tb_flags, TB_FLAGS, MEM_IDX);
1078 ctx->mstatus_fs = tb_flags & TB_FLAGS_MSTATUS_FS;
1079 ctx->mstatus_vs = tb_flags & TB_FLAGS_MSTATUS_VS;
1080 ctx->priv_ver = env->priv_ver;
1081#if !defined(CONFIG_USER_ONLY)
1082 if (riscv_has_ext(env, RVH)) {
1083 ctx->virt_enabled = riscv_cpu_virt_enabled(env);
1084 } else {
1085 ctx->virt_enabled = false;
1086 }
1087#else
1088 ctx->virt_enabled = false;
1089#endif
1090 ctx->misa_ext = env->misa_ext;
1091 ctx->frm = -1;
1092 ctx->cfg_ptr = &(cpu->cfg);
1093 ctx->mstatus_hs_fs = FIELD_EX32(tb_flags, TB_FLAGS, MSTATUS_HS_FS);
1094 ctx->mstatus_hs_vs = FIELD_EX32(tb_flags, TB_FLAGS, MSTATUS_HS_VS);
1095 ctx->hlsx = FIELD_EX32(tb_flags, TB_FLAGS, HLSX);
1096 ctx->vill = FIELD_EX32(tb_flags, TB_FLAGS, VILL);
1097 ctx->sew = FIELD_EX32(tb_flags, TB_FLAGS, SEW);
1098 ctx->lmul = sextract32(FIELD_EX32(tb_flags, TB_FLAGS, LMUL), 0, 3);
1099 ctx->vta = FIELD_EX32(tb_flags, TB_FLAGS, VTA) && cpu->cfg.rvv_ta_all_1s;
1100 ctx->cfg_vta_all_1s = cpu->cfg.rvv_ta_all_1s;
1101 ctx->vstart = env->vstart;
1102 ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX);
1103 ctx->misa_mxl_max = env->misa_mxl_max;
1104 ctx->xl = FIELD_EX32(tb_flags, TB_FLAGS, XL);
1105 ctx->cs = cs;
1106 ctx->ntemp = 0;
1107 memset(ctx->temp, 0, sizeof(ctx->temp));
1108 ctx->nftemp = 0;
1109 memset(ctx->ftemp, 0, sizeof(ctx->ftemp));
1110 ctx->pm_mask_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_MASK_ENABLED);
1111 ctx->pm_base_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_BASE_ENABLED);
1112 ctx->zero = tcg_constant_tl(0);
1113}
1114
1115static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu)
1116{
1117}
1118
1119static void riscv_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu)
1120{
1121 DisasContext *ctx = container_of(dcbase, DisasContext, base);
1122
1123 tcg_gen_insn_start(ctx->base.pc_next, 0);
1124 ctx->insn_start = tcg_last_op();
1125}
1126
1127static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
1128{
1129 DisasContext *ctx = container_of(dcbase, DisasContext, base);
1130 CPURISCVState *env = cpu->env_ptr;
1131 uint16_t opcode16 = translator_lduw(env, &ctx->base, ctx->base.pc_next);
1132 int i;
1133
1134 ctx->ol = ctx->xl;
1135 decode_opc(env, ctx, opcode16);
1136 ctx->base.pc_next = ctx->pc_succ_insn;
1137
1138 for (i = ctx->ntemp - 1; i >= 0; --i) {
1139 tcg_temp_free(ctx->temp[i]);
1140 ctx->temp[i] = NULL;
1141 }
1142 ctx->ntemp = 0;
1143 for (i = ctx->nftemp - 1; i >= 0; --i) {
1144 tcg_temp_free_i64(ctx->ftemp[i]);
1145 ctx->ftemp[i] = NULL;
1146 }
1147 ctx->nftemp = 0;
1148
1149 if (ctx->base.is_jmp == DISAS_NEXT) {
1150 target_ulong page_start;
1151
1152 page_start = ctx->base.pc_first & TARGET_PAGE_MASK;
1153 if (ctx->base.pc_next - page_start >= TARGET_PAGE_SIZE) {
1154 ctx->base.is_jmp = DISAS_TOO_MANY;
1155 }
1156 }
1157}
1158
1159static void riscv_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
1160{
1161 DisasContext *ctx = container_of(dcbase, DisasContext, base);
1162
1163 switch (ctx->base.is_jmp) {
1164 case DISAS_TOO_MANY:
1165 gen_goto_tb(ctx, 0, ctx->base.pc_next);
1166 break;
1167 case DISAS_NORETURN:
1168 break;
1169 default:
1170 g_assert_not_reached();
1171 }
1172}
1173
1174static void riscv_tr_disas_log(const DisasContextBase *dcbase,
1175 CPUState *cpu, FILE *logfile)
1176{
1177#ifndef CONFIG_USER_ONLY
1178 RISCVCPU *rvcpu = RISCV_CPU(cpu);
1179 CPURISCVState *env = &rvcpu->env;
1180#endif
1181
1182 fprintf(logfile, "IN: %s\n", lookup_symbol(dcbase->pc_first));
1183#ifndef CONFIG_USER_ONLY
1184 fprintf(logfile, "Priv: "TARGET_FMT_ld"; Virt: "TARGET_FMT_ld"\n",
1185 env->priv, env->virt);
1186#endif
1187 target_disas(logfile, cpu, dcbase->pc_first, dcbase->tb->size);
1188}
1189
1190static const TranslatorOps riscv_tr_ops = {
1191 .init_disas_context = riscv_tr_init_disas_context,
1192 .tb_start = riscv_tr_tb_start,
1193 .insn_start = riscv_tr_insn_start,
1194 .translate_insn = riscv_tr_translate_insn,
1195 .tb_stop = riscv_tr_tb_stop,
1196 .disas_log = riscv_tr_disas_log,
1197};
1198
1199void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
1200{
1201 DisasContext ctx;
1202
1203 translator_loop(&riscv_tr_ops, &ctx.base, cs, tb, max_insns);
1204}
1205
1206void riscv_translate_init(void)
1207{
1208 int i;
1209
1210
1211
1212
1213
1214
1215 cpu_gpr[0] = NULL;
1216 cpu_gprh[0] = NULL;
1217
1218 for (i = 1; i < 32; i++) {
1219 cpu_gpr[i] = tcg_global_mem_new(cpu_env,
1220 offsetof(CPURISCVState, gpr[i]), riscv_int_regnames[i]);
1221 cpu_gprh[i] = tcg_global_mem_new(cpu_env,
1222 offsetof(CPURISCVState, gprh[i]), riscv_int_regnamesh[i]);
1223 }
1224
1225 for (i = 0; i < 32; i++) {
1226 cpu_fpr[i] = tcg_global_mem_new_i64(cpu_env,
1227 offsetof(CPURISCVState, fpr[i]), riscv_fpr_regnames[i]);
1228 }
1229
1230 cpu_pc = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, pc), "pc");
1231 cpu_vl = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, vl), "vl");
1232 cpu_vstart = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, vstart),
1233 "vstart");
1234 load_res = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_res),
1235 "load_res");
1236 load_val = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_val),
1237 "load_val");
1238
1239 pm_mask = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, cur_pmmask),
1240 "pmmask");
1241 pm_base = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, cur_pmbase),
1242 "pmbase");
1243}
1244