1#ifndef SPARC_CPU_H
2#define SPARC_CPU_H
3
4#include "qemu/bswap.h"
5#include "cpu-qom.h"
6#include "exec/cpu-defs.h"
7#include "qemu/cpu-float.h"
8
9#if !defined(TARGET_SPARC64)
10#define TARGET_DPREGS 16
11#else
12#define TARGET_DPREGS 32
13#endif
14
15
16
17
18enum {
19 WREG_O0,
20 WREG_O1,
21 WREG_O2,
22 WREG_O3,
23 WREG_O4,
24 WREG_O5,
25 WREG_O6,
26 WREG_O7,
27
28 WREG_L0,
29 WREG_L1,
30 WREG_L2,
31 WREG_L3,
32 WREG_L4,
33 WREG_L5,
34 WREG_L6,
35 WREG_L7,
36
37 WREG_I0,
38 WREG_I1,
39 WREG_I2,
40 WREG_I3,
41 WREG_I4,
42 WREG_I5,
43 WREG_I6,
44 WREG_I7,
45
46 WREG_SP = WREG_O6,
47 WREG_FP = WREG_I6,
48};
49
50
51#ifndef TARGET_SPARC64
52#define TT_TFAULT 0x01
53#define TT_ILL_INSN 0x02
54#define TT_PRIV_INSN 0x03
55#define TT_NFPU_INSN 0x04
56#define TT_WIN_OVF 0x05
57#define TT_WIN_UNF 0x06
58#define TT_UNALIGNED 0x07
59#define TT_FP_EXCP 0x08
60#define TT_DFAULT 0x09
61#define TT_TOVF 0x0a
62#define TT_EXTINT 0x10
63#define TT_CODE_ACCESS 0x21
64#define TT_UNIMP_FLUSH 0x25
65#define TT_DATA_ACCESS 0x29
66#define TT_DIV_ZERO 0x2a
67#define TT_NCP_INSN 0x24
68#define TT_TRAP 0x80
69#else
70#define TT_POWER_ON_RESET 0x01
71#define TT_TFAULT 0x08
72#define TT_CODE_ACCESS 0x0a
73#define TT_ILL_INSN 0x10
74#define TT_UNIMP_FLUSH TT_ILL_INSN
75#define TT_PRIV_INSN 0x11
76#define TT_NFPU_INSN 0x20
77#define TT_FP_EXCP 0x21
78#define TT_TOVF 0x23
79#define TT_CLRWIN 0x24
80#define TT_DIV_ZERO 0x28
81#define TT_DFAULT 0x30
82#define TT_DATA_ACCESS 0x32
83#define TT_UNALIGNED 0x34
84#define TT_PRIV_ACT 0x37
85#define TT_INSN_REAL_TRANSLATION_MISS 0x3e
86#define TT_DATA_REAL_TRANSLATION_MISS 0x3f
87#define TT_EXTINT 0x40
88#define TT_IVEC 0x60
89#define TT_TMISS 0x64
90#define TT_DMISS 0x68
91#define TT_DPROT 0x6c
92#define TT_SPILL 0x80
93#define TT_FILL 0xc0
94#define TT_WOTHER (1 << 5)
95#define TT_TRAP 0x100
96#define TT_HTRAP 0x180
97#endif
98
99#define PSR_NEG_SHIFT 23
100#define PSR_NEG (1 << PSR_NEG_SHIFT)
101#define PSR_ZERO_SHIFT 22
102#define PSR_ZERO (1 << PSR_ZERO_SHIFT)
103#define PSR_OVF_SHIFT 21
104#define PSR_OVF (1 << PSR_OVF_SHIFT)
105#define PSR_CARRY_SHIFT 20
106#define PSR_CARRY (1 << PSR_CARRY_SHIFT)
107#define PSR_ICC (PSR_NEG|PSR_ZERO|PSR_OVF|PSR_CARRY)
108#if !defined(TARGET_SPARC64)
109#define PSR_EF (1<<12)
110#define PSR_PIL 0xf00
111#define PSR_S (1<<7)
112#define PSR_PS (1<<6)
113#define PSR_ET (1<<5)
114#define PSR_CWP 0x1f
115#endif
116
117#define CC_SRC (env->cc_src)
118#define CC_SRC2 (env->cc_src2)
119#define CC_DST (env->cc_dst)
120#define CC_OP (env->cc_op)
121
122
123
124
125
126
127enum {
128 CC_OP_DYNAMIC,
129 CC_OP_FLAGS,
130 CC_OP_DIV,
131 CC_OP_ADD,
132 CC_OP_ADDX,
133 CC_OP_TADD,
134 CC_OP_TADDTV,
135 CC_OP_SUB,
136 CC_OP_SUBX,
137 CC_OP_TSUB,
138 CC_OP_TSUBTV,
139 CC_OP_LOGIC,
140 CC_OP_NB,
141};
142
143
144#define TBR_BASE_MASK 0xfffff000
145
146#if defined(TARGET_SPARC64)
147#define PS_TCT (1<<12)
148#define PS_IG (1<<11)
149#define PS_MG (1<<10)
150#define PS_CLE (1<<9)
151#define PS_TLE (1<<8)
152#define PS_RMO (1<<7)
153#define PS_RED (1<<5)
154#define PS_PEF (1<<4)
155#define PS_AM (1<<3)
156#define PS_PRIV (1<<2)
157#define PS_IE (1<<1)
158#define PS_AG (1<<0)
159
160#define FPRS_DL (1 << 0)
161#define FPRS_DU (1 << 1)
162#define FPRS_FEF (1 << 2)
163
164#define HS_PRIV (1<<2)
165#endif
166
167
168#define FSR_RD1 (1ULL << 31)
169#define FSR_RD0 (1ULL << 30)
170#define FSR_RD_MASK (FSR_RD1 | FSR_RD0)
171#define FSR_RD_NEAREST 0
172#define FSR_RD_ZERO FSR_RD0
173#define FSR_RD_POS FSR_RD1
174#define FSR_RD_NEG (FSR_RD1 | FSR_RD0)
175
176#define FSR_NVM (1ULL << 27)
177#define FSR_OFM (1ULL << 26)
178#define FSR_UFM (1ULL << 25)
179#define FSR_DZM (1ULL << 24)
180#define FSR_NXM (1ULL << 23)
181#define FSR_TEM_MASK (FSR_NVM | FSR_OFM | FSR_UFM | FSR_DZM | FSR_NXM)
182
183#define FSR_NVA (1ULL << 9)
184#define FSR_OFA (1ULL << 8)
185#define FSR_UFA (1ULL << 7)
186#define FSR_DZA (1ULL << 6)
187#define FSR_NXA (1ULL << 5)
188#define FSR_AEXC_MASK (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA)
189
190#define FSR_NVC (1ULL << 4)
191#define FSR_OFC (1ULL << 3)
192#define FSR_UFC (1ULL << 2)
193#define FSR_DZC (1ULL << 1)
194#define FSR_NXC (1ULL << 0)
195#define FSR_CEXC_MASK (FSR_NVC | FSR_OFC | FSR_UFC | FSR_DZC | FSR_NXC)
196
197#define FSR_FTT2 (1ULL << 16)
198#define FSR_FTT1 (1ULL << 15)
199#define FSR_FTT0 (1ULL << 14)
200
201
202#ifdef TARGET_SPARC64
203#define FSR_FTT_NMASK 0xfffffffffffe3fffULL
204#define FSR_FTT_CEXC_NMASK 0xfffffffffffe3fe0ULL
205#define FSR_LDFSR_OLDMASK 0x0000003f000fc000ULL
206#define FSR_LDXFSR_MASK 0x0000003fcfc00fffULL
207#define FSR_LDXFSR_OLDMASK 0x00000000000fc000ULL
208#else
209#define FSR_FTT_NMASK 0xfffe3fffULL
210#define FSR_FTT_CEXC_NMASK 0xfffe3fe0ULL
211#define FSR_LDFSR_OLDMASK 0x000fc000ULL
212#endif
213#define FSR_LDFSR_MASK 0xcfc00fffULL
214#define FSR_FTT_IEEE_EXCP (1ULL << 14)
215#define FSR_FTT_UNIMPFPOP (3ULL << 14)
216#define FSR_FTT_SEQ_ERROR (4ULL << 14)
217#define FSR_FTT_INVAL_FPR (6ULL << 14)
218
219#define FSR_FCC1_SHIFT 11
220#define FSR_FCC1 (1ULL << FSR_FCC1_SHIFT)
221#define FSR_FCC0_SHIFT 10
222#define FSR_FCC0 (1ULL << FSR_FCC0_SHIFT)
223
224
225#define MMU_E (1<<0)
226#define MMU_NF (1<<1)
227
228#define PTE_ENTRYTYPE_MASK 3
229#define PTE_ACCESS_MASK 0x1c
230#define PTE_ACCESS_SHIFT 2
231#define PTE_PPN_SHIFT 7
232#define PTE_ADDR_MASK 0xffffff00
233
234#define PG_ACCESSED_BIT 5
235#define PG_MODIFIED_BIT 6
236#define PG_CACHE_BIT 7
237
238#define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT)
239#define PG_MODIFIED_MASK (1 << PG_MODIFIED_BIT)
240#define PG_CACHE_MASK (1 << PG_CACHE_BIT)
241
242
243#define MIN_NWINDOWS 3
244#define MAX_NWINDOWS 32
245
246#ifdef TARGET_SPARC64
247typedef struct trap_state {
248 uint64_t tpc;
249 uint64_t tnpc;
250 uint64_t tstate;
251 uint32_t tt;
252} trap_state;
253#endif
254#define TARGET_INSN_START_EXTRA_WORDS 1
255
256struct sparc_def_t {
257 const char *name;
258 target_ulong iu_version;
259 uint32_t fpu_version;
260 uint32_t mmu_version;
261 uint32_t mmu_bm;
262 uint32_t mmu_ctpr_mask;
263 uint32_t mmu_cxr_mask;
264 uint32_t mmu_sfsr_mask;
265 uint32_t mmu_trcr_mask;
266 uint32_t mxcc_version;
267 uint32_t features;
268 uint32_t nwindows;
269 uint32_t maxtl;
270};
271
272#define CPU_FEATURE_FLOAT (1 << 0)
273#define CPU_FEATURE_FLOAT128 (1 << 1)
274#define CPU_FEATURE_SWAP (1 << 2)
275#define CPU_FEATURE_MUL (1 << 3)
276#define CPU_FEATURE_DIV (1 << 4)
277#define CPU_FEATURE_FLUSH (1 << 5)
278#define CPU_FEATURE_FSQRT (1 << 6)
279#define CPU_FEATURE_FMUL (1 << 7)
280#define CPU_FEATURE_VIS1 (1 << 8)
281#define CPU_FEATURE_VIS2 (1 << 9)
282#define CPU_FEATURE_FSMULD (1 << 10)
283#define CPU_FEATURE_HYPV (1 << 11)
284#define CPU_FEATURE_CMT (1 << 12)
285#define CPU_FEATURE_GL (1 << 13)
286#define CPU_FEATURE_TA0_SHUTDOWN (1 << 14)
287#define CPU_FEATURE_ASR17 (1 << 15)
288#define CPU_FEATURE_CACHE_CTRL (1 << 16)
289#define CPU_FEATURE_POWERDOWN (1 << 17)
290#define CPU_FEATURE_CASA (1 << 18)
291
292#ifndef TARGET_SPARC64
293#define CPU_DEFAULT_FEATURES (CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | \
294 CPU_FEATURE_MUL | CPU_FEATURE_DIV | \
295 CPU_FEATURE_FLUSH | CPU_FEATURE_FSQRT | \
296 CPU_FEATURE_FMUL | CPU_FEATURE_FSMULD)
297#else
298#define CPU_DEFAULT_FEATURES (CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | \
299 CPU_FEATURE_MUL | CPU_FEATURE_DIV | \
300 CPU_FEATURE_FLUSH | CPU_FEATURE_FSQRT | \
301 CPU_FEATURE_FMUL | CPU_FEATURE_VIS1 | \
302 CPU_FEATURE_VIS2 | CPU_FEATURE_FSMULD | \
303 CPU_FEATURE_CASA)
304enum {
305 mmu_us_12,
306 mmu_us_3,
307 mmu_us_4,
308 mmu_sun4v,
309};
310#endif
311
312#define TTE_VALID_BIT (1ULL << 63)
313#define TTE_NFO_BIT (1ULL << 60)
314#define TTE_IE_BIT (1ULL << 59)
315#define TTE_USED_BIT (1ULL << 41)
316#define TTE_LOCKED_BIT (1ULL << 6)
317#define TTE_SIDEEFFECT_BIT (1ULL << 3)
318#define TTE_PRIV_BIT (1ULL << 2)
319#define TTE_W_OK_BIT (1ULL << 1)
320#define TTE_GLOBAL_BIT (1ULL << 0)
321
322#define TTE_NFO_BIT_UA2005 (1ULL << 62)
323#define TTE_USED_BIT_UA2005 (1ULL << 47)
324#define TTE_LOCKED_BIT_UA2005 (1ULL << 61)
325#define TTE_SIDEEFFECT_BIT_UA2005 (1ULL << 11)
326#define TTE_PRIV_BIT_UA2005 (1ULL << 8)
327#define TTE_W_OK_BIT_UA2005 (1ULL << 6)
328
329#define TTE_IS_VALID(tte) ((tte) & TTE_VALID_BIT)
330#define TTE_IS_NFO(tte) ((tte) & TTE_NFO_BIT)
331#define TTE_IS_IE(tte) ((tte) & TTE_IE_BIT)
332#define TTE_IS_USED(tte) ((tte) & TTE_USED_BIT)
333#define TTE_IS_LOCKED(tte) ((tte) & TTE_LOCKED_BIT)
334#define TTE_IS_SIDEEFFECT(tte) ((tte) & TTE_SIDEEFFECT_BIT)
335#define TTE_IS_SIDEEFFECT_UA2005(tte) ((tte) & TTE_SIDEEFFECT_BIT_UA2005)
336#define TTE_IS_PRIV(tte) ((tte) & TTE_PRIV_BIT)
337#define TTE_IS_W_OK(tte) ((tte) & TTE_W_OK_BIT)
338
339#define TTE_IS_NFO_UA2005(tte) ((tte) & TTE_NFO_BIT_UA2005)
340#define TTE_IS_USED_UA2005(tte) ((tte) & TTE_USED_BIT_UA2005)
341#define TTE_IS_LOCKED_UA2005(tte) ((tte) & TTE_LOCKED_BIT_UA2005)
342#define TTE_IS_SIDEEFFECT_UA2005(tte) ((tte) & TTE_SIDEEFFECT_BIT_UA2005)
343#define TTE_IS_PRIV_UA2005(tte) ((tte) & TTE_PRIV_BIT_UA2005)
344#define TTE_IS_W_OK_UA2005(tte) ((tte) & TTE_W_OK_BIT_UA2005)
345
346#define TTE_IS_GLOBAL(tte) ((tte) & TTE_GLOBAL_BIT)
347
348#define TTE_SET_USED(tte) ((tte) |= TTE_USED_BIT)
349#define TTE_SET_UNUSED(tte) ((tte) &= ~TTE_USED_BIT)
350
351#define TTE_PGSIZE(tte) (((tte) >> 61) & 3ULL)
352#define TTE_PGSIZE_UA2005(tte) ((tte) & 7ULL)
353#define TTE_PA(tte) ((tte) & 0x1ffffffe000ULL)
354
355
356#define TLB_UST1_IS_REAL_BIT (1ULL << 9)
357#define TLB_UST1_IS_SUN4V_BIT (1ULL << 10)
358
359#define SFSR_NF_BIT (1ULL << 24)
360#define SFSR_TM_BIT (1ULL << 15)
361#define SFSR_FT_VA_IMMU_BIT (1ULL << 13)
362#define SFSR_FT_VA_DMMU_BIT (1ULL << 12)
363#define SFSR_FT_NFO_BIT (1ULL << 11)
364#define SFSR_FT_ILL_BIT (1ULL << 10)
365#define SFSR_FT_ATOMIC_BIT (1ULL << 9)
366#define SFSR_FT_NF_E_BIT (1ULL << 8)
367#define SFSR_FT_PRIV_BIT (1ULL << 7)
368#define SFSR_PR_BIT (1ULL << 3)
369#define SFSR_WRITE_BIT (1ULL << 2)
370#define SFSR_OW_BIT (1ULL << 1)
371#define SFSR_VALID_BIT (1ULL << 0)
372
373#define SFSR_ASI_SHIFT 16
374#define SFSR_ASI_MASK (0xffULL << SFSR_ASI_SHIFT)
375#define SFSR_CT_PRIMARY (0ULL << 4)
376#define SFSR_CT_SECONDARY (1ULL << 4)
377#define SFSR_CT_NUCLEUS (2ULL << 4)
378#define SFSR_CT_NOTRANS (3ULL << 4)
379#define SFSR_CT_MASK (3ULL << 4)
380
381
382
383
384
385
386#define CACHE_STATE_MASK 0x3
387#define CACHE_DISABLED 0x0
388#define CACHE_FROZEN 0x1
389#define CACHE_ENABLED 0x3
390
391
392
393#define CACHE_CTRL_IF (1 << 4)
394#define CACHE_CTRL_DF (1 << 5)
395#define CACHE_CTRL_DP (1 << 14)
396#define CACHE_CTRL_IP (1 << 15)
397#define CACHE_CTRL_IB (1 << 16)
398#define CACHE_CTRL_FI (1 << 21)
399#define CACHE_CTRL_FD (1 << 22)
400#define CACHE_CTRL_DS (1 << 23)
401
402#define CONVERT_BIT(X, SRC, DST) \
403 (SRC > DST ? (X) / (SRC / DST) & (DST) : ((X) & SRC) * (DST / SRC))
404
405typedef struct SparcTLBEntry {
406 uint64_t tag;
407 uint64_t tte;
408} SparcTLBEntry;
409
410struct CPUTimer
411{
412 const char *name;
413 uint32_t frequency;
414 uint32_t disabled;
415 uint64_t disabled_mask;
416 uint32_t npt;
417 uint64_t npt_mask;
418 int64_t clock_offset;
419 QEMUTimer *qtimer;
420};
421
422typedef struct CPUTimer CPUTimer;
423
424typedef struct CPUArchState CPUSPARCState;
425#if defined(TARGET_SPARC64)
426typedef union {
427 uint64_t mmuregs[16];
428 struct {
429 uint64_t tsb_tag_target;
430 uint64_t mmu_primary_context;
431 uint64_t mmu_secondary_context;
432 uint64_t sfsr;
433 uint64_t sfar;
434 uint64_t tsb;
435 uint64_t tag_access;
436 uint64_t virtual_watchpoint;
437 uint64_t physical_watchpoint;
438 uint64_t sun4v_ctx_config[2];
439 uint64_t sun4v_tsb_pointers[4];
440 };
441} SparcV9MMU;
442#endif
443struct CPUArchState {
444 target_ulong gregs[8];
445 target_ulong *regwptr;
446 target_ulong pc;
447 target_ulong npc;
448 target_ulong y;
449
450
451 target_ulong cc_src, cc_src2;
452 target_ulong cc_dst;
453 uint32_t cc_op;
454
455 target_ulong cond;
456
457
458 uint32_t psr;
459 target_ulong fsr;
460 CPU_DoubleU fpr[TARGET_DPREGS];
461 uint32_t cwp;
462
463#if !defined(TARGET_SPARC64) || defined(TARGET_ABI32)
464 uint32_t wim;
465#endif
466 target_ulong tbr;
467#if !defined(TARGET_SPARC64)
468 int psrs;
469 int psrps;
470 int psret;
471#endif
472 uint32_t psrpil;
473 uint32_t pil_in;
474#if !defined(TARGET_SPARC64)
475 int psref;
476#endif
477 int interrupt_index;
478
479 target_ulong regbase[MAX_NWINDOWS * 16 + 8];
480
481
482 struct {} end_reset_fields;
483
484
485 target_ulong version;
486 uint32_t nwindows;
487
488
489#if defined(TARGET_SPARC64)
490 uint64_t lsu;
491#define DMMU_E 0x8
492#define IMMU_E 0x4
493 SparcV9MMU immu;
494 SparcV9MMU dmmu;
495 SparcTLBEntry itlb[64];
496 SparcTLBEntry dtlb[64];
497 uint32_t mmu_version;
498#else
499 uint32_t mmuregs[32];
500 uint64_t mxccdata[4];
501 uint64_t mxccregs[8];
502 uint32_t mmubpctrv, mmubpctrc, mmubpctrs;
503 uint64_t mmubpaction;
504 uint64_t mmubpregs[4];
505 uint64_t prom_addr;
506#endif
507
508 float128 qt0, qt1;
509 float_status fp_status;
510#if defined(TARGET_SPARC64)
511#define MAXTL_MAX 8
512#define MAXTL_MASK (MAXTL_MAX - 1)
513 trap_state ts[MAXTL_MAX];
514 uint32_t xcc;
515 uint32_t asi;
516 uint32_t pstate;
517 uint32_t tl;
518 uint32_t maxtl;
519 uint32_t cansave, canrestore, otherwin, wstate, cleanwin;
520 uint64_t agregs[8];
521 uint64_t bgregs[8];
522 uint64_t igregs[8];
523 uint64_t mgregs[8];
524 uint64_t glregs[8 * MAXTL_MAX];
525 uint64_t fprs;
526 uint64_t tick_cmpr, stick_cmpr;
527 CPUTimer *tick, *stick;
528#define TICK_NPT_MASK 0x8000000000000000ULL
529#define TICK_INT_DIS 0x8000000000000000ULL
530 uint64_t gsr;
531 uint32_t gl;
532
533 uint64_t hpstate, htstate[MAXTL_MAX], hintp, htba, hver, hstick_cmpr, ssr;
534 uint64_t scratch[8];
535 CPUTimer *hstick;
536
537 uint64_t ivec_status;
538 uint64_t ivec_data[3];
539 uint32_t softint;
540#define SOFTINT_TIMER 1
541#define SOFTINT_STIMER (1 << 16)
542#define SOFTINT_INTRMASK (0xFFFE)
543#define SOFTINT_REG_MASK (SOFTINT_STIMER|SOFTINT_INTRMASK|SOFTINT_TIMER)
544#endif
545 sparc_def_t def;
546
547 void *irq_manager;
548 void (*qemu_irq_ack)(CPUSPARCState *env, void *irq_manager, int intno);
549
550
551 uint32_t cache_control;
552};
553
554
555
556
557
558
559
560struct ArchCPU {
561
562 CPUState parent_obj;
563
564
565 CPUNegativeOffsetState neg;
566 CPUSPARCState env;
567};
568
569
570#ifndef CONFIG_USER_ONLY
571extern const VMStateDescription vmstate_sparc_cpu;
572#endif
573
574void sparc_cpu_do_interrupt(CPUState *cpu);
575hwaddr sparc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
576int sparc_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
577int sparc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
578G_NORETURN void sparc_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
579 MMUAccessType access_type,
580 int mmu_idx,
581 uintptr_t retaddr);
582G_NORETURN void cpu_raise_exception_ra(CPUSPARCState *, int, uintptr_t);
583
584#ifndef NO_CPU_IO_DEFS
585
586void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu);
587void sparc_cpu_list(void);
588
589bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
590 MMUAccessType access_type, int mmu_idx,
591 bool probe, uintptr_t retaddr);
592target_ulong mmu_probe(CPUSPARCState *env, target_ulong address, int mmulev);
593void dump_mmu(CPUSPARCState *env);
594
595#if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY)
596int sparc_cpu_memory_rw_debug(CPUState *cpu, vaddr addr,
597 uint8_t *buf, int len, bool is_write);
598#endif
599
600
601
602void sparc_tcg_init(void);
603
604
605
606
607target_ulong cpu_get_psr(CPUSPARCState *env1);
608void cpu_put_psr(CPUSPARCState *env1, target_ulong val);
609void cpu_put_psr_raw(CPUSPARCState *env1, target_ulong val);
610#ifdef TARGET_SPARC64
611void cpu_change_pstate(CPUSPARCState *env1, uint32_t new_pstate);
612void cpu_gl_switch_gregs(CPUSPARCState *env, uint32_t new_gl);
613#endif
614int cpu_cwp_inc(CPUSPARCState *env1, int cwp);
615int cpu_cwp_dec(CPUSPARCState *env1, int cwp);
616void cpu_set_cwp(CPUSPARCState *env1, int new_cwp);
617
618
619void cpu_check_irqs(CPUSPARCState *env);
620
621#if defined (TARGET_SPARC64)
622
623static inline int compare_masked(uint64_t x, uint64_t y, uint64_t mask)
624{
625 return (x & mask) == (y & mask);
626}
627
628#define MMU_CONTEXT_BITS 13
629#define MMU_CONTEXT_MASK ((1 << MMU_CONTEXT_BITS) - 1)
630
631static inline int tlb_compare_context(const SparcTLBEntry *tlb,
632 uint64_t context)
633{
634 return compare_masked(context, tlb->tag, MMU_CONTEXT_MASK);
635}
636
637#endif
638#endif
639
640
641#if !defined(CONFIG_USER_ONLY)
642void sparc_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
643 vaddr addr, unsigned size,
644 MMUAccessType access_type,
645 int mmu_idx, MemTxAttrs attrs,
646 MemTxResult response, uintptr_t retaddr);
647#if defined(TARGET_SPARC64)
648hwaddr cpu_get_phys_page_nofault(CPUSPARCState *env, target_ulong addr,
649 int mmu_idx);
650#endif
651#endif
652
653#define SPARC_CPU_TYPE_SUFFIX "-" TYPE_SPARC_CPU
654#define SPARC_CPU_TYPE_NAME(model) model SPARC_CPU_TYPE_SUFFIX
655#define CPU_RESOLVING_TYPE TYPE_SPARC_CPU
656
657#define cpu_list sparc_cpu_list
658
659
660#if defined (TARGET_SPARC64)
661#define MMU_USER_IDX 0
662#define MMU_USER_SECONDARY_IDX 1
663#define MMU_KERNEL_IDX 2
664#define MMU_KERNEL_SECONDARY_IDX 3
665#define MMU_NUCLEUS_IDX 4
666#define MMU_PHYS_IDX 5
667#else
668#define MMU_USER_IDX 0
669#define MMU_KERNEL_IDX 1
670#define MMU_PHYS_IDX 2
671#endif
672
673#if defined (TARGET_SPARC64)
674static inline int cpu_has_hypervisor(CPUSPARCState *env1)
675{
676 return env1->def.features & CPU_FEATURE_HYPV;
677}
678
679static inline int cpu_hypervisor_mode(CPUSPARCState *env1)
680{
681 return cpu_has_hypervisor(env1) && (env1->hpstate & HS_PRIV);
682}
683
684static inline int cpu_supervisor_mode(CPUSPARCState *env1)
685{
686 return env1->pstate & PS_PRIV;
687}
688#else
689static inline int cpu_supervisor_mode(CPUSPARCState *env1)
690{
691 return env1->psrs;
692}
693#endif
694
695static inline int cpu_mmu_index(CPUSPARCState *env, bool ifetch)
696{
697#if defined(CONFIG_USER_ONLY)
698 return MMU_USER_IDX;
699#elif !defined(TARGET_SPARC64)
700 if ((env->mmuregs[0] & MMU_E) == 0) {
701 return MMU_PHYS_IDX;
702 } else {
703 return env->psrs;
704 }
705#else
706
707 if (ifetch
708 ? (env->lsu & IMMU_E) == 0 || (env->pstate & PS_RED) != 0
709 : (env->lsu & DMMU_E) == 0) {
710 return MMU_PHYS_IDX;
711 } else if (cpu_hypervisor_mode(env)) {
712 return MMU_PHYS_IDX;
713 } else if (env->tl > 0) {
714 return MMU_NUCLEUS_IDX;
715 } else if (cpu_supervisor_mode(env)) {
716 return MMU_KERNEL_IDX;
717 } else {
718 return MMU_USER_IDX;
719 }
720#endif
721}
722
723static inline int cpu_interrupts_enabled(CPUSPARCState *env1)
724{
725#if !defined (TARGET_SPARC64)
726 if (env1->psret != 0)
727 return 1;
728#else
729 if ((env1->pstate & PS_IE) && !cpu_hypervisor_mode(env1)) {
730 return 1;
731 }
732#endif
733
734 return 0;
735}
736
737static inline int cpu_pil_allowed(CPUSPARCState *env1, int pil)
738{
739#if !defined(TARGET_SPARC64)
740
741 return pil == 15 || pil > env1->psrpil;
742#else
743 return pil > env1->psrpil;
744#endif
745}
746
747#include "exec/cpu-all.h"
748
749#ifdef TARGET_SPARC64
750
751void cpu_tick_set_count(CPUTimer *timer, uint64_t count);
752uint64_t cpu_tick_get_count(CPUTimer *timer);
753void cpu_tick_set_limit(CPUTimer *timer, uint64_t limit);
754trap_state* cpu_tsptr(CPUSPARCState* env);
755#endif
756
757#define TB_FLAG_MMU_MASK 7
758#define TB_FLAG_FPU_ENABLED (1 << 4)
759#define TB_FLAG_AM_ENABLED (1 << 5)
760#define TB_FLAG_SUPER (1 << 6)
761#define TB_FLAG_HYPER (1 << 7)
762#define TB_FLAG_ASI_SHIFT 24
763
764static inline void cpu_get_tb_cpu_state(CPUSPARCState *env, target_ulong *pc,
765 target_ulong *cs_base, uint32_t *pflags)
766{
767 uint32_t flags;
768 *pc = env->pc;
769 *cs_base = env->npc;
770 flags = cpu_mmu_index(env, false);
771#ifndef CONFIG_USER_ONLY
772 if (cpu_supervisor_mode(env)) {
773 flags |= TB_FLAG_SUPER;
774 }
775#endif
776#ifdef TARGET_SPARC64
777#ifndef CONFIG_USER_ONLY
778 if (cpu_hypervisor_mode(env)) {
779 flags |= TB_FLAG_HYPER;
780 }
781#endif
782 if (env->pstate & PS_AM) {
783 flags |= TB_FLAG_AM_ENABLED;
784 }
785 if ((env->def.features & CPU_FEATURE_FLOAT)
786 && (env->pstate & PS_PEF)
787 && (env->fprs & FPRS_FEF)) {
788 flags |= TB_FLAG_FPU_ENABLED;
789 }
790 flags |= env->asi << TB_FLAG_ASI_SHIFT;
791#else
792 if ((env->def.features & CPU_FEATURE_FLOAT) && env->psref) {
793 flags |= TB_FLAG_FPU_ENABLED;
794 }
795#endif
796 *pflags = flags;
797}
798
799static inline bool tb_fpu_enabled(int tb_flags)
800{
801#if defined(CONFIG_USER_ONLY)
802 return true;
803#else
804 return tb_flags & TB_FLAG_FPU_ENABLED;
805#endif
806}
807
808static inline bool tb_am_enabled(int tb_flags)
809{
810#ifndef TARGET_SPARC64
811 return false;
812#else
813 return tb_flags & TB_FLAG_AM_ENABLED;
814#endif
815}
816
817#ifdef TARGET_SPARC64
818
819target_ulong cpu_get_ccr(CPUSPARCState *env1);
820void cpu_put_ccr(CPUSPARCState *env1, target_ulong val);
821target_ulong cpu_get_cwp64(CPUSPARCState *env1);
822void cpu_put_cwp64(CPUSPARCState *env1, int cwp);
823
824static inline uint64_t sparc64_tstate(CPUSPARCState *env)
825{
826 uint64_t tstate = (cpu_get_ccr(env) << 32) |
827 ((env->asi & 0xff) << 24) | ((env->pstate & 0xf3f) << 8) |
828 cpu_get_cwp64(env);
829
830 if (env->def.features & CPU_FEATURE_GL) {
831 tstate |= (env->gl & 7ULL) << 40;
832 }
833 return tstate;
834}
835#endif
836
837#endif
838