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26#ifndef ARM_TCG_TARGET_H
27#define ARM_TCG_TARGET_H
28
29extern int arm_arch;
30
31#define use_armv7_instructions (__ARM_ARCH >= 7 || arm_arch >= 7)
32
33#undef TCG_TARGET_STACK_GROWSUP
34#define TCG_TARGET_INSN_UNIT_SIZE 4
35#define TCG_TARGET_TLB_DISPLACEMENT_BITS 16
36#define MAX_CODE_GEN_BUFFER_SIZE UINT32_MAX
37
38typedef enum {
39 TCG_REG_R0 = 0,
40 TCG_REG_R1,
41 TCG_REG_R2,
42 TCG_REG_R3,
43 TCG_REG_R4,
44 TCG_REG_R5,
45 TCG_REG_R6,
46 TCG_REG_R7,
47 TCG_REG_R8,
48 TCG_REG_R9,
49 TCG_REG_R10,
50 TCG_REG_R11,
51 TCG_REG_R12,
52 TCG_REG_R13,
53 TCG_REG_R14,
54 TCG_REG_PC,
55
56 TCG_REG_Q0,
57 TCG_REG_Q1,
58 TCG_REG_Q2,
59 TCG_REG_Q3,
60 TCG_REG_Q4,
61 TCG_REG_Q5,
62 TCG_REG_Q6,
63 TCG_REG_Q7,
64 TCG_REG_Q8,
65 TCG_REG_Q9,
66 TCG_REG_Q10,
67 TCG_REG_Q11,
68 TCG_REG_Q12,
69 TCG_REG_Q13,
70 TCG_REG_Q14,
71 TCG_REG_Q15,
72
73 TCG_AREG0 = TCG_REG_R6,
74 TCG_REG_CALL_STACK = TCG_REG_R13,
75} TCGReg;
76
77#define TCG_TARGET_NB_REGS 32
78
79#ifdef __ARM_ARCH_EXT_IDIV__
80#define use_idiv_instructions 1
81#else
82extern bool use_idiv_instructions;
83#endif
84#ifdef __ARM_NEON__
85#define use_neon_instructions 1
86#else
87extern bool use_neon_instructions;
88#endif
89
90
91#define TCG_TARGET_STACK_ALIGN 8
92#define TCG_TARGET_CALL_ALIGN_ARGS 1
93#define TCG_TARGET_CALL_STACK_OFFSET 0
94
95
96#define TCG_TARGET_HAS_ext8s_i32 1
97#define TCG_TARGET_HAS_ext16s_i32 1
98#define TCG_TARGET_HAS_ext8u_i32 0
99#define TCG_TARGET_HAS_ext16u_i32 1
100#define TCG_TARGET_HAS_bswap16_i32 1
101#define TCG_TARGET_HAS_bswap32_i32 1
102#define TCG_TARGET_HAS_not_i32 1
103#define TCG_TARGET_HAS_neg_i32 1
104#define TCG_TARGET_HAS_rot_i32 1
105#define TCG_TARGET_HAS_andc_i32 1
106#define TCG_TARGET_HAS_orc_i32 0
107#define TCG_TARGET_HAS_eqv_i32 0
108#define TCG_TARGET_HAS_nand_i32 0
109#define TCG_TARGET_HAS_nor_i32 0
110#define TCG_TARGET_HAS_clz_i32 1
111#define TCG_TARGET_HAS_ctz_i32 use_armv7_instructions
112#define TCG_TARGET_HAS_ctpop_i32 0
113#define TCG_TARGET_HAS_deposit_i32 use_armv7_instructions
114#define TCG_TARGET_HAS_extract_i32 use_armv7_instructions
115#define TCG_TARGET_HAS_sextract_i32 use_armv7_instructions
116#define TCG_TARGET_HAS_extract2_i32 1
117#define TCG_TARGET_HAS_movcond_i32 1
118#define TCG_TARGET_HAS_mulu2_i32 1
119#define TCG_TARGET_HAS_muls2_i32 1
120#define TCG_TARGET_HAS_muluh_i32 0
121#define TCG_TARGET_HAS_mulsh_i32 0
122#define TCG_TARGET_HAS_div_i32 use_idiv_instructions
123#define TCG_TARGET_HAS_rem_i32 0
124#define TCG_TARGET_HAS_direct_jump 0
125#define TCG_TARGET_HAS_qemu_st8_i32 0
126
127#define TCG_TARGET_HAS_v64 use_neon_instructions
128#define TCG_TARGET_HAS_v128 use_neon_instructions
129#define TCG_TARGET_HAS_v256 0
130
131#define TCG_TARGET_HAS_andc_vec 1
132#define TCG_TARGET_HAS_orc_vec 1
133#define TCG_TARGET_HAS_nand_vec 0
134#define TCG_TARGET_HAS_nor_vec 0
135#define TCG_TARGET_HAS_eqv_vec 0
136#define TCG_TARGET_HAS_not_vec 1
137#define TCG_TARGET_HAS_neg_vec 1
138#define TCG_TARGET_HAS_abs_vec 1
139#define TCG_TARGET_HAS_roti_vec 0
140#define TCG_TARGET_HAS_rots_vec 0
141#define TCG_TARGET_HAS_rotv_vec 0
142#define TCG_TARGET_HAS_shi_vec 1
143#define TCG_TARGET_HAS_shs_vec 0
144#define TCG_TARGET_HAS_shv_vec 0
145#define TCG_TARGET_HAS_mul_vec 1
146#define TCG_TARGET_HAS_sat_vec 1
147#define TCG_TARGET_HAS_minmax_vec 1
148#define TCG_TARGET_HAS_bitsel_vec 1
149#define TCG_TARGET_HAS_cmpsel_vec 0
150
151#define TCG_TARGET_DEFAULT_MO (0)
152#define TCG_TARGET_HAS_MEMORY_BSWAP 0
153
154
155void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t);
156
157#define TCG_TARGET_NEED_LDST_LABELS
158#define TCG_TARGET_NEED_POOL_LABELS
159
160#endif
161