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13#include "qemu/osdep.h"
14#include "qemu/module.h"
15#include "qemu/units.h"
16#include "qapi/error.h"
17#include "hw/irq.h"
18#include "hw/pci/pci.h"
19#include "hw/pci/pci_bus.h"
20#include "hw/qdev-properties.h"
21#include "hw/pci-host/dino.h"
22#include "migration/vmstate.h"
23#include "trace.h"
24#include "qom/object.h"
25
26
27
28
29
30
31static void gsc_to_pci_forwarding(DinoState *s)
32{
33 uint32_t io_addr_en, tmp;
34 int enabled, i;
35
36 tmp = extract32(s->io_control, 7, 2);
37 enabled = (tmp == 0x01);
38 io_addr_en = s->io_addr_en;
39
40 io_addr_en &= ~(BIT(31) | BIT(0));
41
42 memory_region_transaction_begin();
43 for (i = 1; i < 31; i++) {
44 MemoryRegion *mem = &s->pci_mem_alias[i];
45 if (enabled && (io_addr_en & (1U << i))) {
46 if (!memory_region_is_mapped(mem)) {
47 uint32_t addr = 0xf0000000 + i * DINO_MEM_CHUNK_SIZE;
48 memory_region_add_subregion(get_system_memory(), addr, mem);
49 }
50 } else if (memory_region_is_mapped(mem)) {
51 memory_region_del_subregion(get_system_memory(), mem);
52 }
53 }
54 memory_region_transaction_commit();
55}
56
57static bool dino_chip_mem_valid(void *opaque, hwaddr addr,
58 unsigned size, bool is_write,
59 MemTxAttrs attrs)
60{
61 bool ret = false;
62
63 switch (addr) {
64 case DINO_IAR0:
65 case DINO_IAR1:
66 case DINO_IRR0:
67 case DINO_IRR1:
68 case DINO_IMR:
69 case DINO_IPR:
70 case DINO_ICR:
71 case DINO_ILR:
72 case DINO_IO_CONTROL:
73 case DINO_IO_FBB_EN:
74 case DINO_IO_ADDR_EN:
75 case DINO_PCI_IO_DATA:
76 case DINO_TOC_ADDR:
77 case DINO_GMASK ... DINO_PCISTS:
78 case DINO_MLTIM ... DINO_PCIWOR:
79 case DINO_TLTIM:
80 ret = true;
81 break;
82 case DINO_PCI_IO_DATA + 2:
83 ret = (size <= 2);
84 break;
85 case DINO_PCI_IO_DATA + 1:
86 case DINO_PCI_IO_DATA + 3:
87 ret = (size == 1);
88 }
89 trace_dino_chip_mem_valid(addr, ret);
90 return ret;
91}
92
93static MemTxResult dino_chip_read_with_attrs(void *opaque, hwaddr addr,
94 uint64_t *data, unsigned size,
95 MemTxAttrs attrs)
96{
97 DinoState *s = opaque;
98 PCIHostState *phb = PCI_HOST_BRIDGE(s);
99 MemTxResult ret = MEMTX_OK;
100 AddressSpace *io;
101 uint16_t ioaddr;
102 uint32_t val;
103
104 switch (addr) {
105 case DINO_PCI_IO_DATA ... DINO_PCI_IO_DATA + 3:
106
107 io = &address_space_io;
108 ioaddr = phb->config_reg + (addr & 3);
109 switch (size) {
110 case 1:
111 val = address_space_ldub(io, ioaddr, attrs, &ret);
112 break;
113 case 2:
114 val = address_space_lduw_be(io, ioaddr, attrs, &ret);
115 break;
116 case 4:
117 val = address_space_ldl_be(io, ioaddr, attrs, &ret);
118 break;
119 default:
120 g_assert_not_reached();
121 }
122 break;
123
124 case DINO_IO_FBB_EN:
125 val = s->io_fbb_en;
126 break;
127 case DINO_IO_ADDR_EN:
128 val = s->io_addr_en;
129 break;
130 case DINO_IO_CONTROL:
131 val = s->io_control;
132 break;
133
134 case DINO_IAR0:
135 val = s->iar0;
136 break;
137 case DINO_IAR1:
138 val = s->iar1;
139 break;
140 case DINO_IMR:
141 val = s->imr;
142 break;
143 case DINO_ICR:
144 val = s->icr;
145 break;
146 case DINO_IPR:
147 val = s->ipr;
148
149 s->ipr = 0;
150 break;
151 case DINO_ILR:
152 val = s->ilr;
153 break;
154 case DINO_IRR0:
155 val = s->ilr & s->imr & ~s->icr;
156 break;
157 case DINO_IRR1:
158 val = s->ilr & s->imr & s->icr;
159 break;
160 case DINO_TOC_ADDR:
161 val = s->toc_addr;
162 break;
163 case DINO_GMASK ... DINO_TLTIM:
164 val = s->reg800[(addr - DINO_GMASK) / 4];
165 if (addr == DINO_PAMR) {
166 val &= ~0x01;
167 }
168 if (addr == DINO_MLTIM) {
169 val &= ~0x07;
170 }
171 if (addr == DINO_BRDG_FEAT) {
172 val &= ~(0x10710E0ul | 8);
173 }
174 break;
175
176 default:
177
178 g_assert_not_reached();
179 }
180
181 trace_dino_chip_read(addr, val);
182 *data = val;
183 return ret;
184}
185
186static MemTxResult dino_chip_write_with_attrs(void *opaque, hwaddr addr,
187 uint64_t val, unsigned size,
188 MemTxAttrs attrs)
189{
190 DinoState *s = opaque;
191 PCIHostState *phb = PCI_HOST_BRIDGE(s);
192 AddressSpace *io;
193 MemTxResult ret;
194 uint16_t ioaddr;
195 int i;
196
197 trace_dino_chip_write(addr, val);
198
199 switch (addr) {
200 case DINO_IO_DATA ... DINO_PCI_IO_DATA + 3:
201
202 io = &address_space_io;
203 ioaddr = phb->config_reg + (addr & 3);
204 switch (size) {
205 case 1:
206 address_space_stb(io, ioaddr, val, attrs, &ret);
207 break;
208 case 2:
209 address_space_stw_be(io, ioaddr, val, attrs, &ret);
210 break;
211 case 4:
212 address_space_stl_be(io, ioaddr, val, attrs, &ret);
213 break;
214 default:
215 g_assert_not_reached();
216 }
217 return ret;
218
219 case DINO_IO_FBB_EN:
220 s->io_fbb_en = val & 0x03;
221 break;
222 case DINO_IO_ADDR_EN:
223 s->io_addr_en = val;
224 gsc_to_pci_forwarding(s);
225 break;
226 case DINO_IO_CONTROL:
227 s->io_control = val;
228 gsc_to_pci_forwarding(s);
229 break;
230
231 case DINO_IAR0:
232 s->iar0 = val;
233 break;
234 case DINO_IAR1:
235 s->iar1 = val;
236 break;
237 case DINO_IMR:
238 s->imr = val;
239 break;
240 case DINO_ICR:
241 s->icr = val;
242 break;
243 case DINO_IPR:
244
245 s->ipr = 0;
246 break;
247 case DINO_TOC_ADDR:
248
249 s->toc_addr = 0xFFFA0030 | (val & 0x1e000);
250 break;
251
252 case DINO_ILR:
253 case DINO_IRR0:
254 case DINO_IRR1:
255
256 break;
257
258 case DINO_GMASK ... DINO_TLTIM:
259 i = (addr - DINO_GMASK) / 4;
260 val &= reg800_keep_bits[i];
261 s->reg800[i] = val;
262 break;
263
264 default:
265
266 g_assert_not_reached();
267 }
268 return MEMTX_OK;
269}
270
271static const MemoryRegionOps dino_chip_ops = {
272 .read_with_attrs = dino_chip_read_with_attrs,
273 .write_with_attrs = dino_chip_write_with_attrs,
274 .endianness = DEVICE_BIG_ENDIAN,
275 .valid = {
276 .min_access_size = 1,
277 .max_access_size = 4,
278 .accepts = dino_chip_mem_valid,
279 },
280 .impl = {
281 .min_access_size = 1,
282 .max_access_size = 4,
283 },
284};
285
286static const VMStateDescription vmstate_dino = {
287 .name = "Dino",
288 .version_id = 2,
289 .minimum_version_id = 1,
290 .fields = (VMStateField[]) {
291 VMSTATE_UINT32(iar0, DinoState),
292 VMSTATE_UINT32(iar1, DinoState),
293 VMSTATE_UINT32(imr, DinoState),
294 VMSTATE_UINT32(ipr, DinoState),
295 VMSTATE_UINT32(icr, DinoState),
296 VMSTATE_UINT32(ilr, DinoState),
297 VMSTATE_UINT32(io_fbb_en, DinoState),
298 VMSTATE_UINT32(io_addr_en, DinoState),
299 VMSTATE_UINT32(io_control, DinoState),
300 VMSTATE_UINT32(toc_addr, DinoState),
301 VMSTATE_END_OF_LIST()
302 }
303};
304
305
306
307static uint64_t dino_config_data_read(void *opaque, hwaddr addr, unsigned len)
308{
309 PCIHostState *s = opaque;
310 return pci_data_read(s->bus, s->config_reg | (addr & 3), len);
311}
312
313static void dino_config_data_write(void *opaque, hwaddr addr,
314 uint64_t val, unsigned len)
315{
316 PCIHostState *s = opaque;
317 pci_data_write(s->bus, s->config_reg | (addr & 3), val, len);
318}
319
320static const MemoryRegionOps dino_config_data_ops = {
321 .read = dino_config_data_read,
322 .write = dino_config_data_write,
323 .endianness = DEVICE_LITTLE_ENDIAN,
324};
325
326static uint64_t dino_config_addr_read(void *opaque, hwaddr addr, unsigned len)
327{
328 DinoState *s = opaque;
329 return s->config_reg_dino;
330}
331
332static void dino_config_addr_write(void *opaque, hwaddr addr,
333 uint64_t val, unsigned len)
334{
335 PCIHostState *s = opaque;
336 DinoState *ds = opaque;
337 ds->config_reg_dino = val;
338 s->config_reg = val & ~3U;
339}
340
341static const MemoryRegionOps dino_config_addr_ops = {
342 .read = dino_config_addr_read,
343 .write = dino_config_addr_write,
344 .valid.min_access_size = 4,
345 .valid.max_access_size = 4,
346 .endianness = DEVICE_BIG_ENDIAN,
347};
348
349static AddressSpace *dino_pcihost_set_iommu(PCIBus *bus, void *opaque,
350 int devfn)
351{
352 DinoState *s = opaque;
353
354 return &s->bm_as;
355}
356
357
358
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364
365
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367
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369
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371
372
373static void dino_set_irq(void *opaque, int irq, int level)
374{
375 DinoState *s = opaque;
376 uint32_t bit = 1u << irq;
377 uint32_t old_ilr = s->ilr;
378
379 if (level) {
380 uint32_t ena = bit & ~old_ilr;
381 s->ipr |= ena;
382 s->ilr = old_ilr | bit;
383 if (ena & s->imr) {
384 uint32_t iar = (ena & s->icr ? s->iar1 : s->iar0);
385 stl_be_phys(&address_space_memory, iar & -32, iar & 31);
386 }
387 } else {
388 s->ilr = old_ilr & ~bit;
389 }
390}
391
392static int dino_pci_map_irq(PCIDevice *d, int irq_num)
393{
394 int slot = PCI_SLOT(d->devfn);
395
396 assert(irq_num >= 0 && irq_num <= 3);
397
398 return slot & 0x03;
399}
400
401static void dino_pcihost_reset(DeviceState *dev)
402{
403 DinoState *s = DINO_PCI_HOST_BRIDGE(dev);
404
405 s->iar0 = s->iar1 = 0xFFFB0000 + 3;
406 s->toc_addr = 0xFFFA0030;
407}
408
409static void dino_pcihost_realize(DeviceState *dev, Error **errp)
410{
411 DinoState *s = DINO_PCI_HOST_BRIDGE(dev);
412
413
414 memory_region_init(&s->bm, OBJECT(s), "bm-dino", 4 * GiB);
415 memory_region_init_alias(&s->bm_ram_alias, OBJECT(s),
416 "bm-system", s->memory_as, 0,
417 0xf0000000 + DINO_MEM_CHUNK_SIZE);
418 memory_region_init_alias(&s->bm_pci_alias, OBJECT(s),
419 "bm-pci", &s->pci_mem,
420 0xf0000000 + DINO_MEM_CHUNK_SIZE,
421 30 * DINO_MEM_CHUNK_SIZE);
422 memory_region_init_alias(&s->bm_cpu_alias, OBJECT(s),
423 "bm-cpu", s->memory_as, 0xfff00000,
424 0xfffff);
425 memory_region_add_subregion(&s->bm, 0,
426 &s->bm_ram_alias);
427 memory_region_add_subregion(&s->bm,
428 0xf0000000 + DINO_MEM_CHUNK_SIZE,
429 &s->bm_pci_alias);
430 memory_region_add_subregion(&s->bm, 0xfff00000,
431 &s->bm_cpu_alias);
432
433 address_space_init(&s->bm_as, &s->bm, "pci-bm");
434}
435
436static void dino_pcihost_unrealize(DeviceState *dev)
437{
438 DinoState *s = DINO_PCI_HOST_BRIDGE(dev);
439
440 address_space_destroy(&s->bm_as);
441}
442
443static void dino_pcihost_init(Object *obj)
444{
445 DinoState *s = DINO_PCI_HOST_BRIDGE(obj);
446 PCIHostState *phb = PCI_HOST_BRIDGE(obj);
447 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
448 int i;
449
450
451 memory_region_init_io(&s->this_mem, OBJECT(s), &dino_chip_ops,
452 s, "dino", 4096);
453
454
455 memory_region_init_io(&phb->conf_mem, OBJECT(phb),
456 &dino_config_addr_ops, DEVICE(s),
457 "pci-conf-idx", 4);
458 memory_region_init_io(&phb->data_mem, OBJECT(phb),
459 &dino_config_data_ops, DEVICE(s),
460 "pci-conf-data", 4);
461 memory_region_add_subregion(&s->this_mem, DINO_PCI_CONFIG_ADDR,
462 &phb->conf_mem);
463 memory_region_add_subregion(&s->this_mem, DINO_CONFIG_DATA,
464 &phb->data_mem);
465
466
467 memory_region_init(&s->pci_mem, OBJECT(s), "pci-memory", 4 * GiB);
468
469 phb->bus = pci_register_root_bus(DEVICE(s), "pci",
470 dino_set_irq, dino_pci_map_irq, s,
471 &s->pci_mem, get_system_io(),
472 PCI_DEVFN(0, 0), 32, TYPE_PCI_BUS);
473
474
475 for (i = 1; i < 31; i++) {
476 uint32_t addr = 0xf0000000 + i * DINO_MEM_CHUNK_SIZE;
477 char *name = g_strdup_printf("PCI Outbound Window %d", i);
478 memory_region_init_alias(&s->pci_mem_alias[i], OBJECT(s),
479 name, &s->pci_mem, addr,
480 DINO_MEM_CHUNK_SIZE);
481 g_free(name);
482 }
483
484 pci_setup_iommu(phb->bus, dino_pcihost_set_iommu, s);
485
486 sysbus_init_mmio(sbd, &s->this_mem);
487
488 qdev_init_gpio_in(DEVICE(obj), dino_set_irq, DINO_IRQS);
489}
490
491static Property dino_pcihost_properties[] = {
492 DEFINE_PROP_LINK("memory-as", DinoState, memory_as, TYPE_MEMORY_REGION,
493 MemoryRegion *),
494 DEFINE_PROP_END_OF_LIST(),
495};
496
497static void dino_pcihost_class_init(ObjectClass *klass, void *data)
498{
499 DeviceClass *dc = DEVICE_CLASS(klass);
500
501 dc->reset = dino_pcihost_reset;
502 dc->realize = dino_pcihost_realize;
503 dc->unrealize = dino_pcihost_unrealize;
504 device_class_set_props(dc, dino_pcihost_properties);
505 dc->vmsd = &vmstate_dino;
506}
507
508static const TypeInfo dino_pcihost_info = {
509 .name = TYPE_DINO_PCI_HOST_BRIDGE,
510 .parent = TYPE_PCI_HOST_BRIDGE,
511 .instance_init = dino_pcihost_init,
512 .instance_size = sizeof(DinoState),
513 .class_init = dino_pcihost_class_init,
514};
515
516static void dino_register_types(void)
517{
518 type_register_static(&dino_pcihost_info);
519}
520
521type_init(dino_register_types)
522
