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20#include "qemu/osdep.h"
21#include "sysemu/reset.h"
22#include "qapi/error.h"
23#include "qemu/log.h"
24#include "qemu/module.h"
25#include "target/ppc/cpu.h"
26#include "hw/ppc/ppc.h"
27#include "hw/ppc/pnv.h"
28#include "hw/ppc/pnv_core.h"
29#include "hw/ppc/pnv_xscom.h"
30#include "hw/ppc/xics.h"
31#include "hw/qdev-properties.h"
32#include "helper_regs.h"
33
34static const char *pnv_core_cpu_typename(PnvCore *pc)
35{
36 const char *core_type = object_class_get_name(object_get_class(OBJECT(pc)));
37 int len = strlen(core_type) - strlen(PNV_CORE_TYPE_SUFFIX);
38 char *s = g_strdup_printf(POWERPC_CPU_TYPE_NAME("%.*s"), len, core_type);
39 const char *cpu_type = object_class_get_name(object_class_by_name(s));
40 g_free(s);
41 return cpu_type;
42}
43
44static void pnv_core_cpu_reset(PnvCore *pc, PowerPCCPU *cpu)
45{
46 CPUState *cs = CPU(cpu);
47 CPUPPCState *env = &cpu->env;
48 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(pc->chip);
49
50 cpu_reset(cs);
51
52
53
54
55
56 env->gpr[3] = PNV_FDT_ADDR;
57 env->nip = 0x10;
58 env->msr |= MSR_HVB;
59 env->spr[SPR_HRMOR] = pc->hrmor;
60 hreg_compute_hflags(env);
61 ppc_maybe_interrupt(env);
62
63 pcc->intc_reset(pc->chip, cpu);
64}
65
66
67
68
69#define PNV_XSCOM_EX_DTS_RESULT0 0x50000
70#define PNV_XSCOM_EX_DTS_RESULT1 0x50001
71
72static uint64_t pnv_core_power8_xscom_read(void *opaque, hwaddr addr,
73 unsigned int width)
74{
75 uint32_t offset = addr >> 3;
76 uint64_t val = 0;
77
78
79 switch (offset) {
80 case PNV_XSCOM_EX_DTS_RESULT0:
81 val = 0x26f024f023f0000ull;
82 break;
83 case PNV_XSCOM_EX_DTS_RESULT1:
84 val = 0x24f000000000000ull;
85 break;
86 default:
87 qemu_log_mask(LOG_UNIMP, "Warning: reading reg=0x%" HWADDR_PRIx "\n",
88 addr);
89 }
90
91 return val;
92}
93
94static void pnv_core_power8_xscom_write(void *opaque, hwaddr addr, uint64_t val,
95 unsigned int width)
96{
97 qemu_log_mask(LOG_UNIMP, "Warning: writing to reg=0x%" HWADDR_PRIx "\n",
98 addr);
99}
100
101static const MemoryRegionOps pnv_core_power8_xscom_ops = {
102 .read = pnv_core_power8_xscom_read,
103 .write = pnv_core_power8_xscom_write,
104 .valid.min_access_size = 8,
105 .valid.max_access_size = 8,
106 .impl.min_access_size = 8,
107 .impl.max_access_size = 8,
108 .endianness = DEVICE_BIG_ENDIAN,
109};
110
111
112
113
114
115#define PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_HYP 0xf010d
116#define PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_OTR 0xf010a
117
118static uint64_t pnv_core_power9_xscom_read(void *opaque, hwaddr addr,
119 unsigned int width)
120{
121 uint32_t offset = addr >> 3;
122 uint64_t val = 0;
123
124
125 switch (offset) {
126 case PNV_XSCOM_EX_DTS_RESULT0:
127 val = 0x26f024f023f0000ull;
128 break;
129 case PNV_XSCOM_EX_DTS_RESULT1:
130 val = 0x24f000000000000ull;
131 break;
132 case PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_HYP:
133 case PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_OTR:
134 val = 0x0;
135 break;
136 default:
137 qemu_log_mask(LOG_UNIMP, "Warning: reading reg=0x%" HWADDR_PRIx "\n",
138 addr);
139 }
140
141 return val;
142}
143
144static void pnv_core_power9_xscom_write(void *opaque, hwaddr addr, uint64_t val,
145 unsigned int width)
146{
147 uint32_t offset = addr >> 3;
148
149 switch (offset) {
150 case PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_HYP:
151 case PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_OTR:
152 break;
153 default:
154 qemu_log_mask(LOG_UNIMP, "Warning: writing to reg=0x%" HWADDR_PRIx "\n",
155 addr);
156 }
157}
158
159static const MemoryRegionOps pnv_core_power9_xscom_ops = {
160 .read = pnv_core_power9_xscom_read,
161 .write = pnv_core_power9_xscom_write,
162 .valid.min_access_size = 8,
163 .valid.max_access_size = 8,
164 .impl.min_access_size = 8,
165 .impl.max_access_size = 8,
166 .endianness = DEVICE_BIG_ENDIAN,
167};
168
169static void pnv_core_cpu_realize(PnvCore *pc, PowerPCCPU *cpu, Error **errp)
170{
171 CPUPPCState *env = &cpu->env;
172 int core_pir;
173 int thread_index = 0;
174 ppc_spr_t *pir = &env->spr_cb[SPR_PIR];
175 Error *local_err = NULL;
176 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(pc->chip);
177
178 if (!qdev_realize(DEVICE(cpu), NULL, errp)) {
179 return;
180 }
181
182 pcc->intc_create(pc->chip, cpu, &local_err);
183 if (local_err) {
184 error_propagate(errp, local_err);
185 return;
186 }
187
188 core_pir = object_property_get_uint(OBJECT(pc), "pir", &error_abort);
189
190
191
192
193
194
195 pir->default_value = core_pir + thread_index;
196
197
198 cpu_ppc_tb_init(env, PNV_TIMEBASE_FREQ);
199}
200
201static void pnv_core_reset(void *dev)
202{
203 CPUCore *cc = CPU_CORE(dev);
204 PnvCore *pc = PNV_CORE(dev);
205 int i;
206
207 for (i = 0; i < cc->nr_threads; i++) {
208 pnv_core_cpu_reset(pc, pc->threads[i]);
209 }
210}
211
212static void pnv_core_realize(DeviceState *dev, Error **errp)
213{
214 PnvCore *pc = PNV_CORE(OBJECT(dev));
215 PnvCoreClass *pcc = PNV_CORE_GET_CLASS(pc);
216 CPUCore *cc = CPU_CORE(OBJECT(dev));
217 const char *typename = pnv_core_cpu_typename(pc);
218 Error *local_err = NULL;
219 void *obj;
220 int i, j;
221 char name[32];
222
223 assert(pc->chip);
224
225 pc->threads = g_new(PowerPCCPU *, cc->nr_threads);
226 for (i = 0; i < cc->nr_threads; i++) {
227 PowerPCCPU *cpu;
228
229 obj = object_new(typename);
230 cpu = POWERPC_CPU(obj);
231
232 pc->threads[i] = POWERPC_CPU(obj);
233
234 snprintf(name, sizeof(name), "thread[%d]", i);
235 object_property_add_child(OBJECT(pc), name, obj);
236
237 cpu->machine_data = g_new0(PnvCPUState, 1);
238
239 object_unref(obj);
240 }
241
242 for (j = 0; j < cc->nr_threads; j++) {
243 pnv_core_cpu_realize(pc, pc->threads[j], &local_err);
244 if (local_err) {
245 goto err;
246 }
247 }
248
249 snprintf(name, sizeof(name), "xscom-core.%d", cc->core_id);
250
251 pnv_xscom_region_init(&pc->xscom_regs, OBJECT(dev), pcc->xscom_ops,
252 pc, name, PNV_XSCOM_EX_SIZE);
253
254 qemu_register_reset(pnv_core_reset, pc);
255 return;
256
257err:
258 while (--i >= 0) {
259 obj = OBJECT(pc->threads[i]);
260 object_unparent(obj);
261 }
262 g_free(pc->threads);
263 error_propagate(errp, local_err);
264}
265
266static void pnv_core_cpu_unrealize(PnvCore *pc, PowerPCCPU *cpu)
267{
268 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
269 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(pc->chip);
270
271 pcc->intc_destroy(pc->chip, cpu);
272 cpu_remove_sync(CPU(cpu));
273 cpu->machine_data = NULL;
274 g_free(pnv_cpu);
275 object_unparent(OBJECT(cpu));
276}
277
278static void pnv_core_unrealize(DeviceState *dev)
279{
280 PnvCore *pc = PNV_CORE(dev);
281 CPUCore *cc = CPU_CORE(dev);
282 int i;
283
284 qemu_unregister_reset(pnv_core_reset, pc);
285
286 for (i = 0; i < cc->nr_threads; i++) {
287 pnv_core_cpu_unrealize(pc, pc->threads[i]);
288 }
289 g_free(pc->threads);
290}
291
292static Property pnv_core_properties[] = {
293 DEFINE_PROP_UINT32("pir", PnvCore, pir, 0),
294 DEFINE_PROP_UINT64("hrmor", PnvCore, hrmor, 0),
295 DEFINE_PROP_LINK("chip", PnvCore, chip, TYPE_PNV_CHIP, PnvChip *),
296 DEFINE_PROP_END_OF_LIST(),
297};
298
299static void pnv_core_power8_class_init(ObjectClass *oc, void *data)
300{
301 PnvCoreClass *pcc = PNV_CORE_CLASS(oc);
302
303 pcc->xscom_ops = &pnv_core_power8_xscom_ops;
304}
305
306static void pnv_core_power9_class_init(ObjectClass *oc, void *data)
307{
308 PnvCoreClass *pcc = PNV_CORE_CLASS(oc);
309
310 pcc->xscom_ops = &pnv_core_power9_xscom_ops;
311}
312
313static void pnv_core_power10_class_init(ObjectClass *oc, void *data)
314{
315 PnvCoreClass *pcc = PNV_CORE_CLASS(oc);
316
317
318 pcc->xscom_ops = &pnv_core_power9_xscom_ops;
319}
320
321static void pnv_core_class_init(ObjectClass *oc, void *data)
322{
323 DeviceClass *dc = DEVICE_CLASS(oc);
324
325 dc->realize = pnv_core_realize;
326 dc->unrealize = pnv_core_unrealize;
327 device_class_set_props(dc, pnv_core_properties);
328 dc->user_creatable = false;
329}
330
331#define DEFINE_PNV_CORE_TYPE(family, cpu_model) \
332 { \
333 .parent = TYPE_PNV_CORE, \
334 .name = PNV_CORE_TYPE_NAME(cpu_model), \
335 .class_init = pnv_core_##family##_class_init, \
336 }
337
338static const TypeInfo pnv_core_infos[] = {
339 {
340 .name = TYPE_PNV_CORE,
341 .parent = TYPE_CPU_CORE,
342 .instance_size = sizeof(PnvCore),
343 .class_size = sizeof(PnvCoreClass),
344 .class_init = pnv_core_class_init,
345 .abstract = true,
346 },
347 DEFINE_PNV_CORE_TYPE(power8, "power8e_v2.1"),
348 DEFINE_PNV_CORE_TYPE(power8, "power8_v2.0"),
349 DEFINE_PNV_CORE_TYPE(power8, "power8nvl_v1.0"),
350 DEFINE_PNV_CORE_TYPE(power9, "power9_v2.0"),
351 DEFINE_PNV_CORE_TYPE(power10, "power10_v2.0"),
352};
353
354DEFINE_TYPES(pnv_core_infos)
355
356
357
358
359
360#define P9X_EX_NCU_SPEC_BAR 0x11010
361
362static uint64_t pnv_quad_xscom_read(void *opaque, hwaddr addr,
363 unsigned int width)
364{
365 uint32_t offset = addr >> 3;
366 uint64_t val = -1;
367
368 switch (offset) {
369 case P9X_EX_NCU_SPEC_BAR:
370 case P9X_EX_NCU_SPEC_BAR + 0x400:
371 val = 0;
372 break;
373 default:
374 qemu_log_mask(LOG_UNIMP, "%s: writing @0x%08x\n", __func__,
375 offset);
376 }
377
378 return val;
379}
380
381static void pnv_quad_xscom_write(void *opaque, hwaddr addr, uint64_t val,
382 unsigned int width)
383{
384 uint32_t offset = addr >> 3;
385
386 switch (offset) {
387 case P9X_EX_NCU_SPEC_BAR:
388 case P9X_EX_NCU_SPEC_BAR + 0x400:
389 break;
390 default:
391 qemu_log_mask(LOG_UNIMP, "%s: writing @0x%08x\n", __func__,
392 offset);
393 }
394}
395
396static const MemoryRegionOps pnv_quad_xscom_ops = {
397 .read = pnv_quad_xscom_read,
398 .write = pnv_quad_xscom_write,
399 .valid.min_access_size = 8,
400 .valid.max_access_size = 8,
401 .impl.min_access_size = 8,
402 .impl.max_access_size = 8,
403 .endianness = DEVICE_BIG_ENDIAN,
404};
405
406static void pnv_quad_realize(DeviceState *dev, Error **errp)
407{
408 PnvQuad *eq = PNV_QUAD(dev);
409 char name[32];
410
411 snprintf(name, sizeof(name), "xscom-quad.%d", eq->quad_id);
412 pnv_xscom_region_init(&eq->xscom_regs, OBJECT(dev), &pnv_quad_xscom_ops,
413 eq, name, PNV9_XSCOM_EQ_SIZE);
414}
415
416static Property pnv_quad_properties[] = {
417 DEFINE_PROP_UINT32("quad-id", PnvQuad, quad_id, 0),
418 DEFINE_PROP_END_OF_LIST(),
419};
420
421static void pnv_quad_class_init(ObjectClass *oc, void *data)
422{
423 DeviceClass *dc = DEVICE_CLASS(oc);
424
425 dc->realize = pnv_quad_realize;
426 device_class_set_props(dc, pnv_quad_properties);
427 dc->user_creatable = false;
428}
429
430static const TypeInfo pnv_quad_info = {
431 .name = TYPE_PNV_QUAD,
432 .parent = TYPE_DEVICE,
433 .instance_size = sizeof(PnvQuad),
434 .class_init = pnv_quad_class_init,
435};
436
437static void pnv_core_register_types(void)
438{
439 type_register_static(&pnv_quad_info);
440}
441
442type_init(pnv_core_register_types)
443
