1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26#include "qemu/osdep.h"
27#include "hw/isa/isa.h"
28#include "hw/qdev-properties.h"
29#include "hw/rtc/m48t59.h"
30#include "m48t59-internal.h"
31#include "qapi/error.h"
32#include "qemu/module.h"
33#include "qom/object.h"
34
35#define TYPE_M48TXX_ISA "isa-m48txx"
36typedef struct M48txxISADeviceClass M48txxISADeviceClass;
37typedef struct M48txxISAState M48txxISAState;
38DECLARE_OBJ_CHECKERS(M48txxISAState, M48txxISADeviceClass,
39 M48TXX_ISA, TYPE_M48TXX_ISA)
40
41struct M48txxISAState {
42 ISADevice parent_obj;
43 M48t59State state;
44 uint32_t io_base;
45 uint8_t isairq;
46 MemoryRegion io;
47};
48
49struct M48txxISADeviceClass {
50 ISADeviceClass parent_class;
51 M48txxInfo info;
52};
53
54static M48txxInfo m48txx_isa_info[] = {
55 {
56 .bus_name = "isa-m48t59",
57 .model = 59,
58 .size = 0x2000,
59 }
60};
61
62static uint32_t m48txx_isa_read(Nvram *obj, uint32_t addr)
63{
64 M48txxISAState *d = M48TXX_ISA(obj);
65 return m48t59_read(&d->state, addr);
66}
67
68static void m48txx_isa_write(Nvram *obj, uint32_t addr, uint32_t val)
69{
70 M48txxISAState *d = M48TXX_ISA(obj);
71 m48t59_write(&d->state, addr, val);
72}
73
74static void m48txx_isa_toggle_lock(Nvram *obj, int lock)
75{
76 M48txxISAState *d = M48TXX_ISA(obj);
77 m48t59_toggle_lock(&d->state, lock);
78}
79
80static Property m48t59_isa_properties[] = {
81 DEFINE_PROP_INT32("base-year", M48txxISAState, state.base_year, 0),
82 DEFINE_PROP_UINT32("iobase", M48txxISAState, io_base, 0x74),
83 DEFINE_PROP_UINT8("irq", M48txxISAState, isairq, 8),
84 DEFINE_PROP_END_OF_LIST(),
85};
86
87static void m48t59_reset_isa(DeviceState *d)
88{
89 M48txxISAState *isa = M48TXX_ISA(d);
90 M48t59State *NVRAM = &isa->state;
91
92 m48t59_reset_common(NVRAM);
93}
94
95static void m48t59_isa_realize(DeviceState *dev, Error **errp)
96{
97 M48txxISADeviceClass *u = M48TXX_ISA_GET_CLASS(dev);
98 ISADevice *isadev = ISA_DEVICE(dev);
99 M48txxISAState *d = M48TXX_ISA(dev);
100 M48t59State *s = &d->state;
101
102 if (d->isairq >= ISA_NUM_IRQS) {
103 error_setg(errp, "Maximum value for \"irq\" is: %u", ISA_NUM_IRQS - 1);
104 return;
105 }
106
107 s->model = u->info.model;
108 s->size = u->info.size;
109 s->IRQ = isa_get_irq(isadev, d->isairq);
110 m48t59_realize_common(s, errp);
111 memory_region_init_io(&d->io, OBJECT(dev), &m48t59_io_ops, s, "m48t59", 4);
112 if (d->io_base != 0) {
113 isa_register_ioport(isadev, &d->io, d->io_base);
114 }
115}
116
117static void m48txx_isa_class_init(ObjectClass *klass, void *data)
118{
119 DeviceClass *dc = DEVICE_CLASS(klass);
120 NvramClass *nc = NVRAM_CLASS(klass);
121
122 dc->realize = m48t59_isa_realize;
123 dc->reset = m48t59_reset_isa;
124 device_class_set_props(dc, m48t59_isa_properties);
125 nc->read = m48txx_isa_read;
126 nc->write = m48txx_isa_write;
127 nc->toggle_lock = m48txx_isa_toggle_lock;
128}
129
130static void m48txx_isa_concrete_class_init(ObjectClass *klass, void *data)
131{
132 M48txxISADeviceClass *u = M48TXX_ISA_CLASS(klass);
133 M48txxInfo *info = data;
134
135 u->info = *info;
136}
137
138static const TypeInfo m48txx_isa_type_info = {
139 .name = TYPE_M48TXX_ISA,
140 .parent = TYPE_ISA_DEVICE,
141 .instance_size = sizeof(M48txxISAState),
142 .abstract = true,
143 .class_init = m48txx_isa_class_init,
144 .interfaces = (InterfaceInfo[]) {
145 { TYPE_NVRAM },
146 { }
147 }
148};
149
150static void m48t59_isa_register_types(void)
151{
152 TypeInfo isa_type_info = {
153 .parent = TYPE_M48TXX_ISA,
154 .class_size = sizeof(M48txxISADeviceClass),
155 .class_init = m48txx_isa_concrete_class_init,
156 };
157 int i;
158
159 type_register_static(&m48txx_isa_type_info);
160
161 for (i = 0; i < ARRAY_SIZE(m48txx_isa_info); i++) {
162 isa_type_info.name = m48txx_isa_info[i].bus_name;
163 isa_type_info.class_data = &m48txx_isa_info[i];
164 type_register(&isa_type_info);
165 }
166}
167
168type_init(m48t59_isa_register_types)
169