1/* SPDX-License-Identifier: GPL-2.0-or-later */ 2/* 3 * QEMU LoongArch CPU 4 * 5 * Copyright (c) 2021 Loongson Technology Corporation Limited 6 */ 7 8#ifndef HW_LS7A_H 9#define HW_LS7A_H 10 11#include "hw/pci/pci.h" 12#include "hw/pci/pcie_host.h" 13#include "hw/pci-host/pam.h" 14#include "qemu/units.h" 15#include "qemu/range.h" 16#include "qom/object.h" 17 18#define VIRT_PCI_MEM_BASE 0x40000000UL 19#define VIRT_PCI_MEM_SIZE 0x40000000UL 20#define VIRT_PCI_IO_OFFSET 0x4000 21#define VIRT_PCI_CFG_BASE 0x20000000 22#define VIRT_PCI_CFG_SIZE 0x08000000 23#define VIRT_PCI_IO_BASE 0x18004000UL 24#define VIRT_PCI_IO_SIZE 0xC000 25 26#define VIRT_PCH_REG_BASE 0x10000000UL 27#define VIRT_IOAPIC_REG_BASE (VIRT_PCH_REG_BASE) 28#define VIRT_PCH_MSI_ADDR_LOW 0x2FF00000UL 29 30/* 31 * According to the kernel pch irq start from 64 offset 32 * 0 ~ 16 irqs used for non-pci device while 16 ~ 64 irqs 33 * used for pci device. 34 */ 35#define PCH_PIC_IRQ_OFFSET 64 36#define VIRT_DEVICE_IRQS 16 37#define VIRT_PCI_IRQS 48 38#define VIRT_UART_IRQ (PCH_PIC_IRQ_OFFSET + 2) 39#define VIRT_UART_BASE 0x1fe001e0 40#define VIRT_UART_SIZE 0X100 41#define VIRT_RTC_IRQ (PCH_PIC_IRQ_OFFSET + 3) 42#define VIRT_MISC_REG_BASE (VIRT_PCH_REG_BASE + 0x00080000) 43#define VIRT_RTC_REG_BASE (VIRT_MISC_REG_BASE + 0x00050100) 44#define VIRT_RTC_LEN 0x100 45#define VIRT_SCI_IRQ (PCH_PIC_IRQ_OFFSET + 4) 46 47#define VIRT_PLATFORM_BUS_BASEADDRESS 0x16000000 48#define VIRT_PLATFORM_BUS_SIZE 0x2000000 49#define VIRT_PLATFORM_BUS_NUM_IRQS 2 50#define VIRT_PLATFORM_BUS_IRQ 69 51#endif 52