1
2
3
4
5#ifndef VIRTIO_SND_IF_H
6#define VIRTIO_SND_IF_H
7
8#include "standard-headers/linux/virtio_types.h"
9
10
11
12
13struct virtio_snd_config {
14
15 uint32_t jacks;
16
17 uint32_t streams;
18
19 uint32_t chmaps;
20};
21
22enum {
23
24 VIRTIO_SND_VQ_CONTROL = 0,
25 VIRTIO_SND_VQ_EVENT,
26 VIRTIO_SND_VQ_TX,
27 VIRTIO_SND_VQ_RX,
28
29 VIRTIO_SND_VQ_MAX
30};
31
32
33
34
35
36
37enum {
38 VIRTIO_SND_D_OUTPUT = 0,
39 VIRTIO_SND_D_INPUT
40};
41
42enum {
43
44 VIRTIO_SND_R_JACK_INFO = 1,
45 VIRTIO_SND_R_JACK_REMAP,
46
47
48 VIRTIO_SND_R_PCM_INFO = 0x0100,
49 VIRTIO_SND_R_PCM_SET_PARAMS,
50 VIRTIO_SND_R_PCM_PREPARE,
51 VIRTIO_SND_R_PCM_RELEASE,
52 VIRTIO_SND_R_PCM_START,
53 VIRTIO_SND_R_PCM_STOP,
54
55
56 VIRTIO_SND_R_CHMAP_INFO = 0x0200,
57
58
59 VIRTIO_SND_EVT_JACK_CONNECTED = 0x1000,
60 VIRTIO_SND_EVT_JACK_DISCONNECTED,
61
62
63 VIRTIO_SND_EVT_PCM_PERIOD_ELAPSED = 0x1100,
64 VIRTIO_SND_EVT_PCM_XRUN,
65
66
67 VIRTIO_SND_S_OK = 0x8000,
68 VIRTIO_SND_S_BAD_MSG,
69 VIRTIO_SND_S_NOT_SUPP,
70 VIRTIO_SND_S_IO_ERR
71};
72
73
74struct virtio_snd_hdr {
75 uint32_t code;
76};
77
78
79struct virtio_snd_event {
80
81 struct virtio_snd_hdr hdr;
82
83 uint32_t data;
84};
85
86
87struct virtio_snd_query_info {
88
89 struct virtio_snd_hdr hdr;
90
91 uint32_t start_id;
92
93 uint32_t count;
94
95 uint32_t size;
96};
97
98
99struct virtio_snd_info {
100
101 uint32_t hda_fn_nid;
102};
103
104
105
106
107struct virtio_snd_jack_hdr {
108
109 struct virtio_snd_hdr hdr;
110
111 uint32_t jack_id;
112};
113
114
115enum {
116 VIRTIO_SND_JACK_F_REMAP = 0
117};
118
119struct virtio_snd_jack_info {
120
121 struct virtio_snd_info hdr;
122
123 uint32_t features;
124
125 uint32_t hda_reg_defconf;
126
127 uint32_t hda_reg_caps;
128
129 uint8_t connected;
130
131 uint8_t padding[7];
132};
133
134
135struct virtio_snd_jack_remap {
136
137 struct virtio_snd_jack_hdr hdr;
138
139 uint32_t association;
140
141 uint32_t sequence;
142};
143
144
145
146
147struct virtio_snd_pcm_hdr {
148
149 struct virtio_snd_hdr hdr;
150
151 uint32_t stream_id;
152};
153
154
155enum {
156 VIRTIO_SND_PCM_F_SHMEM_HOST = 0,
157 VIRTIO_SND_PCM_F_SHMEM_GUEST,
158 VIRTIO_SND_PCM_F_MSG_POLLING,
159 VIRTIO_SND_PCM_F_EVT_SHMEM_PERIODS,
160 VIRTIO_SND_PCM_F_EVT_XRUNS
161};
162
163
164enum {
165
166 VIRTIO_SND_PCM_FMT_IMA_ADPCM = 0,
167 VIRTIO_SND_PCM_FMT_MU_LAW,
168 VIRTIO_SND_PCM_FMT_A_LAW,
169 VIRTIO_SND_PCM_FMT_S8,
170 VIRTIO_SND_PCM_FMT_U8,
171 VIRTIO_SND_PCM_FMT_S16,
172 VIRTIO_SND_PCM_FMT_U16,
173 VIRTIO_SND_PCM_FMT_S18_3,
174 VIRTIO_SND_PCM_FMT_U18_3,
175 VIRTIO_SND_PCM_FMT_S20_3,
176 VIRTIO_SND_PCM_FMT_U20_3,
177 VIRTIO_SND_PCM_FMT_S24_3,
178 VIRTIO_SND_PCM_FMT_U24_3,
179 VIRTIO_SND_PCM_FMT_S20,
180 VIRTIO_SND_PCM_FMT_U20,
181 VIRTIO_SND_PCM_FMT_S24,
182 VIRTIO_SND_PCM_FMT_U24,
183 VIRTIO_SND_PCM_FMT_S32,
184 VIRTIO_SND_PCM_FMT_U32,
185 VIRTIO_SND_PCM_FMT_FLOAT,
186 VIRTIO_SND_PCM_FMT_FLOAT64,
187
188 VIRTIO_SND_PCM_FMT_DSD_U8,
189 VIRTIO_SND_PCM_FMT_DSD_U16,
190 VIRTIO_SND_PCM_FMT_DSD_U32,
191 VIRTIO_SND_PCM_FMT_IEC958_SUBFRAME
192};
193
194
195enum {
196 VIRTIO_SND_PCM_RATE_5512 = 0,
197 VIRTIO_SND_PCM_RATE_8000,
198 VIRTIO_SND_PCM_RATE_11025,
199 VIRTIO_SND_PCM_RATE_16000,
200 VIRTIO_SND_PCM_RATE_22050,
201 VIRTIO_SND_PCM_RATE_32000,
202 VIRTIO_SND_PCM_RATE_44100,
203 VIRTIO_SND_PCM_RATE_48000,
204 VIRTIO_SND_PCM_RATE_64000,
205 VIRTIO_SND_PCM_RATE_88200,
206 VIRTIO_SND_PCM_RATE_96000,
207 VIRTIO_SND_PCM_RATE_176400,
208 VIRTIO_SND_PCM_RATE_192000,
209 VIRTIO_SND_PCM_RATE_384000
210};
211
212struct virtio_snd_pcm_info {
213
214 struct virtio_snd_info hdr;
215
216 uint32_t features;
217
218 uint64_t formats;
219
220 uint64_t rates;
221
222 uint8_t direction;
223
224 uint8_t channels_min;
225
226 uint8_t channels_max;
227
228 uint8_t padding[5];
229};
230
231
232struct virtio_snd_pcm_set_params {
233
234 struct virtio_snd_pcm_hdr hdr;
235
236 uint32_t buffer_bytes;
237
238 uint32_t period_bytes;
239
240 uint32_t features;
241
242 uint8_t channels;
243
244 uint8_t format;
245
246 uint8_t rate;
247
248 uint8_t padding;
249};
250
251
252
253
254
255
256struct virtio_snd_pcm_xfer {
257
258 uint32_t stream_id;
259};
260
261
262struct virtio_snd_pcm_status {
263
264 uint32_t status;
265
266 uint32_t latency_bytes;
267};
268
269
270
271
272struct virtio_snd_chmap_hdr {
273
274 struct virtio_snd_hdr hdr;
275
276 uint32_t chmap_id;
277};
278
279
280enum {
281 VIRTIO_SND_CHMAP_NONE = 0,
282 VIRTIO_SND_CHMAP_NA,
283 VIRTIO_SND_CHMAP_MONO,
284 VIRTIO_SND_CHMAP_FL,
285 VIRTIO_SND_CHMAP_FR,
286 VIRTIO_SND_CHMAP_RL,
287 VIRTIO_SND_CHMAP_RR,
288 VIRTIO_SND_CHMAP_FC,
289 VIRTIO_SND_CHMAP_LFE,
290 VIRTIO_SND_CHMAP_SL,
291 VIRTIO_SND_CHMAP_SR,
292 VIRTIO_SND_CHMAP_RC,
293 VIRTIO_SND_CHMAP_FLC,
294 VIRTIO_SND_CHMAP_FRC,
295 VIRTIO_SND_CHMAP_RLC,
296 VIRTIO_SND_CHMAP_RRC,
297 VIRTIO_SND_CHMAP_FLW,
298 VIRTIO_SND_CHMAP_FRW,
299 VIRTIO_SND_CHMAP_FLH,
300 VIRTIO_SND_CHMAP_FCH,
301 VIRTIO_SND_CHMAP_FRH,
302 VIRTIO_SND_CHMAP_TC,
303 VIRTIO_SND_CHMAP_TFL,
304 VIRTIO_SND_CHMAP_TFR,
305 VIRTIO_SND_CHMAP_TFC,
306 VIRTIO_SND_CHMAP_TRL,
307 VIRTIO_SND_CHMAP_TRR,
308 VIRTIO_SND_CHMAP_TRC,
309 VIRTIO_SND_CHMAP_TFLC,
310 VIRTIO_SND_CHMAP_TFRC,
311 VIRTIO_SND_CHMAP_TSL,
312 VIRTIO_SND_CHMAP_TSR,
313 VIRTIO_SND_CHMAP_LLFE,
314 VIRTIO_SND_CHMAP_RLFE,
315 VIRTIO_SND_CHMAP_BC,
316 VIRTIO_SND_CHMAP_BLC,
317 VIRTIO_SND_CHMAP_BRC
318};
319
320
321#define VIRTIO_SND_CHMAP_MAX_SIZE 18
322
323struct virtio_snd_chmap_info {
324
325 struct virtio_snd_info hdr;
326
327 uint8_t direction;
328
329 uint8_t channels;
330
331 uint8_t positions[VIRTIO_SND_CHMAP_MAX_SIZE];
332};
333
334#endif
335