1/* 2 * xtensa/config/core-isa.h -- HAL definitions that are dependent on Xtensa 3 * processor CORE configuration 4 * 5 * See <xtensa/config/core.h>, which includes this file, for more details. 6 */ 7 8/* Xtensa processor core configuration information. 9 10 Copyright (c) 1999-2019 Tensilica Inc. 11 12 Permission is hereby granted, free of charge, to any person obtaining 13 a copy of this software and associated documentation files (the 14 "Software"), to deal in the Software without restriction, including 15 without limitation the rights to use, copy, modify, merge, publish, 16 distribute, sublicense, and/or sell copies of the Software, and to 17 permit persons to whom the Software is furnished to do so, subject to 18 the following conditions: 19 20 The above copyright notice and this permission notice shall be included 21 in all copies or substantial portions of the Software. 22 23 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 26 IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY 27 CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 28 TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 29 SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ 30 31#ifndef XTENSA_CORE_TEST_MMUHIFI_C3_CORE_ISA_H 32#define XTENSA_CORE_TEST_MMUHIFI_C3_CORE_ISA_H 33 34 35/**************************************************************************** 36 Parameters Useful for Any Code, USER or PRIVILEGED 37 ****************************************************************************/ 38 39/* 40 * Note: Macros of the form XCHAL_HAVE_*** have a value of 1 if the option is 41 * configured, and a value of 0 otherwise. These macros are always defined. 42 */ 43 44 45/*---------------------------------------------------------------------- 46 ISA 47 ----------------------------------------------------------------------*/ 48 49#define XCHAL_HAVE_BE 0 /* big-endian byte ordering */ 50#define XCHAL_HAVE_WINDOWED 1 /* windowed registers option */ 51#define XCHAL_NUM_AREGS 32 /* num of physical addr regs */ 52#define XCHAL_NUM_AREGS_LOG2 5 /* log2(XCHAL_NUM_AREGS) */ 53#define XCHAL_MAX_INSTRUCTION_SIZE 8 /* max instr bytes (3..8) */ 54#define XCHAL_HAVE_DEBUG 1 /* debug option */ 55#define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */ 56#define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */ 57#define XCHAL_LOOP_BUFFER_SIZE 0 /* zero-ov. loop instr buffer size */ 58#define XCHAL_HAVE_NSA 1 /* NSA/NSAU instructions */ 59#define XCHAL_HAVE_MINMAX 1 /* MIN/MAX instructions */ 60#define XCHAL_HAVE_SEXT 1 /* SEXT instruction */ 61#define XCHAL_HAVE_CLAMPS 1 /* CLAMPS instruction */ 62#define XCHAL_HAVE_MUL16 1 /* MUL16S/MUL16U instructions */ 63#define XCHAL_HAVE_MUL32 1 /* MULL instruction */ 64#define XCHAL_HAVE_MUL32_HIGH 0 /* MULUH/MULSH instructions */ 65#define XCHAL_HAVE_DIV32 0 /* QUOS/QUOU/REMS/REMU instructions */ 66#define XCHAL_HAVE_L32R 1 /* L32R instruction */ 67#define XCHAL_HAVE_ABSOLUTE_LITERALS 1 /* non-PC-rel (extended) L32R */ 68#define XCHAL_HAVE_CONST16 0 /* CONST16 instruction */ 69#define XCHAL_HAVE_ADDX 1 /* ADDX#/SUBX# instructions */ 70#define XCHAL_HAVE_WIDE_BRANCHES 0 /* B*.W18 or B*.W15 instr's */ 71#define XCHAL_HAVE_PREDICTED_BRANCHES 0 /* B[EQ/EQZ/NE/NEZ]T instr's */ 72#define XCHAL_HAVE_CALL4AND12 1 /* (obsolete option) */ 73#define XCHAL_HAVE_ABS 1 /* ABS instruction */ 74/*#define XCHAL_HAVE_POPC 0*/ /* POPC instruction */ 75/*#define XCHAL_HAVE_CRC 0*/ /* CRC instruction */ 76#define XCHAL_HAVE_RELEASE_SYNC 1 /* L32AI/S32RI instructions */ 77#define XCHAL_HAVE_S32C1I 1 /* S32C1I instruction */ 78#define XCHAL_HAVE_SPECULATION 0 /* speculation */ 79#define XCHAL_HAVE_FULL_RESET 1 /* all regs/state reset */ 80#define XCHAL_NUM_CONTEXTS 1 /* */ 81#define XCHAL_NUM_MISC_REGS 2 /* num of scratch regs (0..4) */ 82#define XCHAL_HAVE_TAP_MASTER 0 /* JTAG TAP control instr's */ 83#define XCHAL_HAVE_PRID 1 /* processor ID register */ 84#define XCHAL_HAVE_EXTERN_REGS 1 /* WER/RER instructions */ 85#define XCHAL_HAVE_MX 1 /* MX core (Tensilica internal) */ 86#define XCHAL_HAVE_MP_INTERRUPTS 1 /* interrupt distributor port */ 87#define XCHAL_HAVE_MP_RUNSTALL 1 /* core RunStall control port */ 88#define XCHAL_HAVE_PSO 0 /* Power Shut-Off */ 89#define XCHAL_HAVE_PSO_CDM 0 /* core/debug/mem pwr domains */ 90#define XCHAL_HAVE_PSO_FULL_RETENTION 0 /* all regs preserved on PSO */ 91#define XCHAL_HAVE_THREADPTR 1 /* THREADPTR register */ 92#define XCHAL_HAVE_BOOLEANS 1 /* boolean registers */ 93#define XCHAL_HAVE_CP 1 /* CPENABLE reg (coprocessor) */ 94#define XCHAL_CP_MAXCFG 2 /* max allowed cp id plus one */ 95#define XCHAL_HAVE_MAC16 0 /* MAC16 package */ 96#define XCHAL_HAVE_VECTORFPU2005 0 /* vector floating-point pkg */ 97#define XCHAL_HAVE_FP 0 /* single prec floating point */ 98#define XCHAL_HAVE_FP_DIV 0 /* FP with DIV instructions */ 99#define XCHAL_HAVE_FP_RECIP 0 /* FP with RECIP instructions */ 100#define XCHAL_HAVE_FP_SQRT 0 /* FP with SQRT instructions */ 101#define XCHAL_HAVE_FP_RSQRT 0 /* FP with RSQRT instructions */ 102#define XCHAL_HAVE_DFP 0 /* double precision FP pkg */ 103#define XCHAL_HAVE_DFP_DIV 0 /* DFP with DIV instructions */ 104#define XCHAL_HAVE_DFP_RECIP 0 /* DFP with RECIP instructions*/ 105#define XCHAL_HAVE_DFP_SQRT 0 /* DFP with SQRT instructions */ 106#define XCHAL_HAVE_DFP_RSQRT 0 /* DFP with RSQRT instructions*/ 107#define XCHAL_HAVE_DFP_accel 0 /* double precision FP acceleration pkg */ 108#define XCHAL_HAVE_VECTRA1 0 /* Vectra I pkg */ 109#define XCHAL_HAVE_VECTRALX 0 /* Vectra LX pkg */ 110#define XCHAL_HAVE_HIFIPRO 0 /* HiFiPro Audio Engine pkg */ 111#define XCHAL_HAVE_HIFI3 0 /* HiFi3 Audio Engine pkg */ 112#define XCHAL_HAVE_HIFI2 1 /* HiFi2 Audio Engine pkg */ 113#define XCHAL_HAVE_HIFI2EP 0 /* HiFi2EP */ 114#define XCHAL_HAVE_HIFI_MINI 0 115#define XCHAL_HAVE_CONNXD2 0 /* ConnX D2 pkg */ 116#define XCHAL_HAVE_BBE16 0 /* ConnX BBE16 pkg */ 117#define XCHAL_HAVE_BBE16_RSQRT 0 /* BBE16 & vector recip sqrt */ 118#define XCHAL_HAVE_BBE16_VECDIV 0 /* BBE16 & vector divide */ 119#define XCHAL_HAVE_BBE16_DESPREAD 0 /* BBE16 & despread */ 120#define XCHAL_HAVE_BBENEP 0 /* ConnX BBENEP pkgs */ 121#define XCHAL_HAVE_BSP3 0 /* ConnX BSP3 pkg */ 122#define XCHAL_HAVE_BSP3_TRANSPOSE 0 /* BSP3 & transpose32x32 */ 123#define XCHAL_HAVE_SSP16 0 /* ConnX SSP16 pkg */ 124#define XCHAL_HAVE_SSP16_VITERBI 0 /* SSP16 & viterbi */ 125#define XCHAL_HAVE_TURBO16 0 /* ConnX Turbo16 pkg */ 126#define XCHAL_HAVE_BBP16 0 /* ConnX BBP16 pkg */ 127#define XCHAL_HAVE_FLIX3 0 /* basic 3-way FLIX option */ 128 129 130/*---------------------------------------------------------------------- 131 MISC 132 ----------------------------------------------------------------------*/ 133 134#define XCHAL_NUM_LOADSTORE_UNITS 1 /* load/store units */ 135#define XCHAL_NUM_WRITEBUFFER_ENTRIES 8 /* size of write buffer */ 136#define XCHAL_INST_FETCH_WIDTH 8 /* instr-fetch width in bytes */ 137#define XCHAL_DATA_WIDTH 8 /* data width in bytes */ 138#define XCHAL_DATA_PIPE_DELAY 1 /* d-side pipeline delay 139 (1 = 5-stage, 2 = 7-stage) */ 140/* In T1050, applies to selected core load and store instructions (see ISA): */ 141#define XCHAL_UNALIGNED_LOAD_EXCEPTION 1 /* unaligned loads cause exc. */ 142#define XCHAL_UNALIGNED_STORE_EXCEPTION 1 /* unaligned stores cause exc.*/ 143#define XCHAL_UNALIGNED_LOAD_HW 0 /* unaligned loads work in hw */ 144#define XCHAL_UNALIGNED_STORE_HW 0 /* unaligned stores work in hw*/ 145 146#define XCHAL_SW_VERSION 1000006 /* sw version of this header */ 147 148#define XCHAL_CORE_ID "test_mmuhifi_c3" /* alphanum core name 149 (CoreID) set in the Xtensa 150 Processor Generator */ 151 152#define XCHAL_BUILD_UNIQUE_ID 0x00005A6A /* 22-bit sw build ID */ 153 154/* 155 * These definitions describe the hardware targeted by this software. 156 */ 157#define XCHAL_HW_CONFIGID0 0xC1B3CBFE /* ConfigID hi 32 bits*/ 158#define XCHAL_HW_CONFIGID1 0x10405A6A /* ConfigID lo 32 bits*/ 159#define XCHAL_HW_VERSION_NAME "LX3.0.0" /* full version name */ 160#define XCHAL_HW_VERSION_MAJOR 2300 /* major ver# of targeted hw */ 161#define XCHAL_HW_VERSION_MINOR 0 /* minor ver# of targeted hw */ 162#define XCHAL_HW_VERSION 230000 /* major*100+minor */ 163#define XCHAL_HW_REL_LX3 1 164#define XCHAL_HW_REL_LX3_0 1 165#define XCHAL_HW_REL_LX3_0_0 1 166#define XCHAL_HW_CONFIGID_RELIABLE 1 167/* If software targets a *range* of hardware versions, these are the bounds: */ 168#define XCHAL_HW_MIN_VERSION_MAJOR 2300 /* major v of earliest tgt hw */ 169#define XCHAL_HW_MIN_VERSION_MINOR 0 /* minor v of earliest tgt hw */ 170#define XCHAL_HW_MIN_VERSION 230000 /* earliest targeted hw */ 171#define XCHAL_HW_MAX_VERSION_MAJOR 2300 /* major v of latest tgt hw */ 172#define XCHAL_HW_MAX_VERSION_MINOR 0 /* minor v of latest tgt hw */ 173#define XCHAL_HW_MAX_VERSION 230000 /* latest targeted hw */ 174 175 176/*---------------------------------------------------------------------- 177 CACHE 178 ----------------------------------------------------------------------*/ 179 180#define XCHAL_ICACHE_LINESIZE 32 /* I-cache line size in bytes */ 181#define XCHAL_DCACHE_LINESIZE 32 /* D-cache line size in bytes */ 182#define XCHAL_ICACHE_LINEWIDTH 5 /* log2(I line size in bytes) */ 183#define XCHAL_DCACHE_LINEWIDTH 5 /* log2(D line size in bytes) */ 184 185#define XCHAL_ICACHE_SIZE 16384 /* I-cache size in bytes or 0 */ 186#define XCHAL_DCACHE_SIZE 16384 /* D-cache size in bytes or 0 */ 187 188#define XCHAL_DCACHE_IS_WRITEBACK 1 /* writeback feature */ 189#define XCHAL_DCACHE_IS_COHERENT 1 /* MP coherence feature */ 190 191#define XCHAL_HAVE_PREFETCH 0 /* PREFCTL register */ 192#define XCHAL_HAVE_PREFETCH_L1 0 /* prefetch to L1 dcache */ 193#define XCHAL_PREFETCH_CASTOUT_LINES 0 /* dcache pref. castout bufsz */ 194 195 196 197 198/**************************************************************************** 199 Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code 200 ****************************************************************************/ 201 202 203#ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY 204 205/*---------------------------------------------------------------------- 206 CACHE 207 ----------------------------------------------------------------------*/ 208 209#define XCHAL_HAVE_PIF 1 /* any outbound PIF present */ 210 211/* If present, cache size in bytes == (ways * 2^(linewidth + setwidth)). */ 212 213/* Number of cache sets in log2(lines per way): */ 214#define XCHAL_ICACHE_SETWIDTH 8 215#define XCHAL_DCACHE_SETWIDTH 8 216 217/* Cache set associativity (number of ways): */ 218#define XCHAL_ICACHE_WAYS 2 219#define XCHAL_DCACHE_WAYS 2 220 221/* Cache features: */ 222#define XCHAL_ICACHE_LINE_LOCKABLE 0 223#define XCHAL_DCACHE_LINE_LOCKABLE 0 224#define XCHAL_ICACHE_ECC_PARITY 0 225#define XCHAL_DCACHE_ECC_PARITY 0 226 227/* Cache access size in bytes (affects operation of SICW instruction): */ 228#define XCHAL_ICACHE_ACCESS_SIZE 8 229#define XCHAL_DCACHE_ACCESS_SIZE 8 230 231#define XCHAL_DCACHE_BANKS 1 /* number of banks */ 232 233/* Number of encoded cache attr bits (see <xtensa/hal.h> for decoded bits): */ 234#define XCHAL_CA_BITS 4 235 236 237/*---------------------------------------------------------------------- 238 INTERNAL I/D RAM/ROMs and XLMI 239 ----------------------------------------------------------------------*/ 240 241#define XCHAL_NUM_INSTROM 0 /* number of core instr. ROMs */ 242#define XCHAL_NUM_INSTRAM 0 /* number of core instr. RAMs */ 243#define XCHAL_NUM_DATAROM 0 /* number of core data ROMs */ 244#define XCHAL_NUM_DATARAM 0 /* number of core data RAMs */ 245#define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/ 246#define XCHAL_NUM_XLMI 0 /* number of core XLMI ports */ 247 248#define XCHAL_HAVE_IMEM_LOADSTORE 1 /* can load/store to IROM/IRAM*/ 249 250 251/*---------------------------------------------------------------------- 252 INTERRUPTS and TIMERS 253 ----------------------------------------------------------------------*/ 254 255#define XCHAL_HAVE_INTERRUPTS 1 /* interrupt option */ 256#define XCHAL_HAVE_HIGHPRI_INTERRUPTS 1 /* med/high-pri. interrupts */ 257#define XCHAL_HAVE_NMI 0 /* non-maskable interrupt */ 258#define XCHAL_HAVE_CCOUNT 1 /* CCOUNT reg. (timer option) */ 259#define XCHAL_NUM_TIMERS 2 /* number of CCOMPAREn regs */ 260#define XCHAL_NUM_INTERRUPTS 12 /* number of interrupts */ 261#define XCHAL_NUM_INTERRUPTS_LOG2 4 /* ceil(log2(NUM_INTERRUPTS)) */ 262#define XCHAL_NUM_EXTINTERRUPTS 9 /* num of external interrupts */ 263#define XCHAL_NUM_INTLEVELS 2 /* number of interrupt levels 264 (not including level zero) */ 265#define XCHAL_EXCM_LEVEL 1 /* level masked by PS.EXCM */ 266 /* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */ 267 268/* Masks of interrupts at each interrupt level: */ 269#define XCHAL_INTLEVEL1_MASK 0x00000FFF 270#define XCHAL_INTLEVEL2_MASK 0x00000000 271#define XCHAL_INTLEVEL3_MASK 0x00000000 272#define XCHAL_INTLEVEL4_MASK 0x00000000 273#define XCHAL_INTLEVEL5_MASK 0x00000000 274#define XCHAL_INTLEVEL6_MASK 0x00000000 275#define XCHAL_INTLEVEL7_MASK 0x00000000 276 277/* Masks of interrupts at each range 1..n of interrupt levels: */ 278#define XCHAL_INTLEVEL1_ANDBELOW_MASK 0x00000FFF 279#define XCHAL_INTLEVEL2_ANDBELOW_MASK 0x00000FFF 280#define XCHAL_INTLEVEL3_ANDBELOW_MASK 0x00000FFF 281#define XCHAL_INTLEVEL4_ANDBELOW_MASK 0x00000FFF 282#define XCHAL_INTLEVEL5_ANDBELOW_MASK 0x00000FFF 283#define XCHAL_INTLEVEL6_ANDBELOW_MASK 0x00000FFF 284#define XCHAL_INTLEVEL7_ANDBELOW_MASK 0x00000FFF 285 286/* Level of each interrupt: */ 287#define XCHAL_INT0_LEVEL 1 288#define XCHAL_INT1_LEVEL 1 289#define XCHAL_INT2_LEVEL 1 290#define XCHAL_INT3_LEVEL 1 291#define XCHAL_INT4_LEVEL 1 292#define XCHAL_INT5_LEVEL 1 293#define XCHAL_INT6_LEVEL 1 294#define XCHAL_INT7_LEVEL 1 295#define XCHAL_INT8_LEVEL 1 296#define XCHAL_INT9_LEVEL 1 297#define XCHAL_INT10_LEVEL 1 298#define XCHAL_INT11_LEVEL 1 299#define XCHAL_DEBUGLEVEL 2 /* debug interrupt level */ 300#define XCHAL_HAVE_DEBUG_EXTERN_INT 1 /* OCD external db interrupt */ 301 302/* Type of each interrupt: */ 303#define XCHAL_INT0_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 304#define XCHAL_INT1_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 305#define XCHAL_INT2_TYPE XTHAL_INTTYPE_EXTERN_EDGE 306#define XCHAL_INT3_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 307#define XCHAL_INT4_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 308#define XCHAL_INT5_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 309#define XCHAL_INT6_TYPE XTHAL_INTTYPE_TIMER 310#define XCHAL_INT7_TYPE XTHAL_INTTYPE_SOFTWARE 311#define XCHAL_INT8_TYPE XTHAL_INTTYPE_TIMER 312#define XCHAL_INT9_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 313#define XCHAL_INT10_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 314#define XCHAL_INT11_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 315 316/* Masks of interrupts for each type of interrupt: */ 317#define XCHAL_INTTYPE_MASK_UNCONFIGURED 0xFFFFF000 318#define XCHAL_INTTYPE_MASK_SOFTWARE 0x00000080 319#define XCHAL_INTTYPE_MASK_EXTERN_EDGE 0x00000004 320#define XCHAL_INTTYPE_MASK_EXTERN_LEVEL 0x00000E3B 321#define XCHAL_INTTYPE_MASK_TIMER 0x00000140 322#define XCHAL_INTTYPE_MASK_NMI 0x00000000 323#define XCHAL_INTTYPE_MASK_WRITE_ERROR 0x00000000 324#define XCHAL_INTTYPE_MASK_PROFILING 0x00000000 325 326/* Interrupt numbers assigned to specific interrupt sources: */ 327#define XCHAL_TIMER0_INTERRUPT 6 /* CCOMPARE0 */ 328#define XCHAL_TIMER1_INTERRUPT 8 /* CCOMPARE1 */ 329#define XCHAL_TIMER2_INTERRUPT XTHAL_TIMER_UNCONFIGURED 330#define XCHAL_TIMER3_INTERRUPT XTHAL_TIMER_UNCONFIGURED 331 332/* Interrupt numbers for levels at which only one interrupt is configured: */ 333/* (There are many interrupts each at level(s) 1.) */ 334 335 336/* 337 * External interrupt mapping. 338 * These macros describe how Xtensa processor interrupt numbers 339 * (as numbered internally, eg. in INTERRUPT and INTENABLE registers) 340 * map to external BInterrupt<n> pins, for those interrupts 341 * configured as external (level-triggered, edge-triggered, or NMI). 342 * See the Xtensa processor databook for more details. 343 */ 344 345/* Core interrupt numbers mapped to each EXTERNAL BInterrupt pin number: */ 346#define XCHAL_EXTINT0_NUM 0 /* (intlevel 1) */ 347#define XCHAL_EXTINT1_NUM 1 /* (intlevel 1) */ 348#define XCHAL_EXTINT2_NUM 2 /* (intlevel 1) */ 349#define XCHAL_EXTINT3_NUM 3 /* (intlevel 1) */ 350#define XCHAL_EXTINT4_NUM 4 /* (intlevel 1) */ 351#define XCHAL_EXTINT5_NUM 5 /* (intlevel 1) */ 352#define XCHAL_EXTINT6_NUM 9 /* (intlevel 1) */ 353#define XCHAL_EXTINT7_NUM 10 /* (intlevel 1) */ 354#define XCHAL_EXTINT8_NUM 11 /* (intlevel 1) */ 355/* EXTERNAL BInterrupt pin numbers mapped to each core interrupt number: */ 356#define XCHAL_INT0_EXTNUM 0 /* (intlevel 1) */ 357#define XCHAL_INT1_EXTNUM 1 /* (intlevel 1) */ 358#define XCHAL_INT2_EXTNUM 2 /* (intlevel 1) */ 359#define XCHAL_INT3_EXTNUM 3 /* (intlevel 1) */ 360#define XCHAL_INT4_EXTNUM 4 /* (intlevel 1) */ 361#define XCHAL_INT5_EXTNUM 5 /* (intlevel 1) */ 362#define XCHAL_INT9_EXTNUM 6 /* (intlevel 1) */ 363#define XCHAL_INT10_EXTNUM 7 /* (intlevel 1) */ 364#define XCHAL_INT11_EXTNUM 8 /* (intlevel 1) */ 365 366 367/*---------------------------------------------------------------------- 368 EXCEPTIONS and VECTORS 369 ----------------------------------------------------------------------*/ 370 371#define XCHAL_XEA_VERSION 2 /* Xtensa Exception Architecture 372 number: 1 == XEA1 (old) 373 2 == XEA2 (new) 374 0 == XEAX (extern) or TX */ 375#define XCHAL_HAVE_XEA1 0 /* Exception Architecture 1 */ 376#define XCHAL_HAVE_XEA2 1 /* Exception Architecture 2 */ 377#define XCHAL_HAVE_XEAX 0 /* External Exception Arch. */ 378#define XCHAL_HAVE_EXCEPTIONS 1 /* exception option */ 379#define XCHAL_HAVE_HALT 0 /* halt architecture option */ 380#define XCHAL_HAVE_BOOTLOADER 0 /* boot loader (for TX) */ 381#define XCHAL_HAVE_MEM_ECC_PARITY 0 /* local memory ECC/parity */ 382#define XCHAL_HAVE_VECTOR_SELECT 1 /* relocatable vectors */ 383#define XCHAL_HAVE_VECBASE 1 /* relocatable vectors */ 384#define XCHAL_VECBASE_RESET_VADDR 0xD0000000 /* VECBASE reset value */ 385#define XCHAL_VECBASE_RESET_PADDR 0x00000000 386#define XCHAL_RESET_VECBASE_OVERLAP 0 387 388#define XCHAL_RESET_VECTOR0_VADDR 0xFE000000 389#define XCHAL_RESET_VECTOR0_PADDR 0xFE000000 390#define XCHAL_RESET_VECTOR1_VADDR 0xD8000500 391#define XCHAL_RESET_VECTOR1_PADDR 0x00000500 392#define XCHAL_RESET_VECTOR_VADDR 0xFE000000 393#define XCHAL_RESET_VECTOR_PADDR 0xFE000000 394#define XCHAL_USER_VECOFS 0x00000340 395#define XCHAL_USER_VECTOR_VADDR 0xD0000340 396#define XCHAL_USER_VECTOR_PADDR 0x00000340 397#define XCHAL_KERNEL_VECOFS 0x00000300 398#define XCHAL_KERNEL_VECTOR_VADDR 0xD0000300 399#define XCHAL_KERNEL_VECTOR_PADDR 0x00000300 400#define XCHAL_DOUBLEEXC_VECOFS 0x000003C0 401#define XCHAL_DOUBLEEXC_VECTOR_VADDR 0xD00003C0 402#define XCHAL_DOUBLEEXC_VECTOR_PADDR 0x000003C0 403#define XCHAL_WINDOW_OF4_VECOFS 0x00000000 404#define XCHAL_WINDOW_UF4_VECOFS 0x00000040 405#define XCHAL_WINDOW_OF8_VECOFS 0x00000080 406#define XCHAL_WINDOW_UF8_VECOFS 0x000000C0 407#define XCHAL_WINDOW_OF12_VECOFS 0x00000100 408#define XCHAL_WINDOW_UF12_VECOFS 0x00000140 409#define XCHAL_WINDOW_VECTORS_VADDR 0xD0000000 410#define XCHAL_WINDOW_VECTORS_PADDR 0x00000000 411#define XCHAL_INTLEVEL2_VECOFS 0x00000280 412#define XCHAL_INTLEVEL2_VECTOR_VADDR 0xD0000280 413#define XCHAL_INTLEVEL2_VECTOR_PADDR 0x00000280 414#define XCHAL_DEBUG_VECOFS XCHAL_INTLEVEL2_VECOFS 415#define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL2_VECTOR_VADDR 416#define XCHAL_DEBUG_VECTOR_PADDR XCHAL_INTLEVEL2_VECTOR_PADDR 417 418 419/*---------------------------------------------------------------------- 420 DEBUG MODULE 421 ----------------------------------------------------------------------*/ 422 423/* Misc */ 424#define XCHAL_HAVE_DEBUG_ERI 0 /* ERI to debug module */ 425#define XCHAL_HAVE_DEBUG_APB 0 /* APB to debug module */ 426#define XCHAL_HAVE_DEBUG_JTAG 0 /* JTAG to debug module */ 427 428/* On-Chip Debug (OCD) */ 429#define XCHAL_HAVE_OCD 1 /* OnChipDebug option */ 430#define XCHAL_NUM_IBREAK 0 /* number of IBREAKn regs */ 431#define XCHAL_NUM_DBREAK 0 /* number of DBREAKn regs */ 432#define XCHAL_HAVE_OCD_DIR_ARRAY 0 /* faster OCD option (to LX4) */ 433#define XCHAL_HAVE_OCD_LS32DDR 0 /* L32DDR/S32DDR (faster OCD) */ 434 435/* TRAX (in core) */ 436#define XCHAL_HAVE_TRAX 0 /* TRAX in debug module */ 437#define XCHAL_TRAX_MEM_SIZE 0 /* TRAX memory size in bytes */ 438#define XCHAL_TRAX_MEM_SHAREABLE 0 /* start/end regs; ready sig. */ 439#define XCHAL_TRAX_ATB_WIDTH 0 /* ATB width (bits), 0=no ATB */ 440#define XCHAL_TRAX_TIME_WIDTH 0 /* timestamp bitwidth, 0=none */ 441 442/* Perf counters */ 443#define XCHAL_NUM_PERF_COUNTERS 0 /* performance counters */ 444 445 446/*---------------------------------------------------------------------- 447 MMU 448 ----------------------------------------------------------------------*/ 449 450/* See core-matmap.h header file for more details. */ 451 452#define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */ 453#define XCHAL_HAVE_SPANNING_WAY 0 /* one way maps I+D 4GB vaddr */ 454#define XCHAL_HAVE_IDENTITY_MAP 0 /* vaddr == paddr always */ 455#define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */ 456#define XCHAL_HAVE_MIMIC_CACHEATTR 0 /* region protection */ 457#define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */ 458#define XCHAL_HAVE_PTP_MMU 1 /* full MMU (with page table 459 [autorefill] and protection) 460 usable for an MMU-based OS */ 461/* If none of the above last 4 are set, it's a custom TLB configuration. */ 462#define XCHAL_ITLB_ARF_ENTRIES_LOG2 2 /* log2(autorefill way size) */ 463#define XCHAL_DTLB_ARF_ENTRIES_LOG2 2 /* log2(autorefill way size) */ 464 465#define XCHAL_MMU_ASID_BITS 8 /* number of bits in ASIDs */ 466#define XCHAL_MMU_RINGS 4 /* number of rings (1..4) */ 467#define XCHAL_MMU_RING_BITS 2 /* num of bits in RING field */ 468 469#endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */ 470 471 472#endif /* XTENSA_CORE_TEST_MMUHIFI_C3_CORE_ISA_H */ 473