LXR qemu/target/xtensa/dbg

   1/*
   2 * Copyright (c) 2011 - 2019, Max Filippov, Open Source and Linux Lab.
   3 * All rights reserved.
   4 *
   5 * Redistribution and use in source and binary forms, with or without
   6 * modification, are permitted provided that the following conditions are met:
   7 *     * Redistributions of source code must retain the above copyright
   8 *       notice, this list of conditions and the following disclaimer.
   9 *     * Redistributions in binary form must reproduce the above copyright
  10 *       notice, this list of conditions and the following disclaimer in the
  11 *       documentation and/or other materials provided with the distribution.
  12 *     * Neither the name of the Open Source and Linux Lab nor the
  13 *       names of its contributors may be used to endorse or promote products
  14 *       derived from this software without specific prior written permission.
  15 *
  16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  20 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  23 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  25 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  26 */
  27
  28#include "qemu/osdep.h"
  29#include "qemu/log.h"
  30#include "qemu/main-loop.h"
  31#include "cpu.h"
  32#include "exec/helper-proto.h"
  33#include "qemu/host-utils.h"
  34#include "exec/exec-all.h"
  35#include "exec/address-spaces.h"
  36
  37static void tb_invalidate_virtual_addr(CPUXtensaState *env, uint32_t vaddr)
  38{
  39    uint32_t paddr;
  40    uint32_t page_size;
  41    unsigned access;
  42    int ret = xtensa_get_physical_addr(env, false, vaddr, 2, 0,
  43                                       &paddr, &page_size, &access);
  44    if (ret == 0) {
  45        tb_invalidate_phys_addr(&address_space_memory, paddr,
  46                                MEMTXATTRS_UNSPECIFIED);
  47    }
  48}
  49
  50void HELPER(wsr_ibreakenable)(CPUXtensaState *env, uint32_t v)
  51{
  52    uint32_t change = v ^ env->sregs[IBREAKENABLE];
  53    unsigned i;
  54
  55    for (i = 0; i < env->config->nibreak; ++i) {
  56        if (change & (1 << i)) {
  57            tb_invalidate_virtual_addr(env, env->sregs[IBREAKA + i]);
  58        }
  59    }
  60    env->sregs[IBREAKENABLE] = v & ((1 << env->config->nibreak) - 1);
  61}
  62
  63void HELPER(wsr_ibreaka)(CPUXtensaState *env, uint32_t i, uint32_t v)
  64{
  65    if (env->sregs[IBREAKENABLE] & (1 << i) && env->sregs[IBREAKA + i] != v) {
  66        tb_invalidate_virtual_addr(env, env->sregs[IBREAKA + i]);
  67        tb_invalidate_virtual_addr(env, v);
  68    }
  69    env->sregs[IBREAKA + i] = v;
  70}
  71
  72static void set_dbreak(CPUXtensaState *env, unsigned i, uint32_t dbreaka,
  73        uint32_t dbreakc)
  74{
  75    CPUState *cs = env_cpu(env);
  76    int flags = BP_CPU | BP_STOP_BEFORE_ACCESS;
  77    uint32_t mask = dbreakc | ~DBREAKC_MASK;
  78
  79    if (env->cpu_watchpoint[i]) {
  80        cpu_watchpoint_remove_by_ref(cs, env->cpu_watchpoint[i]);
  81    }
  82    if (dbreakc & DBREAKC_SB) {
  83        flags |= BP_MEM_WRITE;
  84    }
  85    if (dbreakc & DBREAKC_LB) {
  86        flags |= BP_MEM_READ;
  87    }
  88    /* contiguous mask after inversion is one less than some power of 2 */
  89    if ((~mask + 1) & ~mask) {
  90        qemu_log_mask(LOG_GUEST_ERROR,
  91                      "DBREAKC mask is not contiguous: 0x%08x\n", dbreakc);
  92        /* cut mask after the first zero bit */
  93        mask = 0xffffffff << (32 - clo32(mask));
  94    }
  95    if (cpu_watchpoint_insert(cs, dbreaka & mask, ~mask + 1,
  96                              flags, &env->cpu_watchpoint[i])) {
  97        env->cpu_watchpoint[i] = NULL;
  98        qemu_log_mask(LOG_GUEST_ERROR,
  99                      "Failed to set data breakpoint at 0x%08x/%d\n",
 100                      dbreaka & mask, ~mask + 1);
 101    }
 102}
 103
 104void HELPER(wsr_dbreaka)(CPUXtensaState *env, uint32_t i, uint32_t v)
 105{
 106    uint32_t dbreakc = env->sregs[DBREAKC + i];
 107
 108    if ((dbreakc & DBREAKC_SB_LB) &&
 109        env->sregs[DBREAKA + i] != v) {
 110        set_dbreak(env, i, v, dbreakc);
 111    }
 112    env->sregs[DBREAKA + i] = v;
 113}
 114
 115void HELPER(wsr_dbreakc)(CPUXtensaState *env, uint32_t i, uint32_t v)
 116{
 117    if ((env->sregs[DBREAKC + i] ^ v) & (DBREAKC_SB_LB | DBREAKC_MASK)) {
 118        if (v & DBREAKC_SB_LB) {
 119            set_dbreak(env, i, env->sregs[DBREAKA + i], v);
 120        } else {
 121            if (env->cpu_watchpoint[i]) {
 122                CPUState *cs = env_cpu(env);
 123
 124                cpu_watchpoint_remove_by_ref(cs, env->cpu_watchpoint[i]);
 125                env->cpu_watchpoint[i] = NULL;
 126            }
 127        }
 128    }
 129    env->sregs[DBREAKC + i] = v;
 130}
 131