1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18#include "qemu/osdep.h"
19#include "qemu/units.h"
20#include "qapi/error.h"
21#include "cpu.h"
22#include "hw/sysbus.h"
23#include "hw/arm/boot.h"
24#include "net/net.h"
25#include "sysemu/sysemu.h"
26#include "hw/boards.h"
27#include "hw/block/flash.h"
28#include "hw/loader.h"
29#include "hw/adc/zynq-xadc.h"
30#include "hw/ssi/ssi.h"
31#include "hw/usb/chipidea.h"
32#include "qemu/error-report.h"
33#include "hw/sd/sdhci.h"
34#include "hw/char/cadence_uart.h"
35#include "hw/net/cadence_gem.h"
36#include "hw/cpu/a9mpcore.h"
37#include "hw/qdev-clock.h"
38#include "sysemu/reset.h"
39#include "qom/object.h"
40
41#define TYPE_ZYNQ_MACHINE MACHINE_TYPE_NAME("xilinx-zynq-a9")
42OBJECT_DECLARE_SIMPLE_TYPE(ZynqMachineState, ZYNQ_MACHINE)
43
44
45#define PS_CLK_FREQUENCY (100 * 1000 * 1000 / 3)
46
47#define NUM_SPI_FLASHES 4
48#define NUM_QSPI_FLASHES 2
49#define NUM_QSPI_BUSSES 2
50
51#define FLASH_SIZE (64 * 1024 * 1024)
52#define FLASH_SECTOR_SIZE (128 * 1024)
53
54#define IRQ_OFFSET 32
55
56#define MPCORE_PERIPHBASE 0xF8F00000
57#define ZYNQ_BOARD_MIDR 0x413FC090
58
59static const int dma_irqs[8] = {
60 46, 47, 48, 49, 72, 73, 74, 75
61};
62
63#define BOARD_SETUP_ADDR 0x100
64
65#define SLCR_LOCK_OFFSET 0x004
66#define SLCR_UNLOCK_OFFSET 0x008
67#define SLCR_ARM_PLL_OFFSET 0x100
68
69#define SLCR_XILINX_UNLOCK_KEY 0xdf0d
70#define SLCR_XILINX_LOCK_KEY 0x767b
71
72#define ZYNQ_SDHCI_CAPABILITIES 0x69ec0080
73
74#define ARMV7_IMM16(x) (extract32((x), 0, 12) | \
75 extract32((x), 12, 4) << 16)
76
77
78
79
80
81#define SLCR_WRITE(addr, val) \
82 0xe3001000 + ARMV7_IMM16(extract32((val), 0, 16)), \
83 0xe3401000 + ARMV7_IMM16(extract32((val), 16, 16)), \
84 0xe5801000 + (addr)
85
86struct ZynqMachineState {
87 MachineState parent;
88 Clock *ps_clk;
89};
90
91static void zynq_write_board_setup(ARMCPU *cpu,
92 const struct arm_boot_info *info)
93{
94 int n;
95 uint32_t board_setup_blob[] = {
96 0xe3a004f8,
97 SLCR_WRITE(SLCR_UNLOCK_OFFSET, SLCR_XILINX_UNLOCK_KEY),
98 SLCR_WRITE(SLCR_ARM_PLL_OFFSET, 0x00014008),
99 SLCR_WRITE(SLCR_LOCK_OFFSET, SLCR_XILINX_LOCK_KEY),
100 0xe12fff1e,
101 };
102 for (n = 0; n < ARRAY_SIZE(board_setup_blob); n++) {
103 board_setup_blob[n] = tswap32(board_setup_blob[n]);
104 }
105 rom_add_blob_fixed("board-setup", board_setup_blob,
106 sizeof(board_setup_blob), BOARD_SETUP_ADDR);
107}
108
109static struct arm_boot_info zynq_binfo = {};
110
111static void gem_init(NICInfo *nd, uint32_t base, qemu_irq irq)
112{
113 DeviceState *dev;
114 SysBusDevice *s;
115
116 dev = qdev_new(TYPE_CADENCE_GEM);
117 if (nd->used) {
118 qemu_check_nic_model(nd, TYPE_CADENCE_GEM);
119 qdev_set_nic_properties(dev, nd);
120 }
121 object_property_set_int(OBJECT(dev), "phy-addr", 7, &error_abort);
122 s = SYS_BUS_DEVICE(dev);
123 sysbus_realize_and_unref(s, &error_fatal);
124 sysbus_mmio_map(s, 0, base);
125 sysbus_connect_irq(s, 0, irq);
126}
127
128static inline int zynq_init_spi_flashes(uint32_t base_addr, qemu_irq irq,
129 bool is_qspi, int unit0)
130{
131 int unit = unit0;
132 DeviceState *dev;
133 SysBusDevice *busdev;
134 SSIBus *spi;
135 DeviceState *flash_dev;
136 int i, j;
137 int num_busses = is_qspi ? NUM_QSPI_BUSSES : 1;
138 int num_ss = is_qspi ? NUM_QSPI_FLASHES : NUM_SPI_FLASHES;
139
140 dev = qdev_new(is_qspi ? "xlnx.ps7-qspi" : "xlnx.ps7-spi");
141 qdev_prop_set_uint8(dev, "num-txrx-bytes", is_qspi ? 4 : 1);
142 qdev_prop_set_uint8(dev, "num-ss-bits", num_ss);
143 qdev_prop_set_uint8(dev, "num-busses", num_busses);
144 busdev = SYS_BUS_DEVICE(dev);
145 sysbus_realize_and_unref(busdev, &error_fatal);
146 sysbus_mmio_map(busdev, 0, base_addr);
147 if (is_qspi) {
148 sysbus_mmio_map(busdev, 1, 0xFC000000);
149 }
150 sysbus_connect_irq(busdev, 0, irq);
151
152 for (i = 0; i < num_busses; ++i) {
153 char bus_name[16];
154 qemu_irq cs_line;
155
156 snprintf(bus_name, 16, "spi%d", i);
157 spi = (SSIBus *)qdev_get_child_bus(dev, bus_name);
158
159 for (j = 0; j < num_ss; ++j) {
160 DriveInfo *dinfo = drive_get(IF_MTD, 0, unit++);
161 flash_dev = qdev_new("n25q128");
162 if (dinfo) {
163 qdev_prop_set_drive_err(flash_dev, "drive",
164 blk_by_legacy_dinfo(dinfo),
165 &error_fatal);
166 }
167 qdev_realize_and_unref(flash_dev, BUS(spi), &error_fatal);
168
169 cs_line = qdev_get_gpio_in_named(flash_dev, SSI_GPIO_CS, 0);
170 sysbus_connect_irq(busdev, i * num_ss + j + 1, cs_line);
171 }
172 }
173
174 return unit;
175}
176
177static void zynq_init(MachineState *machine)
178{
179 ZynqMachineState *zynq_machine = ZYNQ_MACHINE(machine);
180 ARMCPU *cpu;
181 MemoryRegion *address_space_mem = get_system_memory();
182 MemoryRegion *ocm_ram = g_new(MemoryRegion, 1);
183 DeviceState *dev, *slcr;
184 SysBusDevice *busdev;
185 qemu_irq pic[64];
186 int n;
187
188
189 if (machine->ram_size > 2 * GiB) {
190 error_report("RAM size more than 2 GiB is not supported");
191 exit(EXIT_FAILURE);
192 }
193
194 cpu = ARM_CPU(object_new(machine->cpu_type));
195
196
197
198
199
200 if (object_property_find(OBJECT(cpu), "has_el3")) {
201 object_property_set_bool(OBJECT(cpu), "has_el3", false, &error_fatal);
202 }
203
204 object_property_set_int(OBJECT(cpu), "midr", ZYNQ_BOARD_MIDR,
205 &error_fatal);
206 object_property_set_int(OBJECT(cpu), "reset-cbar", MPCORE_PERIPHBASE,
207 &error_fatal);
208 qdev_realize(DEVICE(cpu), NULL, &error_fatal);
209
210
211 memory_region_add_subregion(address_space_mem, 0, machine->ram);
212
213
214 memory_region_init_ram(ocm_ram, NULL, "zynq.ocm_ram", 256 * KiB,
215 &error_fatal);
216 memory_region_add_subregion(address_space_mem, 0xFFFC0000, ocm_ram);
217
218 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0);
219
220
221 pflash_cfi02_register(0xe2000000, "zynq.pflash", FLASH_SIZE,
222 dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
223 FLASH_SECTOR_SIZE, 1,
224 1, 0x0066, 0x0022, 0x0000, 0x0000, 0x0555, 0x2aa,
225 0);
226
227
228 zynq_machine->ps_clk = CLOCK(object_new(TYPE_CLOCK));
229 object_property_add_child(OBJECT(zynq_machine), "ps_clk",
230 OBJECT(zynq_machine->ps_clk));
231 object_unref(OBJECT(zynq_machine->ps_clk));
232 clock_set_hz(zynq_machine->ps_clk, PS_CLK_FREQUENCY);
233
234
235 slcr = qdev_new("xilinx-zynq_slcr");
236 qdev_connect_clock_in(slcr, "ps_clk", zynq_machine->ps_clk);
237 sysbus_realize_and_unref(SYS_BUS_DEVICE(slcr), &error_fatal);
238 sysbus_mmio_map(SYS_BUS_DEVICE(slcr), 0, 0xF8000000);
239
240 dev = qdev_new(TYPE_A9MPCORE_PRIV);
241 qdev_prop_set_uint32(dev, "num-cpu", 1);
242 busdev = SYS_BUS_DEVICE(dev);
243 sysbus_realize_and_unref(busdev, &error_fatal);
244 sysbus_mmio_map(busdev, 0, MPCORE_PERIPHBASE);
245 sysbus_connect_irq(busdev, 0,
246 qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ));
247
248 for (n = 0; n < 64; n++) {
249 pic[n] = qdev_get_gpio_in(dev, n);
250 }
251
252 n = zynq_init_spi_flashes(0xE0006000, pic[58 - IRQ_OFFSET], false, 0);
253 n = zynq_init_spi_flashes(0xE0007000, pic[81 - IRQ_OFFSET], false, n);
254 n = zynq_init_spi_flashes(0xE000D000, pic[51 - IRQ_OFFSET], true, n);
255
256 sysbus_create_simple(TYPE_CHIPIDEA, 0xE0002000, pic[53 - IRQ_OFFSET]);
257 sysbus_create_simple(TYPE_CHIPIDEA, 0xE0003000, pic[76 - IRQ_OFFSET]);
258
259 dev = qdev_new(TYPE_CADENCE_UART);
260 busdev = SYS_BUS_DEVICE(dev);
261 qdev_prop_set_chr(dev, "chardev", serial_hd(0));
262 qdev_connect_clock_in(dev, "refclk",
263 qdev_get_clock_out(slcr, "uart0_ref_clk"));
264 sysbus_realize_and_unref(busdev, &error_fatal);
265 sysbus_mmio_map(busdev, 0, 0xE0000000);
266 sysbus_connect_irq(busdev, 0, pic[59 - IRQ_OFFSET]);
267 dev = qdev_new(TYPE_CADENCE_UART);
268 busdev = SYS_BUS_DEVICE(dev);
269 qdev_prop_set_chr(dev, "chardev", serial_hd(1));
270 qdev_connect_clock_in(dev, "refclk",
271 qdev_get_clock_out(slcr, "uart1_ref_clk"));
272 sysbus_realize_and_unref(busdev, &error_fatal);
273 sysbus_mmio_map(busdev, 0, 0xE0001000);
274 sysbus_connect_irq(busdev, 0, pic[82 - IRQ_OFFSET]);
275
276 sysbus_create_varargs("cadence_ttc", 0xF8001000,
277 pic[42-IRQ_OFFSET], pic[43-IRQ_OFFSET], pic[44-IRQ_OFFSET], NULL);
278 sysbus_create_varargs("cadence_ttc", 0xF8002000,
279 pic[69-IRQ_OFFSET], pic[70-IRQ_OFFSET], pic[71-IRQ_OFFSET], NULL);
280
281 gem_init(&nd_table[0], 0xE000B000, pic[54-IRQ_OFFSET]);
282 gem_init(&nd_table[1], 0xE000C000, pic[77-IRQ_OFFSET]);
283
284 for (n = 0; n < 2; n++) {
285 int hci_irq = n ? 79 : 56;
286 hwaddr hci_addr = n ? 0xE0101000 : 0xE0100000;
287 DriveInfo *di;
288 BlockBackend *blk;
289 DeviceState *carddev;
290
291
292
293
294
295
296 dev = qdev_new(TYPE_SYSBUS_SDHCI);
297 qdev_prop_set_uint8(dev, "sd-spec-version", 2);
298 qdev_prop_set_uint64(dev, "capareg", ZYNQ_SDHCI_CAPABILITIES);
299 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
300 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, hci_addr);
301 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[hci_irq - IRQ_OFFSET]);
302
303 di = drive_get(IF_SD, 0, n);
304 blk = di ? blk_by_legacy_dinfo(di) : NULL;
305 carddev = qdev_new(TYPE_SD_CARD);
306 qdev_prop_set_drive_err(carddev, "drive", blk, &error_fatal);
307 qdev_realize_and_unref(carddev, qdev_get_child_bus(dev, "sd-bus"),
308 &error_fatal);
309 }
310
311 dev = qdev_new(TYPE_ZYNQ_XADC);
312 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
313 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xF8007100);
314 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[39-IRQ_OFFSET]);
315
316 dev = qdev_new("pl330");
317 object_property_set_link(OBJECT(dev), "memory",
318 OBJECT(address_space_mem),
319 &error_fatal);
320 qdev_prop_set_uint8(dev, "num_chnls", 8);
321 qdev_prop_set_uint8(dev, "num_periph_req", 4);
322 qdev_prop_set_uint8(dev, "num_events", 16);
323
324 qdev_prop_set_uint8(dev, "data_width", 64);
325 qdev_prop_set_uint8(dev, "wr_cap", 8);
326 qdev_prop_set_uint8(dev, "wr_q_dep", 16);
327 qdev_prop_set_uint8(dev, "rd_cap", 8);
328 qdev_prop_set_uint8(dev, "rd_q_dep", 16);
329 qdev_prop_set_uint16(dev, "data_buffer_dep", 256);
330
331 busdev = SYS_BUS_DEVICE(dev);
332 sysbus_realize_and_unref(busdev, &error_fatal);
333 sysbus_mmio_map(busdev, 0, 0xF8003000);
334 sysbus_connect_irq(busdev, 0, pic[45-IRQ_OFFSET]);
335 for (n = 0; n < ARRAY_SIZE(dma_irqs); ++n) {
336 sysbus_connect_irq(busdev, n + 1, pic[dma_irqs[n] - IRQ_OFFSET]);
337 }
338
339 dev = qdev_new("xlnx.ps7-dev-cfg");
340 busdev = SYS_BUS_DEVICE(dev);
341 sysbus_realize_and_unref(busdev, &error_fatal);
342 sysbus_connect_irq(busdev, 0, pic[40 - IRQ_OFFSET]);
343 sysbus_mmio_map(busdev, 0, 0xF8007000);
344
345 zynq_binfo.ram_size = machine->ram_size;
346 zynq_binfo.board_id = 0xd32;
347 zynq_binfo.loader_start = 0;
348 zynq_binfo.board_setup_addr = BOARD_SETUP_ADDR;
349 zynq_binfo.write_board_setup = zynq_write_board_setup;
350
351 arm_load_kernel(ARM_CPU(first_cpu), machine, &zynq_binfo);
352}
353
354static void zynq_machine_class_init(ObjectClass *oc, void *data)
355{
356 MachineClass *mc = MACHINE_CLASS(oc);
357 mc->desc = "Xilinx Zynq Platform Baseboard for Cortex-A9";
358 mc->init = zynq_init;
359 mc->max_cpus = 1;
360 mc->no_sdcard = 1;
361 mc->ignore_memory_transaction_failures = true;
362 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a9");
363 mc->default_ram_id = "zynq.ext_ram";
364}
365
366static const TypeInfo zynq_machine_type = {
367 .name = TYPE_ZYNQ_MACHINE,
368 .parent = TYPE_MACHINE,
369 .class_init = zynq_machine_class_init,
370 .instance_size = sizeof(ZynqMachineState),
371};
372
373static void zynq_machine_register_types(void)
374{
375 type_register_static(&zynq_machine_type);
376}
377
378type_init(zynq_machine_register_types)
379
