LXR qemu/hw/intc/loongarch_pch

   1/* SPDX-License-Identifier: GPL-2.0-or-later */
   2/*
   3 * QEMU Loongson 7A1000 msi interrupt controller.
   4 *
   5 * Copyright (C) 2021 Loongson Technology Corporation Limited
   6 */
   7
   8#include "qemu/osdep.h"
   9#include "hw/sysbus.h"
  10#include "hw/irq.h"
  11#include "hw/intc/loongarch_pch_msi.h"
  12#include "hw/intc/loongarch_pch_pic.h"
  13#include "hw/pci/msi.h"
  14#include "hw/misc/unimp.h"
  15#include "migration/vmstate.h"
  16#include "trace.h"
  17
  18static uint64_t loongarch_msi_mem_read(void *opaque, hwaddr addr, unsigned size)
  19{
  20    return 0;
  21}
  22
  23static void loongarch_msi_mem_write(void *opaque, hwaddr addr,
  24                                    uint64_t val, unsigned size)
  25{
  26    LoongArchPCHMSI *s = (LoongArchPCHMSI *)opaque;
  27    int irq_num;
  28
  29    /*
  30     * vector number is irq number from upper extioi intc
  31     * need subtract irq base to get msi vector offset
  32     */
  33    irq_num = (val & 0xff) - s->irq_base;
  34    trace_loongarch_msi_set_irq(irq_num);
  35    assert(irq_num < PCH_MSI_IRQ_NUM);
  36    qemu_set_irq(s->pch_msi_irq[irq_num], 1);
  37}
  38
  39static const MemoryRegionOps loongarch_pch_msi_ops = {
  40    .read  = loongarch_msi_mem_read,
  41    .write = loongarch_msi_mem_write,
  42    .endianness = DEVICE_LITTLE_ENDIAN,
  43};
  44
  45static void pch_msi_irq_handler(void *opaque, int irq, int level)
  46{
  47    LoongArchPCHMSI *s = LOONGARCH_PCH_MSI(opaque);
  48
  49    qemu_set_irq(s->pch_msi_irq[irq], level);
  50}
  51
  52static void loongarch_pch_msi_init(Object *obj)
  53{
  54    LoongArchPCHMSI *s = LOONGARCH_PCH_MSI(obj);
  55    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
  56
  57    memory_region_init_io(&s->msi_mmio, obj, &loongarch_pch_msi_ops,
  58                          s, TYPE_LOONGARCH_PCH_MSI, 0x8);
  59    sysbus_init_mmio(sbd, &s->msi_mmio);
  60    msi_nonbroken = true;
  61
  62    qdev_init_gpio_out(DEVICE(obj), s->pch_msi_irq, PCH_MSI_IRQ_NUM);
  63    qdev_init_gpio_in(DEVICE(obj), pch_msi_irq_handler, PCH_MSI_IRQ_NUM);
  64}
  65
  66static Property loongarch_msi_properties[] = {
  67    DEFINE_PROP_UINT32("msi_irq_base", LoongArchPCHMSI, irq_base, 0),
  68    DEFINE_PROP_END_OF_LIST(),
  69};
  70
  71static void loongarch_pch_msi_class_init(ObjectClass *klass, void *data)
  72{
  73    DeviceClass *dc = DEVICE_CLASS(klass);
  74
  75    device_class_set_props(dc, loongarch_msi_properties);
  76}
  77
  78static const TypeInfo loongarch_pch_msi_info = {
  79    .name          = TYPE_LOONGARCH_PCH_MSI,
  80    .parent        = TYPE_SYS_BUS_DEVICE,
  81    .instance_size = sizeof(LoongArchPCHMSI),
  82    .instance_init = loongarch_pch_msi_init,
  83    .class_init    = loongarch_pch_msi_class_init,
  84};
  85
  86static void loongarch_pch_msi_register_types(void)
  87{
  88    type_register_static(&loongarch_pch_msi_info);
  89}
  90
  91type_init(loongarch_pch_msi_register_types)
  92