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140#ifndef PPC_XIVE_H
141#define PPC_XIVE_H
142
143#include "sysemu/kvm.h"
144#include "hw/sysbus.h"
145#include "hw/ppc/xive_regs.h"
146#include "qom/object.h"
147
148
149
150
151
152typedef struct XiveNotifier XiveNotifier;
153
154#define TYPE_XIVE_NOTIFIER "xive-notifier"
155#define XIVE_NOTIFIER(obj) \
156 INTERFACE_CHECK(XiveNotifier, (obj), TYPE_XIVE_NOTIFIER)
157typedef struct XiveNotifierClass XiveNotifierClass;
158DECLARE_CLASS_CHECKERS(XiveNotifierClass, XIVE_NOTIFIER,
159 TYPE_XIVE_NOTIFIER)
160
161struct XiveNotifierClass {
162 InterfaceClass parent;
163 void (*notify)(XiveNotifier *xn, uint32_t lisn, bool pq_checked);
164};
165
166
167
168
169
170#define TYPE_XIVE_SOURCE "xive-source"
171OBJECT_DECLARE_SIMPLE_TYPE(XiveSource, XIVE_SOURCE)
172
173
174
175
176
177#define XIVE_SRC_H_INT_ESB 0x1
178#define XIVE_SRC_STORE_EOI 0x2
179#define XIVE_SRC_PQ_DISABLE 0x4
180
181struct XiveSource {
182 DeviceState parent;
183
184
185 uint32_t nr_irqs;
186 unsigned long *lsi_map;
187
188
189 uint8_t *status;
190
191
192 uint64_t esb_flags;
193 uint32_t esb_shift;
194 MemoryRegion esb_mmio;
195 MemoryRegion esb_mmio_emulated;
196
197
198 void *esb_mmap;
199 MemoryRegion esb_mmio_kvm;
200
201 XiveNotifier *xive;
202};
203
204
205
206
207
208
209#define XIVE_ESB_4K 12
210#define XIVE_ESB_4K_2PAGE 13
211#define XIVE_ESB_64K 16
212#define XIVE_ESB_64K_2PAGE 17
213
214static inline bool xive_source_esb_has_2page(XiveSource *xsrc)
215{
216 return xsrc->esb_shift == XIVE_ESB_64K_2PAGE ||
217 xsrc->esb_shift == XIVE_ESB_4K_2PAGE;
218}
219
220static inline size_t xive_source_esb_len(XiveSource *xsrc)
221{
222 return (1ull << xsrc->esb_shift) * xsrc->nr_irqs;
223}
224
225
226static inline hwaddr xive_source_esb_page(XiveSource *xsrc, uint32_t srcno)
227{
228 assert(srcno < xsrc->nr_irqs);
229 return (1ull << xsrc->esb_shift) * srcno;
230}
231
232
233static inline hwaddr xive_source_esb_mgmt(XiveSource *xsrc, int srcno)
234{
235 hwaddr addr = xive_source_esb_page(xsrc, srcno);
236
237 if (xive_source_esb_has_2page(xsrc)) {
238 addr += (1 << (xsrc->esb_shift - 1));
239 }
240
241 return addr;
242}
243
244
245
246
247
248
249
250
251
252
253
254
255
256#define XIVE_STATUS_ASSERTED 0x4
257#define XIVE_ESB_VAL_P 0x2
258#define XIVE_ESB_VAL_Q 0x1
259
260#define XIVE_ESB_RESET 0x0
261#define XIVE_ESB_PENDING XIVE_ESB_VAL_P
262#define XIVE_ESB_QUEUED (XIVE_ESB_VAL_P | XIVE_ESB_VAL_Q)
263#define XIVE_ESB_OFF XIVE_ESB_VAL_Q
264
265bool xive_esb_trigger(uint8_t *pq);
266bool xive_esb_eoi(uint8_t *pq);
267uint8_t xive_esb_set(uint8_t *pq, uint8_t value);
268
269
270
271
272
273
274
275
276
277
278
279#define XIVE_ESB_STORE_EOI 0x400
280#define XIVE_ESB_LOAD_EOI 0x000
281#define XIVE_ESB_GET 0x800
282#define XIVE_ESB_INJECT 0x800
283#define XIVE_ESB_SET_PQ_00 0xc00
284#define XIVE_ESB_SET_PQ_01 0xd00
285#define XIVE_ESB_SET_PQ_10 0xe00
286#define XIVE_ESB_SET_PQ_11 0xf00
287
288uint8_t xive_source_esb_get(XiveSource *xsrc, uint32_t srcno);
289uint8_t xive_source_esb_set(XiveSource *xsrc, uint32_t srcno, uint8_t pq);
290
291
292
293
294static inline void xive_source_set_status(XiveSource *xsrc, uint32_t srcno,
295 uint8_t status, bool enable)
296{
297 if (enable) {
298 xsrc->status[srcno] |= status;
299 } else {
300 xsrc->status[srcno] &= ~status;
301 }
302}
303
304static inline void xive_source_set_asserted(XiveSource *xsrc, uint32_t srcno,
305 bool enable)
306{
307 xive_source_set_status(xsrc, srcno, XIVE_STATUS_ASSERTED, enable);
308}
309
310static inline bool xive_source_is_asserted(XiveSource *xsrc, uint32_t srcno)
311{
312 return xsrc->status[srcno] & XIVE_STATUS_ASSERTED;
313}
314
315void xive_source_pic_print_info(XiveSource *xsrc, uint32_t offset,
316 Monitor *mon);
317
318static inline bool xive_source_irq_is_lsi(XiveSource *xsrc, uint32_t srcno)
319{
320 assert(srcno < xsrc->nr_irqs);
321 return test_bit(srcno, xsrc->lsi_map);
322}
323
324static inline void xive_source_irq_set_lsi(XiveSource *xsrc, uint32_t srcno)
325{
326 assert(srcno < xsrc->nr_irqs);
327 bitmap_set(xsrc->lsi_map, srcno, 1);
328}
329
330void xive_source_set_irq(void *opaque, int srcno, int val);
331
332
333
334
335
336#define TYPE_XIVE_TCTX "xive-tctx"
337OBJECT_DECLARE_SIMPLE_TYPE(XiveTCTX, XIVE_TCTX)
338
339
340
341
342
343
344
345
346
347#define XIVE_TM_RING_COUNT 4
348#define XIVE_TM_RING_SIZE 0x10
349
350typedef struct XivePresenter XivePresenter;
351
352struct XiveTCTX {
353 DeviceState parent_obj;
354
355 CPUState *cs;
356 qemu_irq hv_output;
357 qemu_irq os_output;
358
359 uint8_t regs[XIVE_TM_RING_COUNT * XIVE_TM_RING_SIZE];
360
361 XivePresenter *xptr;
362};
363
364static inline uint32_t xive_tctx_word2(uint8_t *ring)
365{
366 return *((uint32_t *) &ring[TM_WORD2]);
367}
368
369
370
371
372typedef struct XiveFabric XiveFabric;
373
374struct XiveRouter {
375 SysBusDevice parent;
376
377 XiveFabric *xfb;
378};
379
380#define TYPE_XIVE_ROUTER "xive-router"
381OBJECT_DECLARE_TYPE(XiveRouter, XiveRouterClass,
382 XIVE_ROUTER)
383
384struct XiveRouterClass {
385 SysBusDeviceClass parent;
386
387
388 int (*get_eas)(XiveRouter *xrtr, uint8_t eas_blk, uint32_t eas_idx,
389 XiveEAS *eas);
390 int (*get_pq)(XiveRouter *xrtr, uint8_t eas_blk, uint32_t eas_idx,
391 uint8_t *pq);
392 int (*set_pq)(XiveRouter *xrtr, uint8_t eas_blk, uint32_t eas_idx,
393 uint8_t *pq);
394 int (*get_end)(XiveRouter *xrtr, uint8_t end_blk, uint32_t end_idx,
395 XiveEND *end);
396 int (*write_end)(XiveRouter *xrtr, uint8_t end_blk, uint32_t end_idx,
397 XiveEND *end, uint8_t word_number);
398 int (*get_nvt)(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx,
399 XiveNVT *nvt);
400 int (*write_nvt)(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx,
401 XiveNVT *nvt, uint8_t word_number);
402 uint8_t (*get_block_id)(XiveRouter *xrtr);
403};
404
405int xive_router_get_eas(XiveRouter *xrtr, uint8_t eas_blk, uint32_t eas_idx,
406 XiveEAS *eas);
407int xive_router_get_end(XiveRouter *xrtr, uint8_t end_blk, uint32_t end_idx,
408 XiveEND *end);
409int xive_router_write_end(XiveRouter *xrtr, uint8_t end_blk, uint32_t end_idx,
410 XiveEND *end, uint8_t word_number);
411int xive_router_get_nvt(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx,
412 XiveNVT *nvt);
413int xive_router_write_nvt(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx,
414 XiveNVT *nvt, uint8_t word_number);
415void xive_router_notify(XiveNotifier *xn, uint32_t lisn, bool pq_checked);
416
417
418
419
420
421typedef struct XiveTCTXMatch {
422 XiveTCTX *tctx;
423 uint8_t ring;
424} XiveTCTXMatch;
425
426#define TYPE_XIVE_PRESENTER "xive-presenter"
427#define XIVE_PRESENTER(obj) \
428 INTERFACE_CHECK(XivePresenter, (obj), TYPE_XIVE_PRESENTER)
429typedef struct XivePresenterClass XivePresenterClass;
430DECLARE_CLASS_CHECKERS(XivePresenterClass, XIVE_PRESENTER,
431 TYPE_XIVE_PRESENTER)
432
433struct XivePresenterClass {
434 InterfaceClass parent;
435 int (*match_nvt)(XivePresenter *xptr, uint8_t format,
436 uint8_t nvt_blk, uint32_t nvt_idx,
437 bool cam_ignore, uint8_t priority,
438 uint32_t logic_serv, XiveTCTXMatch *match);
439 bool (*in_kernel)(const XivePresenter *xptr);
440};
441
442int xive_presenter_tctx_match(XivePresenter *xptr, XiveTCTX *tctx,
443 uint8_t format,
444 uint8_t nvt_blk, uint32_t nvt_idx,
445 bool cam_ignore, uint32_t logic_serv);
446bool xive_presenter_notify(XiveFabric *xfb, uint8_t format,
447 uint8_t nvt_blk, uint32_t nvt_idx,
448 bool cam_ignore, uint8_t priority,
449 uint32_t logic_serv);
450
451
452
453
454
455#define TYPE_XIVE_FABRIC "xive-fabric"
456#define XIVE_FABRIC(obj) \
457 INTERFACE_CHECK(XiveFabric, (obj), TYPE_XIVE_FABRIC)
458typedef struct XiveFabricClass XiveFabricClass;
459DECLARE_CLASS_CHECKERS(XiveFabricClass, XIVE_FABRIC,
460 TYPE_XIVE_FABRIC)
461
462struct XiveFabricClass {
463 InterfaceClass parent;
464 int (*match_nvt)(XiveFabric *xfb, uint8_t format,
465 uint8_t nvt_blk, uint32_t nvt_idx,
466 bool cam_ignore, uint8_t priority,
467 uint32_t logic_serv, XiveTCTXMatch *match);
468};
469
470
471
472
473
474#define TYPE_XIVE_END_SOURCE "xive-end-source"
475OBJECT_DECLARE_SIMPLE_TYPE(XiveENDSource, XIVE_END_SOURCE)
476
477struct XiveENDSource {
478 DeviceState parent;
479
480 uint32_t nr_ends;
481
482
483 uint32_t esb_shift;
484 MemoryRegion esb_mmio;
485
486 XiveRouter *xrtr;
487};
488
489
490
491
492
493
494#define XIVE_PRIORITY_MAX 7
495
496
497
498
499
500
501static inline uint8_t xive_priority_to_ipb(uint8_t priority)
502{
503 return priority > XIVE_PRIORITY_MAX ?
504 0 : 1 << (XIVE_PRIORITY_MAX - priority);
505}
506
507
508
509
510
511
512
513
514
515#define XIVE_TM_HW_PAGE 0x0
516#define XIVE_TM_HV_PAGE 0x1
517#define XIVE_TM_OS_PAGE 0x2
518#define XIVE_TM_USER_PAGE 0x3
519
520void xive_tctx_tm_write(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset,
521 uint64_t value, unsigned size);
522uint64_t xive_tctx_tm_read(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset,
523 unsigned size);
524
525void xive_tctx_pic_print_info(XiveTCTX *tctx, Monitor *mon);
526Object *xive_tctx_create(Object *cpu, XivePresenter *xptr, Error **errp);
527void xive_tctx_reset(XiveTCTX *tctx);
528void xive_tctx_destroy(XiveTCTX *tctx);
529void xive_tctx_ipb_update(XiveTCTX *tctx, uint8_t ring, uint8_t ipb);
530void xive_tctx_reset_os_signal(XiveTCTX *tctx);
531
532
533
534
535
536int kvmppc_xive_source_reset_one(XiveSource *xsrc, int srcno, Error **errp);
537void kvmppc_xive_source_set_irq(void *opaque, int srcno, int val);
538int kvmppc_xive_cpu_connect(XiveTCTX *tctx, Error **errp);
539int kvmppc_xive_cpu_synchronize_state(XiveTCTX *tctx, Error **errp);
540int kvmppc_xive_cpu_get_state(XiveTCTX *tctx, Error **errp);
541int kvmppc_xive_cpu_set_state(XiveTCTX *tctx, Error **errp);
542
543#endif
544