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21#ifndef CRIS_CPU_H
22#define CRIS_CPU_H
23
24#include "cpu-qom.h"
25#include "exec/cpu-defs.h"
26
27#define EXCP_NMI 1
28#define EXCP_GURU 2
29#define EXCP_BUSFAULT 3
30#define EXCP_IRQ 4
31#define EXCP_BREAK 5
32
33
34#define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3
35
36
37
38#define CRIS_CPU_IRQ 0
39#define CRIS_CPU_NMI 1
40
41
42#define R_FP 8
43#define R_SP 14
44#define R_ACR 15
45
46
47#define PR_BZ 0
48#define PR_VR 1
49#define PR_PID 2
50#define PR_SRS 3
51#define PR_WZ 4
52#define PR_EXS 5
53#define PR_EDA 6
54#define PR_PREFIX 6
55#define PR_MOF 7
56#define PR_DZ 8
57#define PR_EBP 9
58#define PR_ERP 10
59#define PR_SRP 11
60#define PR_NRP 12
61#define PR_CCS 13
62#define PR_USP 14
63#define PRV10_BRP 14
64#define PR_SPC 15
65
66
67#define Q_FLAG 0x80000000
68#define M_FLAG_V32 0x40000000
69#define PFIX_FLAG 0x800
70#define F_FLAG_V10 0x400
71#define P_FLAG_V10 0x200
72#define S_FLAG 0x200
73#define R_FLAG 0x100
74#define P_FLAG 0x80
75#define M_FLAG_V10 0x80
76#define U_FLAG 0x40
77#define I_FLAG 0x20
78#define X_FLAG 0x10
79#define N_FLAG 0x08
80#define Z_FLAG 0x04
81#define V_FLAG 0x02
82#define C_FLAG 0x01
83#define ALU_FLAGS 0x1F
84
85
86#define CC_CC 0
87#define CC_CS 1
88#define CC_NE 2
89#define CC_EQ 3
90#define CC_VC 4
91#define CC_VS 5
92#define CC_PL 6
93#define CC_MI 7
94#define CC_LS 8
95#define CC_HI 9
96#define CC_GE 10
97#define CC_LT 11
98#define CC_GT 12
99#define CC_LE 13
100#define CC_A 14
101#define CC_P 15
102
103typedef struct {
104 uint32_t hi;
105 uint32_t lo;
106} TLBSet;
107
108typedef struct CPUArchState {
109 uint32_t regs[16];
110
111 uint32_t pregs[16];
112
113
114 uint32_t pc;
115
116
117 uint32_t ksp;
118
119
120 int dslot;
121 int btaken;
122 uint32_t btarget;
123
124
125 uint32_t cc_op;
126 uint32_t cc_mask;
127 uint32_t cc_dest;
128 uint32_t cc_src;
129 uint32_t cc_result;
130
131 int cc_size;
132
133 int cc_x;
134
135
136 int locked_irq;
137 int interrupt_vector;
138 int fault_vector;
139 int trap_vector;
140
141
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145
146
147
148 uint32_t sregs[4][16];
149
150
151
152
153 uint32_t mmu_rand_lfsr;
154
155
156
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158
159
160
161 TLBSet tlbsets[2][4][16];
162
163
164 struct {} end_reset_fields;
165
166
167 void *load_info;
168} CPUCRISState;
169
170
171
172
173
174
175
176struct ArchCPU {
177
178 CPUState parent_obj;
179
180
181 CPUNegativeOffsetState neg;
182 CPUCRISState env;
183};
184
185
186#ifndef CONFIG_USER_ONLY
187extern const VMStateDescription vmstate_cris_cpu;
188
189void cris_cpu_do_interrupt(CPUState *cpu);
190void crisv10_cpu_do_interrupt(CPUState *cpu);
191bool cris_cpu_exec_interrupt(CPUState *cpu, int int_req);
192
193bool cris_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
194 MMUAccessType access_type, int mmu_idx,
195 bool probe, uintptr_t retaddr);
196#endif
197
198void cris_cpu_dump_state(CPUState *cs, FILE *f, int flags);
199
200hwaddr cris_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
201
202int crisv10_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
203int cris_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
204int cris_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
205
206void cris_initialize_tcg(void);
207void cris_initialize_crisv10_tcg(void);
208
209
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211
212
213
214
215
216enum {
217 CC_OP_DYNAMIC,
218 CC_OP_FLAGS,
219 CC_OP_CMP,
220 CC_OP_MOVE,
221 CC_OP_ADD,
222 CC_OP_ADDC,
223 CC_OP_MCP,
224 CC_OP_ADDU,
225 CC_OP_SUB,
226 CC_OP_SUBU,
227 CC_OP_NEG,
228 CC_OP_BTST,
229 CC_OP_MULS,
230 CC_OP_MULU,
231 CC_OP_DSTEP,
232 CC_OP_MSTEP,
233 CC_OP_BOUND,
234
235 CC_OP_OR,
236 CC_OP_AND,
237 CC_OP_XOR,
238 CC_OP_LSL,
239 CC_OP_LSR,
240 CC_OP_ASR,
241 CC_OP_LZ
242};
243
244
245#define MMAP_SHIFT TARGET_PAGE_BITS
246
247#define CRIS_CPU_TYPE_SUFFIX "-" TYPE_CRIS_CPU
248#define CRIS_CPU_TYPE_NAME(name) (name CRIS_CPU_TYPE_SUFFIX)
249#define CPU_RESOLVING_TYPE TYPE_CRIS_CPU
250
251
252#define MMU_USER_IDX 1
253static inline int cpu_mmu_index (CPUCRISState *env, bool ifetch)
254{
255 return !!(env->pregs[PR_CCS] & U_FLAG);
256}
257
258
259#define SFR_RW_GC_CFG 0][0
260#define SFR_RW_MM_CFG env->pregs[PR_SRS]][0
261#define SFR_RW_MM_KBASE_LO env->pregs[PR_SRS]][1
262#define SFR_RW_MM_KBASE_HI env->pregs[PR_SRS]][2
263#define SFR_R_MM_CAUSE env->pregs[PR_SRS]][3
264#define SFR_RW_MM_TLB_SEL env->pregs[PR_SRS]][4
265#define SFR_RW_MM_TLB_LO env->pregs[PR_SRS]][5
266#define SFR_RW_MM_TLB_HI env->pregs[PR_SRS]][6
267
268#include "exec/cpu-all.h"
269
270static inline void cpu_get_tb_cpu_state(CPUCRISState *env, target_ulong *pc,
271 target_ulong *cs_base, uint32_t *flags)
272{
273 *pc = env->pc;
274 *cs_base = 0;
275 *flags = env->dslot |
276 (env->pregs[PR_CCS] & (S_FLAG | P_FLAG | U_FLAG
277 | X_FLAG | PFIX_FLAG));
278}
279
280#define cpu_list cris_cpu_list
281void cris_cpu_list(void);
282
283#endif
284