LXR qemu/target/loongarch/insn_trans/trans

   1/* SPDX-License-Identifier: GPL-2.0-or-later */
   2/*
   3 * Copyright (c) 2021 Loongson Technology Corporation Limited
   4 */
   5
   6static bool trans_break(DisasContext *ctx, arg_break *a)
   7{
   8    generate_exception(ctx, EXCCODE_BRK);
   9    return true;
  10}
  11
  12static bool trans_syscall(DisasContext *ctx, arg_syscall *a)
  13{
  14    generate_exception(ctx, EXCCODE_SYS);
  15    return true;
  16}
  17
  18static bool trans_asrtle_d(DisasContext *ctx, arg_asrtle_d * a)
  19{
  20    TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);
  21    TCGv src2 = gpr_src(ctx, a->rk, EXT_NONE);
  22
  23    gen_helper_asrtle_d(cpu_env, src1, src2);
  24    return true;
  25}
  26
  27static bool trans_asrtgt_d(DisasContext *ctx, arg_asrtgt_d * a)
  28{
  29    TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);
  30    TCGv src2 = gpr_src(ctx, a->rk, EXT_NONE);
  31
  32    gen_helper_asrtgt_d(cpu_env, src1, src2);
  33    return true;
  34}
  35
  36static bool gen_rdtime(DisasContext *ctx, arg_rr *a,
  37                       bool word, bool high)
  38{
  39    TCGv dst1 = gpr_dst(ctx, a->rd, EXT_NONE);
  40    TCGv dst2 = gpr_dst(ctx, a->rj, EXT_NONE);
  41
  42    if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
  43        gen_io_start();
  44    }
  45    gen_helper_rdtime_d(dst1, cpu_env);
  46    if (word) {
  47        tcg_gen_sextract_tl(dst1, dst1, high ? 32 : 0, 32);
  48    }
  49    tcg_gen_ld_i64(dst2, cpu_env, offsetof(CPULoongArchState, CSR_TID));
  50
  51    return true;
  52}
  53
  54static bool trans_rdtimel_w(DisasContext *ctx, arg_rdtimel_w *a)
  55{
  56    return gen_rdtime(ctx, a, 1, 0);
  57}
  58
  59static bool trans_rdtimeh_w(DisasContext *ctx, arg_rdtimeh_w *a)
  60{
  61    return gen_rdtime(ctx, a, 1, 1);
  62}
  63
  64static bool trans_rdtime_d(DisasContext *ctx, arg_rdtime_d *a)
  65{
  66    return gen_rdtime(ctx, a, 0, 0);
  67}
  68
  69static bool trans_cpucfg(DisasContext *ctx, arg_cpucfg *a)
  70{
  71    TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE);
  72    TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);
  73
  74    gen_helper_cpucfg(dest, cpu_env, src1);
  75    gen_set_gpr(a->rd, dest, EXT_NONE);
  76
  77    return true;
  78}
  79
  80static bool gen_crc(DisasContext *ctx, arg_rrr *a,
  81                    void (*func)(TCGv, TCGv, TCGv, TCGv),
  82                    TCGv tsz)
  83{
  84    TCGv dest = gpr_dst(ctx, a->rd, EXT_SIGN);
  85    TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);
  86    TCGv src2 = gpr_src(ctx, a->rk, EXT_NONE);
  87
  88    func(dest, src2, src1, tsz);
  89    gen_set_gpr(a->rd, dest, EXT_SIGN);
  90
  91    return true;
  92}
  93
  94TRANS(crc_w_b_w, gen_crc, gen_helper_crc32, tcg_constant_tl(1))
  95TRANS(crc_w_h_w, gen_crc, gen_helper_crc32, tcg_constant_tl(2))
  96TRANS(crc_w_w_w, gen_crc, gen_helper_crc32, tcg_constant_tl(4))
  97TRANS(crc_w_d_w, gen_crc, gen_helper_crc32, tcg_constant_tl(8))
  98TRANS(crcc_w_b_w, gen_crc, gen_helper_crc32c, tcg_constant_tl(1))
  99TRANS(crcc_w_h_w, gen_crc, gen_helper_crc32c, tcg_constant_tl(2))
 100TRANS(crcc_w_w_w, gen_crc, gen_helper_crc32c, tcg_constant_tl(4))
 101TRANS(crcc_w_d_w, gen_crc, gen_helper_crc32c, tcg_constant_tl(8))
 102