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20#ifndef QEMU_PPC_CPU_QOM_H
21#define QEMU_PPC_CPU_QOM_H
22
23#include "hw/core/cpu.h"
24#include "qom/object.h"
25
26#ifdef TARGET_PPC64
27#define TYPE_POWERPC_CPU "powerpc64-cpu"
28#else
29#define TYPE_POWERPC_CPU "powerpc-cpu"
30#endif
31
32OBJECT_DECLARE_CPU_TYPE(PowerPCCPU, PowerPCCPUClass, POWERPC_CPU)
33
34typedef struct CPUArchState CPUPPCState;
35typedef struct ppc_tb_t ppc_tb_t;
36typedef struct ppc_dcr_t ppc_dcr_t;
37
38
39
40typedef enum powerpc_mmu_t powerpc_mmu_t;
41enum powerpc_mmu_t {
42 POWERPC_MMU_UNKNOWN = 0x00000000,
43
44 POWERPC_MMU_32B = 0x00000001,
45
46 POWERPC_MMU_SOFT_6xx = 0x00000002,
47
48
49
50
51
52 POWERPC_MMU_SOFT_74xx = 0x00000003,
53
54 POWERPC_MMU_SOFT_4xx = 0x00000004,
55
56 POWERPC_MMU_REAL = 0x00000006,
57
58 POWERPC_MMU_MPC8xx = 0x00000007,
59
60 POWERPC_MMU_BOOKE = 0x00000008,
61
62 POWERPC_MMU_BOOKE206 = 0x00000009,
63#define POWERPC_MMU_64 0x00010000
64
65 POWERPC_MMU_64B = POWERPC_MMU_64 | 0x00000001,
66
67 POWERPC_MMU_2_03 = POWERPC_MMU_64 | 0x00000002,
68
69 POWERPC_MMU_2_06 = POWERPC_MMU_64 | 0x00000003,
70
71 POWERPC_MMU_2_07 = POWERPC_MMU_64 | 0x00000004,
72
73 POWERPC_MMU_3_00 = POWERPC_MMU_64 | 0x00000005,
74};
75
76static inline bool mmu_is_64bit(powerpc_mmu_t mmu_model)
77{
78 return mmu_model & POWERPC_MMU_64;
79}
80
81
82
83typedef enum powerpc_excp_t powerpc_excp_t;
84enum powerpc_excp_t {
85 POWERPC_EXCP_UNKNOWN = 0,
86
87 POWERPC_EXCP_STD,
88
89 POWERPC_EXCP_40x,
90
91 POWERPC_EXCP_6xx,
92
93 POWERPC_EXCP_7xx,
94
95 POWERPC_EXCP_74xx,
96
97 POWERPC_EXCP_BOOKE,
98
99 POWERPC_EXCP_970,
100
101 POWERPC_EXCP_POWER7,
102
103 POWERPC_EXCP_POWER8,
104
105 POWERPC_EXCP_POWER9,
106
107 POWERPC_EXCP_POWER10,
108};
109
110
111
112typedef enum {
113 PPC_PM_DOZE,
114 PPC_PM_NAP,
115 PPC_PM_SLEEP,
116 PPC_PM_RVWINKLE,
117 PPC_PM_STOP,
118} powerpc_pm_insn_t;
119
120
121
122typedef enum powerpc_input_t powerpc_input_t;
123enum powerpc_input_t {
124 PPC_FLAGS_INPUT_UNKNOWN = 0,
125
126 PPC_FLAGS_INPUT_6xx,
127
128 PPC_FLAGS_INPUT_BookE,
129
130 PPC_FLAGS_INPUT_405,
131
132 PPC_FLAGS_INPUT_970,
133
134 PPC_FLAGS_INPUT_POWER7,
135
136 PPC_FLAGS_INPUT_POWER9,
137
138 PPC_FLAGS_INPUT_RCPU,
139};
140
141typedef struct PPCHash64Options PPCHash64Options;
142
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147
148
149
150struct PowerPCCPUClass {
151
152 CPUClass parent_class;
153
154
155 DeviceRealize parent_realize;
156 DeviceUnrealize parent_unrealize;
157 DeviceReset parent_reset;
158 void (*parent_parse_features)(const char *type, char *str, Error **errp);
159
160 uint32_t pvr;
161
162
163
164
165 bool (*pvr_match)(struct PowerPCCPUClass *pcc, uint32_t pvr, bool best);
166 uint64_t pcr_mask;
167 uint64_t pcr_supported;
168 uint32_t svr;
169 uint64_t insns_flags;
170 uint64_t insns_flags2;
171 uint64_t msr_mask;
172 uint64_t lpcr_mask;
173 uint64_t lpcr_pm;
174 powerpc_mmu_t mmu_model;
175 powerpc_excp_t excp_model;
176 powerpc_input_t bus_model;
177 uint32_t flags;
178 int bfd_mach;
179 uint32_t l1_dcache_size, l1_icache_size;
180#ifndef CONFIG_USER_ONLY
181 unsigned int gdb_num_sprs;
182 const char *gdb_spr_xml;
183#endif
184 const PPCHash64Options *hash64_opts;
185 struct ppc_radix_page_info *radix_page_info;
186 uint32_t lrg_decr_bits;
187 int n_host_threads;
188 void (*init_proc)(CPUPPCState *env);
189 int (*check_pow)(CPUPPCState *env);
190};
191
192#ifndef CONFIG_USER_ONLY
193typedef struct PPCTimebase {
194 uint64_t guest_timebase;
195 int64_t time_of_the_day_ns;
196 bool runstate_paused;
197} PPCTimebase;
198
199extern const VMStateDescription vmstate_ppc_timebase;
200
201#define VMSTATE_PPC_TIMEBASE_V(_field, _state, _version) { \
202 .name = (stringify(_field)), \
203 .version_id = (_version), \
204 .size = sizeof(PPCTimebase), \
205 .vmsd = &vmstate_ppc_timebase, \
206 .flags = VMS_STRUCT, \
207 .offset = vmstate_offset_value(_state, _field, PPCTimebase), \
208}
209
210void cpu_ppc_clock_vm_state_change(void *opaque, bool running,
211 RunState state);
212#endif
213
214#endif
215