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25#include "qemu/osdep.h"
26#include <getopt.h>
27
28#include "libqtest.h"
29#include "libqos/libqos-pc.h"
30#include "libqos/ahci.h"
31#include "libqos/pci-pc.h"
32
33#include "qapi/qmp/qdict.h"
34#include "qemu/host-utils.h"
35
36#include "hw/pci/pci_ids.h"
37#include "hw/pci/pci_regs.h"
38
39
40#define qmp_discard_response(s, ...) qobject_unref(qtest_qmp(s, __VA_ARGS__))
41
42
43#define TEST_IMAGE_SIZE_MB_LARGE (200 * 1024)
44#define TEST_IMAGE_SIZE_MB_SMALL 64
45
46
47static char *tmp_path;
48static char *debug_path;
49static char *mig_socket;
50static bool ahci_pedantic;
51static const char *imgfmt;
52static unsigned test_image_size_mb;
53
54
55static void ahci_test_port_spec(AHCIQState *ahci, uint8_t port);
56static void ahci_test_pci_spec(AHCIQState *ahci);
57static void ahci_test_pci_caps(AHCIQState *ahci, uint16_t header,
58 uint8_t offset);
59static void ahci_test_satacap(AHCIQState *ahci, uint8_t offset);
60static void ahci_test_msicap(AHCIQState *ahci, uint8_t offset);
61static void ahci_test_pmcap(AHCIQState *ahci, uint8_t offset);
62
63
64
65static uint64_t mb_to_sectors(uint64_t image_size_mb)
66{
67 return (image_size_mb * 1024 * 1024) / AHCI_SECTOR_SIZE;
68}
69
70static void string_bswap16(uint16_t *s, size_t bytes)
71{
72 g_assert_cmphex((bytes & 1), ==, 0);
73 bytes /= 2;
74
75 while (bytes--) {
76 *s = bswap16(*s);
77 s++;
78 }
79}
80
81
82
83
84static void verify_state(AHCIQState *ahci, uint64_t hba_old)
85{
86 int i, j;
87 uint32_t ahci_fingerprint;
88 uint64_t hba_base;
89 AHCICommandHeader cmd;
90
91 ahci_fingerprint = qpci_config_readl(ahci->dev, PCI_VENDOR_ID);
92 g_assert_cmphex(ahci_fingerprint, ==, ahci->fingerprint);
93
94
95 if (!ahci->enabled) {
96 return;
97 }
98
99 hba_base = (uint64_t)qpci_config_readl(ahci->dev, PCI_BASE_ADDRESS_5);
100 g_assert_cmphex(hba_base, ==, hba_old);
101
102 g_assert_cmphex(ahci_rreg(ahci, AHCI_CAP), ==, ahci->cap);
103 g_assert_cmphex(ahci_rreg(ahci, AHCI_CAP2), ==, ahci->cap2);
104
105 for (i = 0; i < 32; i++) {
106 g_assert_cmphex(ahci_px_rreg(ahci, i, AHCI_PX_FB), ==,
107 ahci->port[i].fb);
108 g_assert_cmphex(ahci_px_rreg(ahci, i, AHCI_PX_CLB), ==,
109 ahci->port[i].clb);
110 for (j = 0; j < 32; j++) {
111 ahci_get_command_header(ahci, i, j, &cmd);
112 g_assert_cmphex(cmd.prdtl, ==, ahci->port[i].prdtl[j]);
113 g_assert_cmphex(cmd.ctba, ==, ahci->port[i].ctba[j]);
114 }
115 }
116}
117
118static void ahci_migrate(AHCIQState *from, AHCIQState *to, const char *uri)
119{
120 QOSState *tmp = to->parent;
121 QPCIDevice *dev = to->dev;
122 char *uri_local = NULL;
123 uint64_t hba_old;
124
125 if (uri == NULL) {
126 uri_local = g_strdup_printf("%s%s", "unix:", mig_socket);
127 uri = uri_local;
128 }
129
130 hba_old = (uint64_t)qpci_config_readl(from->dev, PCI_BASE_ADDRESS_5);
131
132
133 migrate(from->parent, to->parent, uri);
134
135
136
137
138 memcpy(to, from, sizeof(AHCIQState));
139 to->parent = tmp;
140 to->dev = dev;
141
142 tmp = from->parent;
143 dev = from->dev;
144 memset(from, 0x00, sizeof(AHCIQState));
145 from->parent = tmp;
146 from->dev = dev;
147
148 verify_state(to, hba_old);
149 g_free(uri_local);
150}
151
152
153
154
155
156
157static AHCIQState *ahci_vboot(const char *cli, va_list ap)
158{
159 AHCIQState *s;
160
161 s = g_new0(AHCIQState, 1);
162 s->parent = qtest_pc_vboot(cli, ap);
163 alloc_set_flags(&s->parent->alloc, ALLOC_LEAK_ASSERT);
164
165
166 s->dev = get_ahci_device(s->parent->qts, &s->fingerprint);
167
168 return s;
169}
170
171
172
173
174static AHCIQState *ahci_boot(const char *cli, ...)
175{
176 AHCIQState *s;
177 va_list ap;
178
179 if (cli) {
180 va_start(ap, cli);
181 s = ahci_vboot(cli, ap);
182 va_end(ap);
183 } else {
184 cli = "-drive if=none,id=drive0,file=%s,cache=writeback,format=%s"
185 " -M q35 "
186 "-device ide-hd,drive=drive0 "
187 "-global ide-hd.serial=%s "
188 "-global ide-hd.ver=%s";
189 s = ahci_boot(cli, tmp_path, imgfmt, "testdisk", "version");
190 }
191
192 return s;
193}
194
195
196
197
198static void ahci_shutdown(AHCIQState *ahci)
199{
200 QOSState *qs = ahci->parent;
201
202 ahci_clean_mem(ahci);
203 free_ahci_device(ahci->dev);
204 g_free(ahci);
205 qtest_shutdown(qs);
206}
207
208
209
210
211
212static AHCIQState *ahci_boot_and_enable(const char *cli, ...)
213{
214 AHCIQState *ahci;
215 va_list ap;
216 uint16_t buff[256];
217 uint8_t port;
218 uint8_t hello;
219
220 if (cli) {
221 va_start(ap, cli);
222 ahci = ahci_vboot(cli, ap);
223 va_end(ap);
224 } else {
225 ahci = ahci_boot(NULL);
226 }
227
228 ahci_pci_enable(ahci);
229 ahci_hba_enable(ahci);
230
231 port = ahci_port_select(ahci);
232 ahci_port_clear(ahci, port);
233 if (is_atapi(ahci, port)) {
234 hello = CMD_PACKET_ID;
235 } else {
236 hello = CMD_IDENTIFY;
237 }
238 ahci_io(ahci, port, hello, &buff, sizeof(buff), 0);
239
240 return ahci;
241}
242
243
244
245
246
247
248static void ahci_test_pci_spec(AHCIQState *ahci)
249{
250 uint8_t datab;
251 uint16_t data;
252 uint32_t datal;
253
254
255 data = qpci_config_readw(ahci->dev, PCI_COMMAND);
256 ASSERT_BIT_CLEAR(data, PCI_COMMAND_MEMORY);
257 ASSERT_BIT_CLEAR(data, PCI_COMMAND_MASTER);
258 ASSERT_BIT_CLEAR(data, PCI_COMMAND_SPECIAL);
259 ASSERT_BIT_CLEAR(data, PCI_COMMAND_VGA_PALETTE);
260 ASSERT_BIT_CLEAR(data, PCI_COMMAND_PARITY);
261 ASSERT_BIT_CLEAR(data, PCI_COMMAND_WAIT);
262 ASSERT_BIT_CLEAR(data, PCI_COMMAND_SERR);
263 ASSERT_BIT_CLEAR(data, PCI_COMMAND_FAST_BACK);
264 ASSERT_BIT_CLEAR(data, PCI_COMMAND_INTX_DISABLE);
265 ASSERT_BIT_CLEAR(data, 0xF800);
266
267 data = qpci_config_readw(ahci->dev, PCI_STATUS);
268 ASSERT_BIT_CLEAR(data, 0x01 | 0x02 | 0x04);
269 ASSERT_BIT_CLEAR(data, PCI_STATUS_INTERRUPT);
270 ASSERT_BIT_SET(data, PCI_STATUS_CAP_LIST);
271 ASSERT_BIT_CLEAR(data, PCI_STATUS_UDF);
272 ASSERT_BIT_CLEAR(data, PCI_STATUS_PARITY);
273 ASSERT_BIT_CLEAR(data, PCI_STATUS_SIG_TARGET_ABORT);
274 ASSERT_BIT_CLEAR(data, PCI_STATUS_REC_TARGET_ABORT);
275 ASSERT_BIT_CLEAR(data, PCI_STATUS_REC_MASTER_ABORT);
276 ASSERT_BIT_CLEAR(data, PCI_STATUS_SIG_SYSTEM_ERROR);
277 ASSERT_BIT_CLEAR(data, PCI_STATUS_DETECTED_PARITY);
278
279
280 datal = qpci_config_readl(ahci->dev, PCI_CLASS_REVISION);
281 if (ahci_pedantic) {
282
283
284 ASSERT_BIT_CLEAR(datal, 0xFF);
285 }
286
287
288 g_assert_cmphex(PCI_BCC(datal), ==, 0x01);
289 if (PCI_SCC(datal) == 0x01) {
290
291 ASSERT_BIT_SET(0x80000000, datal);
292 ASSERT_BIT_CLEAR(0x60000000, datal);
293 } else if (PCI_SCC(datal) == 0x04) {
294
295 g_assert_cmphex(PCI_PI(datal), ==, 0);
296 } else if (PCI_SCC(datal) == 0x06) {
297
298 g_assert_cmphex(PCI_PI(datal), ==, 0x01);
299 } else {
300 g_assert_not_reached();
301 }
302
303 datab = qpci_config_readb(ahci->dev, PCI_CACHE_LINE_SIZE);
304 g_assert_cmphex(datab, ==, 0);
305
306 datab = qpci_config_readb(ahci->dev, PCI_LATENCY_TIMER);
307 g_assert_cmphex(datab, ==, 0);
308
309
310 datab = qpci_config_readb(ahci->dev, PCI_HEADER_TYPE);
311 ASSERT_BIT_CLEAR(datab, 0x7F);
312
313
314 datab = qpci_config_readb(ahci->dev, PCI_BIST);
315 ASSERT_BIT_CLEAR(datab, 0x7F);
316
317
318 datal = qpci_config_readl(ahci->dev, PCI_BASE_ADDRESS_5);
319 g_assert_cmphex(datal, ==, 0);
320
321 qpci_config_writel(ahci->dev, PCI_BASE_ADDRESS_5, 0xFFFFFFFF);
322 datal = qpci_config_readl(ahci->dev, PCI_BASE_ADDRESS_5);
323
324
325 ASSERT_BIT_CLEAR(datal, 0xFF);
326
327
328 datal = qpci_config_readl(ahci->dev, PCI_CAPABILITY_LIST);
329
330 ASSERT_BIT_CLEAR(datal, ~0xFF);
331 g_assert_cmphex(datal, !=, 0);
332
333
334 data = qpci_config_readw(ahci->dev, datal);
335
336 switch (ahci->fingerprint) {
337 case AHCI_INTEL_ICH9:
338
339 g_assert_cmphex((data & 0xFF), ==, PCI_CAP_ID_MSI);
340 break;
341 default:
342
343 g_assert_cmphex((data & 0xFF), ==, PCI_CAP_ID_PM);
344 }
345
346 ahci_test_pci_caps(ahci, data, (uint8_t)datal);
347
348
349 datal = qpci_config_readl(ahci->dev, PCI_CAPABILITY_LIST + 4);
350 g_assert_cmphex(datal, ==, 0);
351
352
353 datab = qpci_config_readb(ahci->dev, PCI_INTERRUPT_LINE);
354 g_assert_cmphex(datab, ==, 0);
355}
356
357
358
359
360static void ahci_test_pci_caps(AHCIQState *ahci, uint16_t header,
361 uint8_t offset)
362{
363 uint8_t cid = header & 0xFF;
364 uint8_t next = header >> 8;
365
366 g_test_message("CID: %02x; next: %02x", cid, next);
367
368 switch (cid) {
369 case PCI_CAP_ID_PM:
370 ahci_test_pmcap(ahci, offset);
371 break;
372 case PCI_CAP_ID_MSI:
373 ahci_test_msicap(ahci, offset);
374 break;
375 case PCI_CAP_ID_SATA:
376 ahci_test_satacap(ahci, offset);
377 break;
378
379 default:
380 g_test_message("Unknown CAP 0x%02x", cid);
381 }
382
383 if (next) {
384 ahci_test_pci_caps(ahci, qpci_config_readw(ahci->dev, next), next);
385 }
386}
387
388
389
390
391static void ahci_test_satacap(AHCIQState *ahci, uint8_t offset)
392{
393 uint16_t dataw;
394 uint32_t datal;
395
396 g_test_message("Verifying SATACAP");
397
398
399 dataw = qpci_config_readw(ahci->dev, offset + 2);
400 g_assert_cmphex(dataw, ==, 0x10);
401
402
403 datal = qpci_config_readw(ahci->dev, offset + 4);
404
405 switch (datal & 0x0F) {
406 case 0x04:
407 case 0x05:
408 case 0x06:
409 case 0x07:
410 case 0x08:
411 case 0x09:
412 case 0x0F:
413 break;
414 default:
415
416 g_assert_not_reached();
417 }
418
419
420 g_assert_cmphex((datal >> 24), ==, 0x00);
421}
422
423
424
425
426static void ahci_test_msicap(AHCIQState *ahci, uint8_t offset)
427{
428 uint16_t dataw;
429 uint32_t datal;
430
431 g_test_message("Verifying MSICAP");
432
433 dataw = qpci_config_readw(ahci->dev, offset + PCI_MSI_FLAGS);
434 ASSERT_BIT_CLEAR(dataw, PCI_MSI_FLAGS_ENABLE);
435 ASSERT_BIT_CLEAR(dataw, PCI_MSI_FLAGS_QSIZE);
436 ASSERT_BIT_CLEAR(dataw, PCI_MSI_FLAGS_RESERVED);
437
438 datal = qpci_config_readl(ahci->dev, offset + PCI_MSI_ADDRESS_LO);
439 g_assert_cmphex(datal, ==, 0);
440
441 if (dataw & PCI_MSI_FLAGS_64BIT) {
442 g_test_message("MSICAP is 64bit");
443 datal = qpci_config_readl(ahci->dev, offset + PCI_MSI_ADDRESS_HI);
444 g_assert_cmphex(datal, ==, 0);
445 dataw = qpci_config_readw(ahci->dev, offset + PCI_MSI_DATA_64);
446 g_assert_cmphex(dataw, ==, 0);
447 } else {
448 g_test_message("MSICAP is 32bit");
449 dataw = qpci_config_readw(ahci->dev, offset + PCI_MSI_DATA_32);
450 g_assert_cmphex(dataw, ==, 0);
451 }
452}
453
454
455
456
457static void ahci_test_pmcap(AHCIQState *ahci, uint8_t offset)
458{
459 uint16_t dataw;
460
461 g_test_message("Verifying PMCAP");
462
463 dataw = qpci_config_readw(ahci->dev, offset + PCI_PM_PMC);
464 ASSERT_BIT_CLEAR(dataw, PCI_PM_CAP_PME_CLOCK);
465 ASSERT_BIT_CLEAR(dataw, PCI_PM_CAP_RESERVED);
466 ASSERT_BIT_CLEAR(dataw, PCI_PM_CAP_D1);
467 ASSERT_BIT_CLEAR(dataw, PCI_PM_CAP_D2);
468
469 dataw = qpci_config_readw(ahci->dev, offset + PCI_PM_CTRL);
470 ASSERT_BIT_CLEAR(dataw, PCI_PM_CTRL_STATE_MASK);
471 ASSERT_BIT_CLEAR(dataw, PCI_PM_CTRL_RESERVED);
472 ASSERT_BIT_CLEAR(dataw, PCI_PM_CTRL_DATA_SEL_MASK);
473 ASSERT_BIT_CLEAR(dataw, PCI_PM_CTRL_DATA_SCALE_MASK);
474}
475
476static void ahci_test_hba_spec(AHCIQState *ahci)
477{
478 unsigned i;
479 uint32_t reg;
480 uint32_t ports;
481 uint8_t nports_impl;
482 uint8_t maxports;
483
484 g_assert(ahci != NULL);
485
486
487
488
489
490
491
492
493
494
495
496
497
498
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501
502
503
504
505
506
507 ahci->cap = ahci_rreg(ahci, AHCI_CAP);
508 ASSERT_BIT_CLEAR(ahci->cap, AHCI_CAP_RESERVED);
509
510
511 reg = ahci_rreg(ahci, AHCI_GHC);
512 ASSERT_BIT_CLEAR(reg, AHCI_GHC_HR);
513 ASSERT_BIT_CLEAR(reg, AHCI_GHC_IE);
514 ASSERT_BIT_CLEAR(reg, AHCI_GHC_MRSM);
515 if (BITSET(ahci->cap, AHCI_CAP_SAM)) {
516 g_test_message("Supports AHCI-Only Mode: GHC_AE is Read-Only.");
517 ASSERT_BIT_SET(reg, AHCI_GHC_AE);
518 } else {
519 g_test_message("Supports AHCI/Legacy mix.");
520 ASSERT_BIT_CLEAR(reg, AHCI_GHC_AE);
521 }
522
523
524 reg = ahci_rreg(ahci, AHCI_IS);
525 g_assert_cmphex(reg, ==, 0);
526
527
528 ports = ahci_rreg(ahci, AHCI_PI);
529
530 g_assert_cmphex(ports, !=, 0);
531
532 nports_impl = ctpopl(ports);
533 g_assert_cmpuint(((AHCI_CAP_NP & ahci->cap) + 1), >=, nports_impl);
534
535
536
537
538 g_assert_cmphex(ahci->barsize, >, 0);
539 maxports = (ahci->barsize - HBA_DATA_REGION_SIZE) / HBA_PORT_DATA_SIZE;
540
541 g_assert_cmphex((reg >> maxports), ==, 0);
542
543
544 reg = ahci_rreg(ahci, AHCI_VS);
545 switch (reg) {
546 case AHCI_VERSION_0_95:
547 case AHCI_VERSION_1_0:
548 case AHCI_VERSION_1_1:
549 case AHCI_VERSION_1_2:
550 case AHCI_VERSION_1_3:
551 break;
552 default:
553 g_assert_not_reached();
554 }
555
556
557 reg = ahci_rreg(ahci, AHCI_CCCCTL);
558 if (BITSET(ahci->cap, AHCI_CAP_CCCS)) {
559 ASSERT_BIT_CLEAR(reg, AHCI_CCCCTL_EN);
560 ASSERT_BIT_CLEAR(reg, AHCI_CCCCTL_RESERVED);
561 ASSERT_BIT_SET(reg, AHCI_CCCCTL_CC);
562 ASSERT_BIT_SET(reg, AHCI_CCCCTL_TV);
563 } else {
564 g_assert_cmphex(reg, ==, 0);
565 }
566
567
568 reg = ahci_rreg(ahci, AHCI_CCCPORTS);
569
570 g_assert_cmphex(reg, ==, 0);
571
572
573 reg = ahci_rreg(ahci, AHCI_EMLOC);
574 if (BITCLR(ahci->cap, AHCI_CAP_EMS)) {
575 g_assert_cmphex(reg, ==, 0);
576 }
577
578
579 reg = ahci_rreg(ahci, AHCI_EMCTL);
580 if (BITSET(ahci->cap, AHCI_CAP_EMS)) {
581 ASSERT_BIT_CLEAR(reg, AHCI_EMCTL_STSMR);
582 ASSERT_BIT_CLEAR(reg, AHCI_EMCTL_CTLTM);
583 ASSERT_BIT_CLEAR(reg, AHCI_EMCTL_CTLRST);
584 ASSERT_BIT_CLEAR(reg, AHCI_EMCTL_RESERVED);
585 } else {
586 g_assert_cmphex(reg, ==, 0);
587 }
588
589
590 ahci->cap2 = ahci_rreg(ahci, AHCI_CAP2);
591 ASSERT_BIT_CLEAR(ahci->cap2, AHCI_CAP2_RESERVED);
592
593
594 reg = ahci_rreg(ahci, AHCI_BOHC);
595 g_assert_cmphex(reg, ==, 0);
596
597
598 g_test_message("Verifying HBA reserved area is empty.");
599 for (i = AHCI_RESERVED; i < AHCI_NVMHCI; ++i) {
600 reg = ahci_rreg(ahci, i);
601 g_assert_cmphex(reg, ==, 0);
602 }
603
604
605 if (BITCLR(ahci->cap2, AHCI_CAP2_NVMP)) {
606 g_test_message("Verifying HBA/NVMHCI area is empty.");
607 for (i = AHCI_NVMHCI; i < AHCI_VENDOR; ++i) {
608 reg = ahci_rreg(ahci, i);
609 g_assert_cmphex(reg, ==, 0);
610 }
611 }
612
613
614 g_test_message("Verifying HBA/Vendor area is empty.");
615 for (i = AHCI_VENDOR; i < AHCI_PORTS; ++i) {
616 reg = ahci_rreg(ahci, i);
617 g_assert_cmphex(reg, ==, 0);
618 }
619
620
621 for (i = 0; ports || (i < maxports); ports >>= 1, ++i) {
622 if (BITSET(ports, 0x1)) {
623 g_test_message("Testing port %u for spec", i);
624 ahci_test_port_spec(ahci, i);
625 } else {
626 uint16_t j;
627 uint16_t low = AHCI_PORTS + (32 * i);
628 uint16_t high = AHCI_PORTS + (32 * (i + 1));
629 g_test_message("Asserting unimplemented port %u "
630 "(reg [%u-%u]) is empty.",
631 i, low, high - 1);
632 for (j = low; j < high; ++j) {
633 reg = ahci_rreg(ahci, j);
634 g_assert_cmphex(reg, ==, 0);
635 }
636 }
637 }
638}
639
640
641
642
643static void ahci_test_port_spec(AHCIQState *ahci, uint8_t port)
644{
645 uint32_t reg;
646 unsigned i;
647
648
649 reg = ahci_px_rreg(ahci, port, AHCI_PX_CLB);
650 ASSERT_BIT_CLEAR(reg, AHCI_PX_CLB_RESERVED);
651
652
653 if (BITCLR(ahci->cap, AHCI_CAP_S64A)) {
654 reg = ahci_px_rreg(ahci, port, AHCI_PX_CLBU);
655 g_assert_cmphex(reg, ==, 0);
656 }
657
658
659 reg = ahci_px_rreg(ahci, port, AHCI_PX_FB);
660 ASSERT_BIT_CLEAR(reg, AHCI_PX_FB_RESERVED);
661
662
663 if (BITCLR(ahci->cap, AHCI_CAP_S64A)) {
664 reg = ahci_px_rreg(ahci, port, AHCI_PX_FBU);
665 g_assert_cmphex(reg, ==, 0);
666 }
667
668
669 reg = ahci_px_rreg(ahci, port, AHCI_PX_IS);
670 g_assert_cmphex(reg, ==, 0);
671
672
673 reg = ahci_px_rreg(ahci, port, AHCI_PX_IE);
674 g_assert_cmphex(reg, ==, 0);
675
676
677 reg = ahci_px_rreg(ahci, port, AHCI_PX_CMD);
678 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_FRE);
679 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_RESERVED);
680 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_CCS);
681 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_FR);
682 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_CR);
683 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_PMA);
684 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_APSTE);
685 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_ATAPI);
686 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_DLAE);
687 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_ALPE);
688 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_ASP);
689 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_ICC);
690
691 if (BITCLR(reg, AHCI_PX_CMD_CPD)) {
692 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_CPS);
693 }
694
695 if (BITCLR(reg, AHCI_PX_CMD_MPSP)) {
696 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_MPSS);
697 }
698
699 if (BITCLR(ahci->cap, AHCI_CAP_SMPS)) {
700 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_MPSS);
701 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_MPSP);
702 }
703
704 if (BITANY(reg, AHCI_PX_CMD_CPD | AHCI_PX_CMD_MPSP)) {
705 ASSERT_BIT_SET(reg, AHCI_PX_CMD_HPCP);
706 }
707
708 g_assert(!BITSET(reg, AHCI_PX_CMD_HPCP | AHCI_PX_CMD_ESP));
709
710 if (BITCLR(ahci->cap, AHCI_CAP_FBSS)) {
711 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_FBSCP);
712 }
713
714
715 reg = ahci_px_rreg(ahci, port, AHCI_PX_RES1);
716 g_assert_cmphex(reg, ==, 0);
717
718
719 reg = ahci_px_rreg(ahci, port, AHCI_PX_TFD);
720
721
722 ASSERT_BIT_SET(reg, AHCI_PX_TFD_STS_ERR);
723 ASSERT_BIT_SET(reg, AHCI_PX_TFD_STS_CS1);
724 ASSERT_BIT_SET(reg, AHCI_PX_TFD_STS_DRQ);
725 ASSERT_BIT_SET(reg, AHCI_PX_TFD_STS_CS2);
726 ASSERT_BIT_CLEAR(reg, AHCI_PX_TFD_STS_BSY);
727 ASSERT_BIT_CLEAR(reg, AHCI_PX_TFD_ERR);
728 ASSERT_BIT_CLEAR(reg, AHCI_PX_TFD_RESERVED);
729
730
731
732
733
734
735
736
737 reg = ahci_px_rreg(ahci, port, AHCI_PX_SSTS);
738 ASSERT_BIT_CLEAR(reg, AHCI_PX_SSTS_RESERVED);
739
740
741
742
743 reg = ahci_px_rreg(ahci, port, AHCI_PX_SCTL);
744 g_assert_cmphex(reg, ==, 0);
745
746
747 reg = ahci_px_rreg(ahci, port, AHCI_PX_SERR);
748 g_assert_cmphex(reg, ==, 0);
749
750
751 reg = ahci_px_rreg(ahci, port, AHCI_PX_SACT);
752 g_assert_cmphex(reg, ==, 0);
753
754
755 reg = ahci_px_rreg(ahci, port, AHCI_PX_CI);
756 g_assert_cmphex(reg, ==, 0);
757
758
759 reg = ahci_px_rreg(ahci, port, AHCI_PX_SNTF);
760 g_assert_cmphex(reg, ==, 0);
761
762
763 reg = ahci_px_rreg(ahci, port, AHCI_PX_FBS);
764 ASSERT_BIT_CLEAR(reg, AHCI_PX_FBS_EN);
765 ASSERT_BIT_CLEAR(reg, AHCI_PX_FBS_DEC);
766 ASSERT_BIT_CLEAR(reg, AHCI_PX_FBS_SDE);
767 ASSERT_BIT_CLEAR(reg, AHCI_PX_FBS_DEV);
768 ASSERT_BIT_CLEAR(reg, AHCI_PX_FBS_DWE);
769 ASSERT_BIT_CLEAR(reg, AHCI_PX_FBS_RESERVED);
770 if (BITSET(ahci->cap, AHCI_CAP_FBSS)) {
771
772 g_assert((reg & AHCI_PX_FBS_ADO) >> ctzl(AHCI_PX_FBS_ADO) >= 2);
773 }
774
775
776 for (i = AHCI_PX_RES2; i < AHCI_PX_VS; ++i) {
777 reg = ahci_px_rreg(ahci, port, i);
778 g_assert_cmphex(reg, ==, 0);
779 }
780
781
782 for (i = AHCI_PX_VS; i < 32; ++i) {
783 reg = ahci_px_rreg(ahci, port, i);
784 if (reg) {
785 g_test_message("INFO: Vendor register %u non-empty", i);
786 }
787 }
788}
789
790
791
792
793
794static void ahci_test_identify(AHCIQState *ahci)
795{
796 uint16_t buff[256];
797 unsigned px;
798 int rc;
799 uint16_t sect_size;
800 const size_t buffsize = 512;
801
802 g_assert(ahci != NULL);
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826 px = ahci_port_select(ahci);
827 g_test_message("Selected port %u for test", px);
828
829
830 ahci_port_clear(ahci, px);
831
832
833 ahci_io(ahci, px, CMD_IDENTIFY, &buff, buffsize, 0);
834
835
836
837
838
839
840 string_bswap16(&buff[10], 20);
841 rc = memcmp(&buff[10], "testdisk ", 20);
842 g_assert_cmphex(rc, ==, 0);
843
844 string_bswap16(&buff[23], 8);
845 rc = memcmp(&buff[23], "version ", 8);
846 g_assert_cmphex(rc, ==, 0);
847
848 sect_size = le16_to_cpu(*((uint16_t *)(&buff[5])));
849 g_assert_cmphex(sect_size, ==, AHCI_SECTOR_SIZE);
850}
851
852static void ahci_test_io_rw_simple(AHCIQState *ahci, unsigned bufsize,
853 uint64_t sector, uint8_t read_cmd,
854 uint8_t write_cmd)
855{
856 uint64_t ptr;
857 uint8_t port;
858 unsigned char *tx = g_malloc(bufsize);
859 unsigned char *rx = g_malloc0(bufsize);
860
861 g_assert(ahci != NULL);
862
863
864 port = ahci_port_select(ahci);
865 ahci_port_clear(ahci, port);
866
867
868
869 ptr = ahci_alloc(ahci, bufsize);
870 g_assert(ptr);
871
872
873 generate_pattern(tx, bufsize, AHCI_SECTOR_SIZE);
874 qtest_bufwrite(ahci->parent->qts, ptr, tx, bufsize);
875
876
877 ahci_guest_io(ahci, port, write_cmd, ptr, bufsize, sector);
878 qtest_memset(ahci->parent->qts, ptr, 0x00, bufsize);
879 ahci_guest_io(ahci, port, read_cmd, ptr, bufsize, sector);
880
881
882 qtest_bufread(ahci->parent->qts, ptr, rx, bufsize);
883 g_assert_cmphex(memcmp(tx, rx, bufsize), ==, 0);
884
885 ahci_free(ahci, ptr);
886 g_free(tx);
887 g_free(rx);
888}
889
890static uint8_t ahci_test_nondata(AHCIQState *ahci, uint8_t ide_cmd)
891{
892 uint8_t port;
893
894
895 port = ahci_port_select(ahci);
896 ahci_port_clear(ahci, port);
897
898 ahci_io(ahci, port, ide_cmd, NULL, 0, 0);
899
900 return port;
901}
902
903static void ahci_test_flush(AHCIQState *ahci)
904{
905 ahci_test_nondata(ahci, CMD_FLUSH_CACHE);
906}
907
908static void ahci_test_max(AHCIQState *ahci)
909{
910 RegD2HFIS *d2h = g_malloc0(0x20);
911 uint64_t nsect;
912 uint8_t port;
913 uint8_t cmd;
914 uint64_t config_sect = mb_to_sectors(test_image_size_mb) - 1;
915
916 if (config_sect > 0xFFFFFF) {
917 cmd = CMD_READ_MAX_EXT;
918 } else {
919 cmd = CMD_READ_MAX;
920 }
921
922 port = ahci_test_nondata(ahci, cmd);
923 qtest_memread(ahci->parent->qts, ahci->port[port].fb + 0x40, d2h, 0x20);
924 nsect = (uint64_t)d2h->lba_hi[2] << 40 |
925 (uint64_t)d2h->lba_hi[1] << 32 |
926 (uint64_t)d2h->lba_hi[0] << 24 |
927 (uint64_t)d2h->lba_lo[2] << 16 |
928 (uint64_t)d2h->lba_lo[1] << 8 |
929 (uint64_t)d2h->lba_lo[0];
930
931 g_assert_cmphex(nsect, ==, config_sect);
932 g_free(d2h);
933}
934
935
936
937
938
939
940
941
942
943static void test_sanity(void)
944{
945 AHCIQState *ahci;
946 ahci = ahci_boot(NULL);
947 ahci_shutdown(ahci);
948}
949
950
951
952
953
954static void test_pci_spec(void)
955{
956 AHCIQState *ahci;
957 ahci = ahci_boot(NULL);
958 ahci_test_pci_spec(ahci);
959 ahci_shutdown(ahci);
960}
961
962
963
964
965
966static void test_pci_enable(void)
967{
968 AHCIQState *ahci;
969 ahci = ahci_boot(NULL);
970 ahci_pci_enable(ahci);
971 ahci_shutdown(ahci);
972}
973
974
975
976
977
978static void test_hba_spec(void)
979{
980 AHCIQState *ahci;
981
982 ahci = ahci_boot(NULL);
983 ahci_pci_enable(ahci);
984 ahci_test_hba_spec(ahci);
985 ahci_shutdown(ahci);
986}
987
988
989
990
991
992static void test_hba_enable(void)
993{
994 AHCIQState *ahci;
995
996 ahci = ahci_boot(NULL);
997 ahci_pci_enable(ahci);
998 ahci_hba_enable(ahci);
999 ahci_shutdown(ahci);
1000}
1001
1002
1003
1004
1005
1006static void test_identify(void)
1007{
1008 AHCIQState *ahci;
1009
1010 ahci = ahci_boot_and_enable(NULL);
1011 ahci_test_identify(ahci);
1012 ahci_shutdown(ahci);
1013}
1014
1015
1016
1017
1018
1019
1020
1021static void test_dma_fragmented(void)
1022{
1023 AHCIQState *ahci;
1024 AHCICommand *cmd;
1025 uint8_t px;
1026 size_t bufsize = 4096;
1027 unsigned char *tx = g_malloc(bufsize);
1028 unsigned char *rx = g_malloc0(bufsize);
1029 uint64_t ptr;
1030
1031 ahci = ahci_boot_and_enable(NULL);
1032 px = ahci_port_select(ahci);
1033 ahci_port_clear(ahci, px);
1034
1035
1036 generate_pattern(tx, bufsize, AHCI_SECTOR_SIZE);
1037
1038
1039 ptr = guest_alloc(&ahci->parent->alloc, bufsize);
1040 g_assert(ptr);
1041 qtest_bufwrite(ahci->parent->qts, ptr, tx, bufsize);
1042
1043 cmd = ahci_command_create(CMD_WRITE_DMA);
1044 ahci_command_adjust(cmd, 0, ptr, bufsize, 32);
1045 ahci_command_commit(ahci, cmd, px);
1046 ahci_command_issue(ahci, cmd);
1047 ahci_command_verify(ahci, cmd);
1048 ahci_command_free(cmd);
1049
1050 cmd = ahci_command_create(CMD_READ_DMA);
1051 ahci_command_adjust(cmd, 0, ptr, bufsize, 32);
1052 ahci_command_commit(ahci, cmd, px);
1053 ahci_command_issue(ahci, cmd);
1054 ahci_command_verify(ahci, cmd);
1055 ahci_command_free(cmd);
1056
1057
1058 qtest_bufread(ahci->parent->qts, ptr, rx, bufsize);
1059 guest_free(&ahci->parent->alloc, ptr);
1060
1061 g_assert_cmphex(memcmp(tx, rx, bufsize), ==, 0);
1062
1063 ahci_shutdown(ahci);
1064
1065 g_free(rx);
1066 g_free(tx);
1067}
1068
1069
1070
1071
1072
1073static void make_dirty(AHCIQState* ahci, uint8_t port)
1074{
1075 uint64_t ptr;
1076 unsigned bufsize = 512;
1077
1078 ptr = ahci_alloc(ahci, bufsize);
1079 g_assert(ptr);
1080
1081 ahci_guest_io(ahci, port, CMD_WRITE_DMA, ptr, bufsize, 1);
1082 ahci_free(ahci, ptr);
1083}
1084
1085static void test_flush(void)
1086{
1087 AHCIQState *ahci;
1088 uint8_t port;
1089
1090 ahci = ahci_boot_and_enable(NULL);
1091
1092 port = ahci_port_select(ahci);
1093 ahci_port_clear(ahci, port);
1094
1095 make_dirty(ahci, port);
1096
1097 ahci_test_flush(ahci);
1098 ahci_shutdown(ahci);
1099}
1100
1101static void test_flush_retry(void)
1102{
1103 AHCIQState *ahci;
1104 AHCICommand *cmd;
1105 uint8_t port;
1106
1107 prepare_blkdebug_script(debug_path, "flush_to_disk");
1108 ahci = ahci_boot_and_enable("-drive file=blkdebug:%s:%s,if=none,id=drive0,"
1109 "format=%s,cache=writeback,"
1110 "rerror=stop,werror=stop "
1111 "-M q35 "
1112 "-device ide-hd,drive=drive0 ",
1113 debug_path,
1114 tmp_path, imgfmt);
1115
1116 port = ahci_port_select(ahci);
1117 ahci_port_clear(ahci, port);
1118
1119
1120 make_dirty(ahci, port);
1121
1122
1123 cmd = ahci_guest_io_halt(ahci, port, CMD_FLUSH_CACHE, 0, 0, 0);
1124 ahci_guest_io_resume(ahci, cmd);
1125
1126 ahci_shutdown(ahci);
1127}
1128
1129
1130
1131
1132static void test_migrate_sanity(void)
1133{
1134 AHCIQState *src, *dst;
1135 char *uri = g_strdup_printf("unix:%s", mig_socket);
1136
1137 src = ahci_boot("-m 384 -M q35 "
1138 "-drive if=ide,file=%s,format=%s ", tmp_path, imgfmt);
1139 dst = ahci_boot("-m 384 -M q35 "
1140 "-drive if=ide,file=%s,format=%s "
1141 "-incoming %s", tmp_path, imgfmt, uri);
1142
1143 ahci_migrate(src, dst, uri);
1144
1145 ahci_shutdown(src);
1146 ahci_shutdown(dst);
1147 g_free(uri);
1148}
1149
1150
1151
1152
1153static void ahci_migrate_simple(uint8_t cmd_read, uint8_t cmd_write)
1154{
1155 AHCIQState *src, *dst;
1156 uint8_t px;
1157 size_t bufsize = 4096;
1158 unsigned char *tx = g_malloc(bufsize);
1159 unsigned char *rx = g_malloc0(bufsize);
1160 char *uri = g_strdup_printf("unix:%s", mig_socket);
1161
1162 src = ahci_boot_and_enable("-m 384 -M q35 "
1163 "-drive if=ide,format=%s,file=%s ",
1164 imgfmt, tmp_path);
1165 dst = ahci_boot("-m 384 -M q35 "
1166 "-drive if=ide,format=%s,file=%s "
1167 "-incoming %s", imgfmt, tmp_path, uri);
1168
1169
1170 px = ahci_port_select(src);
1171 ahci_port_clear(src, px);
1172
1173
1174 generate_pattern(tx, bufsize, AHCI_SECTOR_SIZE);
1175
1176
1177 ahci_io(src, px, cmd_write, tx, bufsize, 0);
1178 ahci_migrate(src, dst, uri);
1179 ahci_io(dst, px, cmd_read, rx, bufsize, 0);
1180
1181
1182 g_assert_cmphex(memcmp(tx, rx, bufsize), ==, 0);
1183
1184 ahci_shutdown(src);
1185 ahci_shutdown(dst);
1186 g_free(rx);
1187 g_free(tx);
1188 g_free(uri);
1189}
1190
1191static void test_migrate_dma(void)
1192{
1193 ahci_migrate_simple(CMD_READ_DMA, CMD_WRITE_DMA);
1194}
1195
1196static void test_migrate_ncq(void)
1197{
1198 ahci_migrate_simple(READ_FPDMA_QUEUED, WRITE_FPDMA_QUEUED);
1199}
1200
1201
1202
1203
1204
1205
1206
1207
1208static void ahci_halted_io_test(uint8_t cmd_read, uint8_t cmd_write)
1209{
1210 AHCIQState *ahci;
1211 uint8_t port;
1212 size_t bufsize = 4096;
1213 unsigned char *tx = g_malloc(bufsize);
1214 unsigned char *rx = g_malloc0(bufsize);
1215 uint64_t ptr;
1216 AHCICommand *cmd;
1217
1218 prepare_blkdebug_script(debug_path, "write_aio");
1219
1220 ahci = ahci_boot_and_enable("-drive file=blkdebug:%s:%s,if=none,id=drive0,"
1221 "format=%s,cache=writeback,"
1222 "rerror=stop,werror=stop "
1223 "-M q35 "
1224 "-device ide-hd,drive=drive0 ",
1225 debug_path,
1226 tmp_path, imgfmt);
1227
1228
1229 port = ahci_port_select(ahci);
1230 ahci_port_clear(ahci, port);
1231
1232
1233 generate_pattern(tx, bufsize, AHCI_SECTOR_SIZE);
1234 ptr = ahci_alloc(ahci, bufsize);
1235 g_assert(ptr);
1236 qtest_memwrite(ahci->parent->qts, ptr, tx, bufsize);
1237
1238
1239 cmd = ahci_guest_io_halt(ahci, port, cmd_write,
1240 ptr, bufsize, 0);
1241
1242
1243 ahci_guest_io_resume(ahci, cmd);
1244 ahci_free(ahci, ptr);
1245
1246
1247 ahci_io(ahci, port, cmd_read, rx, bufsize, 0);
1248 g_assert_cmphex(memcmp(tx, rx, bufsize), ==, 0);
1249
1250
1251 ahci_shutdown(ahci);
1252 g_free(rx);
1253 g_free(tx);
1254}
1255
1256static void test_halted_dma(void)
1257{
1258 ahci_halted_io_test(CMD_READ_DMA, CMD_WRITE_DMA);
1259}
1260
1261static void test_halted_ncq(void)
1262{
1263 ahci_halted_io_test(READ_FPDMA_QUEUED, WRITE_FPDMA_QUEUED);
1264}
1265
1266
1267
1268
1269
1270
1271
1272
1273static void ahci_migrate_halted_io(uint8_t cmd_read, uint8_t cmd_write)
1274{
1275 AHCIQState *src, *dst;
1276 uint8_t port;
1277 size_t bufsize = 4096;
1278 unsigned char *tx = g_malloc(bufsize);
1279 unsigned char *rx = g_malloc0(bufsize);
1280 uint64_t ptr;
1281 AHCICommand *cmd;
1282 char *uri = g_strdup_printf("unix:%s", mig_socket);
1283
1284 prepare_blkdebug_script(debug_path, "write_aio");
1285
1286 src = ahci_boot_and_enable("-drive file=blkdebug:%s:%s,if=none,id=drive0,"
1287 "format=%s,cache=writeback,"
1288 "rerror=stop,werror=stop "
1289 "-M q35 "
1290 "-device ide-hd,drive=drive0 ",
1291 debug_path,
1292 tmp_path, imgfmt);
1293
1294 dst = ahci_boot("-drive file=%s,if=none,id=drive0,"
1295 "format=%s,cache=writeback,"
1296 "rerror=stop,werror=stop "
1297 "-M q35 "
1298 "-device ide-hd,drive=drive0 "
1299 "-incoming %s",
1300 tmp_path, imgfmt, uri);
1301
1302
1303 port = ahci_port_select(src);
1304 ahci_port_clear(src, port);
1305 generate_pattern(tx, bufsize, AHCI_SECTOR_SIZE);
1306
1307
1308 ptr = ahci_alloc(src, bufsize);
1309 g_assert(ptr);
1310 qtest_memwrite(src->parent->qts, ptr, tx, bufsize);
1311
1312
1313 cmd = ahci_guest_io_halt(src, port, cmd_write,
1314 ptr, bufsize, 0);
1315 ahci_migrate(src, dst, uri);
1316 ahci_guest_io_resume(dst, cmd);
1317 ahci_free(dst, ptr);
1318
1319
1320 ahci_io(dst, port, cmd_read, rx, bufsize, 0);
1321
1322
1323 g_assert_cmphex(memcmp(tx, rx, bufsize), ==, 0);
1324
1325
1326 ahci_shutdown(src);
1327 ahci_shutdown(dst);
1328 g_free(rx);
1329 g_free(tx);
1330 g_free(uri);
1331}
1332
1333static void test_migrate_halted_dma(void)
1334{
1335 ahci_migrate_halted_io(CMD_READ_DMA, CMD_WRITE_DMA);
1336}
1337
1338static void test_migrate_halted_ncq(void)
1339{
1340 ahci_migrate_halted_io(READ_FPDMA_QUEUED, WRITE_FPDMA_QUEUED);
1341}
1342
1343
1344
1345
1346static void test_flush_migrate(void)
1347{
1348 AHCIQState *src, *dst;
1349 AHCICommand *cmd;
1350 uint8_t px;
1351 char *uri = g_strdup_printf("unix:%s", mig_socket);
1352
1353 prepare_blkdebug_script(debug_path, "flush_to_disk");
1354
1355 src = ahci_boot_and_enable("-drive file=blkdebug:%s:%s,if=none,id=drive0,"
1356 "cache=writeback,rerror=stop,werror=stop,"
1357 "format=%s "
1358 "-M q35 "
1359 "-device ide-hd,drive=drive0 ",
1360 debug_path, tmp_path, imgfmt);
1361 dst = ahci_boot("-drive file=%s,if=none,id=drive0,"
1362 "cache=writeback,rerror=stop,werror=stop,"
1363 "format=%s "
1364 "-M q35 "
1365 "-device ide-hd,drive=drive0 "
1366 "-incoming %s", tmp_path, imgfmt, uri);
1367
1368 px = ahci_port_select(src);
1369 ahci_port_clear(src, px);
1370
1371
1372 make_dirty(src, px);
1373
1374
1375 cmd = ahci_command_create(CMD_FLUSH_CACHE);
1376 ahci_command_commit(src, cmd, px);
1377 ahci_command_issue_async(src, cmd);
1378 qtest_qmp_eventwait(src->parent->qts, "STOP");
1379
1380
1381 ahci_migrate(src, dst, uri);
1382
1383
1384 qtest_qmp_send(dst->parent->qts, "{'execute':'cont' }");
1385 qtest_qmp_eventwait(dst->parent->qts, "RESUME");
1386 ahci_command_wait(dst, cmd);
1387 ahci_command_verify(dst, cmd);
1388
1389 ahci_command_free(cmd);
1390 ahci_shutdown(src);
1391 ahci_shutdown(dst);
1392 g_free(uri);
1393}
1394
1395static void test_max(void)
1396{
1397 AHCIQState *ahci;
1398
1399 ahci = ahci_boot_and_enable(NULL);
1400 ahci_test_max(ahci);
1401 ahci_shutdown(ahci);
1402}
1403
1404static void test_reset(void)
1405{
1406 AHCIQState *ahci;
1407 int i;
1408
1409 ahci = ahci_boot(NULL);
1410 ahci_test_pci_spec(ahci);
1411 ahci_pci_enable(ahci);
1412
1413 for (i = 0; i < 2; i++) {
1414 ahci_test_hba_spec(ahci);
1415 ahci_hba_enable(ahci);
1416 ahci_test_identify(ahci);
1417 ahci_test_io_rw_simple(ahci, 4096, 0,
1418 CMD_READ_DMA_EXT,
1419 CMD_WRITE_DMA_EXT);
1420 ahci_set(ahci, AHCI_GHC, AHCI_GHC_HR);
1421 ahci_clean_mem(ahci);
1422 }
1423
1424 ahci_shutdown(ahci);
1425}
1426
1427static void test_ncq_simple(void)
1428{
1429 AHCIQState *ahci;
1430
1431 ahci = ahci_boot_and_enable(NULL);
1432 ahci_test_io_rw_simple(ahci, 4096, 0,
1433 READ_FPDMA_QUEUED,
1434 WRITE_FPDMA_QUEUED);
1435 ahci_shutdown(ahci);
1436}
1437
1438static int prepare_iso(size_t size, unsigned char **buf, char **name)
1439{
1440 g_autofree char *cdrom_path = NULL;
1441 unsigned char *patt;
1442 ssize_t ret;
1443 int fd = g_file_open_tmp("qtest.iso.XXXXXX", &cdrom_path, NULL);
1444
1445 g_assert(fd != -1);
1446 g_assert(buf);
1447 g_assert(name);
1448 patt = g_malloc(size);
1449
1450
1451 generate_pattern(patt, size, ATAPI_SECTOR_SIZE);
1452 ret = write(fd, patt, size);
1453 g_assert(ret == size);
1454
1455 *name = g_strdup(cdrom_path);
1456 *buf = patt;
1457 return fd;
1458}
1459
1460static void remove_iso(int fd, char *name)
1461{
1462 unlink(name);
1463 g_free(name);
1464 close(fd);
1465}
1466
1467static int ahci_cb_cmp_buff(AHCIQState *ahci, AHCICommand *cmd,
1468 const AHCIOpts *opts)
1469{
1470 unsigned char *tx = opts->opaque;
1471 unsigned char *rx;
1472
1473 if (!opts->size) {
1474 return 0;
1475 }
1476
1477 rx = g_malloc0(opts->size);
1478 qtest_bufread(ahci->parent->qts, opts->buffer, rx, opts->size);
1479 g_assert_cmphex(memcmp(tx, rx, opts->size), ==, 0);
1480 g_free(rx);
1481
1482 return 0;
1483}
1484
1485static void ahci_test_cdrom(int nsectors, bool dma, uint8_t cmd,
1486 bool override_bcl, uint16_t bcl)
1487{
1488 AHCIQState *ahci;
1489 unsigned char *tx;
1490 char *iso;
1491 int fd;
1492 AHCIOpts opts = {
1493 .size = ((uint64_t)ATAPI_SECTOR_SIZE * nsectors),
1494 .atapi = true,
1495 .atapi_dma = dma,
1496 .post_cb = ahci_cb_cmp_buff,
1497 .set_bcl = override_bcl,
1498 .bcl = bcl,
1499 };
1500 uint64_t iso_size = (uint64_t)ATAPI_SECTOR_SIZE * (nsectors + 1);
1501
1502
1503 fd = prepare_iso(iso_size, &tx, &iso);
1504 opts.opaque = tx;
1505
1506
1507 ahci = ahci_boot_and_enable("-drive if=none,id=drive0,file=%s,format=raw "
1508 "-M q35 "
1509 "-device ide-cd,drive=drive0 ", iso);
1510
1511
1512 ahci_exec(ahci, ahci_port_select(ahci), cmd, &opts);
1513
1514
1515 g_free(tx);
1516 ahci_shutdown(ahci);
1517 remove_iso(fd, iso);
1518}
1519
1520static void ahci_test_cdrom_read10(int nsectors, bool dma)
1521{
1522 ahci_test_cdrom(nsectors, dma, CMD_ATAPI_READ_10, false, 0);
1523}
1524
1525static void test_cdrom_dma(void)
1526{
1527 ahci_test_cdrom_read10(1, true);
1528}
1529
1530static void test_cdrom_dma_multi(void)
1531{
1532 ahci_test_cdrom_read10(3, true);
1533}
1534
1535static void test_cdrom_pio(void)
1536{
1537 ahci_test_cdrom_read10(1, false);
1538}
1539
1540static void test_cdrom_pio_multi(void)
1541{
1542 ahci_test_cdrom_read10(3, false);
1543}
1544
1545
1546
1547static void test_atapi_bcl(void)
1548{
1549 ahci_test_cdrom(0, false, CMD_ATAPI_READ_CD, true, 0);
1550}
1551
1552
1553static void atapi_wait_tray(AHCIQState *ahci, bool open)
1554{
1555 QDict *rsp = qtest_qmp_eventwait_ref(ahci->parent->qts,
1556 "DEVICE_TRAY_MOVED");
1557 QDict *data = qdict_get_qdict(rsp, "data");
1558 if (open) {
1559 g_assert(qdict_get_bool(data, "tray-open"));
1560 } else {
1561 g_assert(!qdict_get_bool(data, "tray-open"));
1562 }
1563 qobject_unref(rsp);
1564}
1565
1566static void test_atapi_tray(void)
1567{
1568 AHCIQState *ahci;
1569 unsigned char *tx;
1570 char *iso;
1571 int fd;
1572 uint8_t port, sense, asc;
1573 uint64_t iso_size = ATAPI_SECTOR_SIZE;
1574 QDict *rsp;
1575
1576 fd = prepare_iso(iso_size, &tx, &iso);
1577 ahci = ahci_boot_and_enable("-blockdev node-name=drive0,driver=file,filename=%s "
1578 "-M q35 "
1579 "-device ide-cd,id=cd0,drive=drive0 ", iso);
1580 port = ahci_port_select(ahci);
1581
1582 ahci_atapi_eject(ahci, port);
1583 atapi_wait_tray(ahci, true);
1584
1585 ahci_atapi_load(ahci, port);
1586 atapi_wait_tray(ahci, false);
1587
1588
1589 qtest_qmp_send(ahci->parent->qts, "{'execute': 'blockdev-open-tray', "
1590 "'arguments': {'id': 'cd0'}}");
1591 atapi_wait_tray(ahci, true);
1592 rsp = qtest_qmp_receive(ahci->parent->qts);
1593 qobject_unref(rsp);
1594
1595 qmp_discard_response(ahci->parent->qts,
1596 "{'execute': 'blockdev-remove-medium', "
1597 "'arguments': {'id': 'cd0'}}");
1598
1599
1600 ahci_atapi_load(ahci, port);
1601 atapi_wait_tray(ahci, false);
1602
1603 ahci_atapi_eject(ahci, port);
1604 atapi_wait_tray(ahci, true);
1605
1606
1607 qmp_discard_response(ahci->parent->qts,
1608 "{'execute': 'blockdev-add', "
1609 "'arguments': {'node-name': 'node0', "
1610 "'driver': 'raw', "
1611 "'file': { 'driver': 'file', "
1612 "'filename': %s }}}", iso);
1613 qmp_discard_response(ahci->parent->qts,
1614 "{'execute': 'blockdev-insert-medium',"
1615 "'arguments': { 'id': 'cd0', "
1616 "'node-name': 'node0' }}");
1617
1618
1619 qtest_qmp_send(ahci->parent->qts, "{'execute': 'blockdev-close-tray', "
1620 "'arguments': {'id': 'cd0'}}");
1621 atapi_wait_tray(ahci, false);
1622 rsp = qtest_qmp_receive(ahci->parent->qts);
1623 qobject_unref(rsp);
1624
1625
1626 ahci_atapi_test_ready(ahci, port, false, SENSE_NOT_READY);
1627 ahci_atapi_get_sense(ahci, port, &sense, &asc);
1628 g_assert_cmpuint(sense, ==, SENSE_NOT_READY);
1629 g_assert_cmpuint(asc, ==, ASC_MEDIUM_NOT_PRESENT);
1630
1631 ahci_atapi_test_ready(ahci, port, false, SENSE_UNIT_ATTENTION);
1632 ahci_atapi_get_sense(ahci, port, &sense, &asc);
1633 g_assert_cmpuint(sense, ==, SENSE_UNIT_ATTENTION);
1634 g_assert_cmpuint(asc, ==, ASC_MEDIUM_MAY_HAVE_CHANGED);
1635
1636 ahci_atapi_test_ready(ahci, port, true, SENSE_NO_SENSE);
1637 ahci_atapi_get_sense(ahci, port, &sense, &asc);
1638 g_assert_cmpuint(sense, ==, SENSE_NO_SENSE);
1639
1640
1641 ahci_atapi_eject(ahci, port);
1642 atapi_wait_tray(ahci, true);
1643
1644 ahci_atapi_load(ahci, port);
1645 atapi_wait_tray(ahci, false);
1646
1647
1648 g_free(tx);
1649 ahci_shutdown(ahci);
1650 remove_iso(fd, iso);
1651}
1652
1653
1654
1655
1656enum BuffLen {
1657 LEN_BEGIN = 0,
1658 LEN_SIMPLE = LEN_BEGIN,
1659 LEN_DOUBLE,
1660 LEN_LONG,
1661 LEN_SHORT,
1662 NUM_LENGTHS
1663};
1664
1665static const char *buff_len_str[NUM_LENGTHS] = { "simple", "double",
1666 "long", "short" };
1667
1668enum AddrMode {
1669 ADDR_MODE_BEGIN = 0,
1670 ADDR_MODE_LBA28 = ADDR_MODE_BEGIN,
1671 ADDR_MODE_LBA48,
1672 NUM_ADDR_MODES
1673};
1674
1675static const char *addr_mode_str[NUM_ADDR_MODES] = { "lba28", "lba48" };
1676
1677enum IOMode {
1678 MODE_BEGIN = 0,
1679 MODE_PIO = MODE_BEGIN,
1680 MODE_DMA,
1681 NUM_MODES
1682};
1683
1684static const char *io_mode_str[NUM_MODES] = { "pio", "dma" };
1685
1686enum IOOps {
1687 IO_BEGIN = 0,
1688 IO_READ = IO_BEGIN,
1689 IO_WRITE,
1690 NUM_IO_OPS
1691};
1692
1693enum OffsetType {
1694 OFFSET_BEGIN = 0,
1695 OFFSET_ZERO = OFFSET_BEGIN,
1696 OFFSET_LOW,
1697 OFFSET_HIGH,
1698 NUM_OFFSETS
1699};
1700
1701static const char *offset_str[NUM_OFFSETS] = { "zero", "low", "high" };
1702
1703typedef struct AHCIIOTestOptions {
1704 enum BuffLen length;
1705 enum AddrMode address_type;
1706 enum IOMode io_type;
1707 enum OffsetType offset;
1708} AHCIIOTestOptions;
1709
1710static uint64_t offset_sector(enum OffsetType ofst,
1711 enum AddrMode addr_type,
1712 uint64_t buffsize)
1713{
1714 uint64_t ceil;
1715 uint64_t nsectors;
1716
1717 switch (ofst) {
1718 case OFFSET_ZERO:
1719 return 0;
1720 case OFFSET_LOW:
1721 return 1;
1722 case OFFSET_HIGH:
1723 ceil = (addr_type == ADDR_MODE_LBA28) ? 0xfffffff : 0xffffffffffff;
1724 ceil = MIN(ceil, mb_to_sectors(test_image_size_mb) - 1);
1725 nsectors = buffsize / AHCI_SECTOR_SIZE;
1726 return ceil - nsectors + 1;
1727 default:
1728 g_assert_not_reached();
1729 }
1730}
1731
1732
1733
1734
1735static const uint8_t io_cmds[NUM_MODES][NUM_ADDR_MODES][NUM_IO_OPS] = {
1736 [MODE_PIO] = {
1737 [ADDR_MODE_LBA28] = {
1738 [IO_READ] = CMD_READ_PIO,
1739 [IO_WRITE] = CMD_WRITE_PIO },
1740 [ADDR_MODE_LBA48] = {
1741 [IO_READ] = CMD_READ_PIO_EXT,
1742 [IO_WRITE] = CMD_WRITE_PIO_EXT }
1743 },
1744 [MODE_DMA] = {
1745 [ADDR_MODE_LBA28] = {
1746 [IO_READ] = CMD_READ_DMA,
1747 [IO_WRITE] = CMD_WRITE_DMA },
1748 [ADDR_MODE_LBA48] = {
1749 [IO_READ] = CMD_READ_DMA_EXT,
1750 [IO_WRITE] = CMD_WRITE_DMA_EXT }
1751 }
1752};
1753
1754
1755
1756
1757
1758static void test_io_rw_interface(enum AddrMode lba48, enum IOMode dma,
1759 unsigned bufsize, uint64_t sector)
1760{
1761 AHCIQState *ahci;
1762
1763 ahci = ahci_boot_and_enable(NULL);
1764 ahci_test_io_rw_simple(ahci, bufsize, sector,
1765 io_cmds[dma][lba48][IO_READ],
1766 io_cmds[dma][lba48][IO_WRITE]);
1767 ahci_shutdown(ahci);
1768}
1769
1770
1771
1772
1773static void test_io_interface(gconstpointer opaque)
1774{
1775 AHCIIOTestOptions *opts = (AHCIIOTestOptions *)opaque;
1776 unsigned bufsize;
1777 uint64_t sector;
1778
1779 switch (opts->length) {
1780 case LEN_SIMPLE:
1781 bufsize = 4096;
1782 break;
1783 case LEN_DOUBLE:
1784 bufsize = 8192;
1785 break;
1786 case LEN_LONG:
1787 bufsize = 4096 * 64;
1788 break;
1789 case LEN_SHORT:
1790 bufsize = 512;
1791 break;
1792 default:
1793 g_assert_not_reached();
1794 }
1795
1796 sector = offset_sector(opts->offset, opts->address_type, bufsize);
1797 test_io_rw_interface(opts->address_type, opts->io_type, bufsize, sector);
1798 g_free(opts);
1799 return;
1800}
1801
1802static void create_ahci_io_test(enum IOMode type, enum AddrMode addr,
1803 enum BuffLen len, enum OffsetType offset)
1804{
1805 char *name;
1806 AHCIIOTestOptions *opts;
1807
1808 opts = g_new(AHCIIOTestOptions, 1);
1809 opts->length = len;
1810 opts->address_type = addr;
1811 opts->io_type = type;
1812 opts->offset = offset;
1813
1814 name = g_strdup_printf("ahci/io/%s/%s/%s/%s",
1815 io_mode_str[type],
1816 addr_mode_str[addr],
1817 buff_len_str[len],
1818 offset_str[offset]);
1819
1820 if ((addr == ADDR_MODE_LBA48) && (offset == OFFSET_HIGH) &&
1821 (mb_to_sectors(test_image_size_mb) <= 0xFFFFFFF)) {
1822 g_test_message("%s: skipped; test image too small", name);
1823 g_free(opts);
1824 g_free(name);
1825 return;
1826 }
1827
1828 qtest_add_data_func(name, opts, test_io_interface);
1829 g_free(name);
1830}
1831
1832
1833
1834int main(int argc, char **argv)
1835{
1836 const char *arch, *base;
1837 int ret;
1838 int fd;
1839 int c;
1840 int i, j, k, m;
1841
1842 static struct option long_options[] = {
1843 {"pedantic", no_argument, 0, 'p' },
1844 {0, 0, 0, 0},
1845 };
1846
1847
1848 g_test_init(&argc, &argv, NULL);
1849
1850 while (1) {
1851 c = getopt_long(argc, argv, "", long_options, NULL);
1852 if (c == -1) {
1853 break;
1854 }
1855 switch (c) {
1856 case -1:
1857 break;
1858 case 'p':
1859 ahci_pedantic = 1;
1860 break;
1861 default:
1862 fprintf(stderr, "Unrecognized ahci_test option.\n");
1863 g_assert_not_reached();
1864 }
1865 }
1866
1867
1868 arch = qtest_get_arch();
1869 if (strcmp(arch, "i386") && strcmp(arch, "x86_64")) {
1870 g_test_message("Skipping test for non-x86");
1871 return 0;
1872 }
1873
1874
1875
1876
1877
1878
1879
1880
1881#ifndef _WIN32
1882 base = g_get_tmp_dir();
1883#else
1884 base = ".";
1885#endif
1886
1887
1888 tmp_path = g_strdup_printf("%s/qtest.XXXXXX", base);
1889 fd = g_mkstemp(tmp_path);
1890 g_assert(fd >= 0);
1891 if (have_qemu_img()) {
1892 imgfmt = "qcow2";
1893 test_image_size_mb = TEST_IMAGE_SIZE_MB_LARGE;
1894 mkqcow2(tmp_path, TEST_IMAGE_SIZE_MB_LARGE);
1895 } else {
1896 g_test_message("QTEST_QEMU_IMG not set or qemu-img missing; "
1897 "skipping LBA48 high-sector tests");
1898 imgfmt = "raw";
1899 test_image_size_mb = TEST_IMAGE_SIZE_MB_SMALL;
1900 ret = ftruncate(fd, test_image_size_mb * 1024 * 1024);
1901 g_assert(ret == 0);
1902 }
1903 close(fd);
1904
1905
1906 debug_path = g_strdup_printf("%s/qtest-blkdebug.XXXXXX", base);
1907 fd = g_mkstemp(debug_path);
1908 g_assert(fd >= 0);
1909 close(fd);
1910
1911
1912 fd = g_file_open_tmp("qtest-migration.XXXXXX", &mig_socket, NULL);
1913 g_assert(fd >= 0);
1914 close(fd);
1915
1916
1917 qtest_add_func("/ahci/sanity", test_sanity);
1918 qtest_add_func("/ahci/pci_spec", test_pci_spec);
1919 qtest_add_func("/ahci/pci_enable", test_pci_enable);
1920 qtest_add_func("/ahci/hba_spec", test_hba_spec);
1921 qtest_add_func("/ahci/hba_enable", test_hba_enable);
1922 qtest_add_func("/ahci/identify", test_identify);
1923
1924 for (i = MODE_BEGIN; i < NUM_MODES; i++) {
1925 for (j = ADDR_MODE_BEGIN; j < NUM_ADDR_MODES; j++) {
1926 for (k = LEN_BEGIN; k < NUM_LENGTHS; k++) {
1927 for (m = OFFSET_BEGIN; m < NUM_OFFSETS; m++) {
1928 create_ahci_io_test(i, j, k, m);
1929 }
1930 }
1931 }
1932 }
1933
1934 qtest_add_func("/ahci/io/dma/lba28/fragmented", test_dma_fragmented);
1935
1936 qtest_add_func("/ahci/flush/simple", test_flush);
1937 qtest_add_func("/ahci/flush/retry", test_flush_retry);
1938 qtest_add_func("/ahci/flush/migrate", test_flush_migrate);
1939
1940 qtest_add_func("/ahci/migrate/sanity", test_migrate_sanity);
1941 qtest_add_func("/ahci/migrate/dma/simple", test_migrate_dma);
1942 qtest_add_func("/ahci/io/dma/lba28/retry", test_halted_dma);
1943 qtest_add_func("/ahci/migrate/dma/halted", test_migrate_halted_dma);
1944
1945 qtest_add_func("/ahci/max", test_max);
1946 qtest_add_func("/ahci/reset", test_reset);
1947
1948 qtest_add_func("/ahci/io/ncq/simple", test_ncq_simple);
1949 qtest_add_func("/ahci/migrate/ncq/simple", test_migrate_ncq);
1950 qtest_add_func("/ahci/io/ncq/retry", test_halted_ncq);
1951 qtest_add_func("/ahci/migrate/ncq/halted", test_migrate_halted_ncq);
1952
1953 qtest_add_func("/ahci/cdrom/dma/single", test_cdrom_dma);
1954 qtest_add_func("/ahci/cdrom/dma/multi", test_cdrom_dma_multi);
1955 qtest_add_func("/ahci/cdrom/pio/single", test_cdrom_pio);
1956 qtest_add_func("/ahci/cdrom/pio/multi", test_cdrom_pio_multi);
1957
1958 qtest_add_func("/ahci/cdrom/pio/bcl", test_atapi_bcl);
1959 qtest_add_func("/ahci/cdrom/eject", test_atapi_tray);
1960
1961 ret = g_test_run();
1962
1963
1964 unlink(tmp_path);
1965 g_free(tmp_path);
1966 unlink(debug_path);
1967 g_free(debug_path);
1968 unlink(mig_socket);
1969 g_free(mig_socket);
1970
1971 return ret;
1972}
1973