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20#include "qemu/osdep.h"
21#include "hw/irq.h"
22#include "hw/qdev-properties.h"
23#include "hw/sysbus.h"
24#include "migration/vmstate.h"
25#include "net/net.h"
26#include "qapi/error.h"
27#include "qemu/module.h"
28#include "qemu/timer.h"
29#include <zlib.h>
30#include "qom/object.h"
31#include "trace.h"
32
33static const char *reg_names[] = {
34 "CR", "DCR", "RCR", "TCR", "IMR", "ISR", "UTDA", "CTDA",
35 "TPS", "TFC", "TSA0", "TSA1", "TFS", "URDA", "CRDA", "CRBA0",
36 "CRBA1", "RBWC0", "RBWC1", "EOBC", "URRA", "RSA", "REA", "RRP",
37 "RWP", "TRBA0", "TRBA1", "0x1b", "0x1c", "0x1d", "0x1e", "LLFA",
38 "TTDA", "CEP", "CAP2", "CAP1", "CAP0", "CE", "CDP", "CDC",
39 "SR", "WT0", "WT1", "RSC", "CRCT", "FAET", "MPT", "MDT",
40 "0x30", "0x31", "0x32", "0x33", "0x34", "0x35", "0x36", "0x37",
41 "0x38", "0x39", "0x3a", "0x3b", "0x3c", "0x3d", "0x3e", "DCR2" };
42
43#define SONIC_CR 0x00
44#define SONIC_DCR 0x01
45#define SONIC_RCR 0x02
46#define SONIC_TCR 0x03
47#define SONIC_IMR 0x04
48#define SONIC_ISR 0x05
49#define SONIC_UTDA 0x06
50#define SONIC_CTDA 0x07
51#define SONIC_TPS 0x08
52#define SONIC_TFC 0x09
53#define SONIC_TSA0 0x0a
54#define SONIC_TSA1 0x0b
55#define SONIC_TFS 0x0c
56#define SONIC_URDA 0x0d
57#define SONIC_CRDA 0x0e
58#define SONIC_CRBA0 0x0f
59#define SONIC_CRBA1 0x10
60#define SONIC_RBWC0 0x11
61#define SONIC_RBWC1 0x12
62#define SONIC_EOBC 0x13
63#define SONIC_URRA 0x14
64#define SONIC_RSA 0x15
65#define SONIC_REA 0x16
66#define SONIC_RRP 0x17
67#define SONIC_RWP 0x18
68#define SONIC_TRBA0 0x19
69#define SONIC_TRBA1 0x1a
70#define SONIC_LLFA 0x1f
71#define SONIC_TTDA 0x20
72#define SONIC_CEP 0x21
73#define SONIC_CAP2 0x22
74#define SONIC_CAP1 0x23
75#define SONIC_CAP0 0x24
76#define SONIC_CE 0x25
77#define SONIC_CDP 0x26
78#define SONIC_CDC 0x27
79#define SONIC_SR 0x28
80#define SONIC_WT0 0x29
81#define SONIC_WT1 0x2a
82#define SONIC_RSC 0x2b
83#define SONIC_CRCT 0x2c
84#define SONIC_FAET 0x2d
85#define SONIC_MPT 0x2e
86#define SONIC_MDT 0x2f
87#define SONIC_DCR2 0x3f
88#define SONIC_REG_COUNT 0x40
89
90#define SONIC_CR_HTX 0x0001
91#define SONIC_CR_TXP 0x0002
92#define SONIC_CR_RXDIS 0x0004
93#define SONIC_CR_RXEN 0x0008
94#define SONIC_CR_STP 0x0010
95#define SONIC_CR_ST 0x0020
96#define SONIC_CR_RST 0x0080
97#define SONIC_CR_RRRA 0x0100
98#define SONIC_CR_LCAM 0x0200
99#define SONIC_CR_MASK 0x03bf
100
101#define SONIC_DCR_DW 0x0020
102#define SONIC_DCR_LBR 0x2000
103#define SONIC_DCR_EXBUS 0x8000
104
105#define SONIC_RCR_PRX 0x0001
106#define SONIC_RCR_LBK 0x0002
107#define SONIC_RCR_FAER 0x0004
108#define SONIC_RCR_CRCR 0x0008
109#define SONIC_RCR_CRS 0x0020
110#define SONIC_RCR_LPKT 0x0040
111#define SONIC_RCR_BC 0x0080
112#define SONIC_RCR_MC 0x0100
113#define SONIC_RCR_LB0 0x0200
114#define SONIC_RCR_LB1 0x0400
115#define SONIC_RCR_AMC 0x0800
116#define SONIC_RCR_PRO 0x1000
117#define SONIC_RCR_BRD 0x2000
118#define SONIC_RCR_RNT 0x4000
119
120#define SONIC_TCR_PTX 0x0001
121#define SONIC_TCR_BCM 0x0002
122#define SONIC_TCR_FU 0x0004
123#define SONIC_TCR_EXC 0x0040
124#define SONIC_TCR_CRSL 0x0080
125#define SONIC_TCR_NCRS 0x0100
126#define SONIC_TCR_EXD 0x0400
127#define SONIC_TCR_CRCI 0x2000
128#define SONIC_TCR_PINT 0x8000
129
130#define SONIC_ISR_RBAE 0x0010
131#define SONIC_ISR_RBE 0x0020
132#define SONIC_ISR_RDE 0x0040
133#define SONIC_ISR_TC 0x0080
134#define SONIC_ISR_TXDN 0x0200
135#define SONIC_ISR_PKTRX 0x0400
136#define SONIC_ISR_PINT 0x0800
137#define SONIC_ISR_LCD 0x1000
138
139#define SONIC_DESC_EOL 0x0001
140#define SONIC_DESC_ADDR 0xFFFE
141
142#define TYPE_DP8393X "dp8393x"
143OBJECT_DECLARE_SIMPLE_TYPE(dp8393xState, DP8393X)
144
145struct dp8393xState {
146 SysBusDevice parent_obj;
147
148
149 uint8_t it_shift;
150 bool big_endian;
151 bool last_rba_is_full;
152 qemu_irq irq;
153 int irq_level;
154 QEMUTimer *watchdog;
155 int64_t wt_last_update;
156 NICConf conf;
157 NICState *nic;
158 MemoryRegion mmio;
159
160
161 uint16_t cam[16][3];
162 uint16_t regs[SONIC_REG_COUNT];
163
164
165 uint8_t tx_buffer[0x10000];
166 int loopback_packet;
167
168
169 MemoryRegion *dma_mr;
170 AddressSpace as;
171};
172
173
174
175
176
177
178
179
180static uint32_t dp8393x_cdp(dp8393xState *s)
181{
182 return (s->regs[SONIC_URRA] << 16) | s->regs[SONIC_CDP];
183}
184
185static uint32_t dp8393x_crba(dp8393xState *s)
186{
187 return (s->regs[SONIC_CRBA1] << 16) | s->regs[SONIC_CRBA0];
188}
189
190static uint32_t dp8393x_crda(dp8393xState *s)
191{
192 return (s->regs[SONIC_URDA] << 16) |
193 (s->regs[SONIC_CRDA] & SONIC_DESC_ADDR);
194}
195
196static uint32_t dp8393x_rbwc(dp8393xState *s)
197{
198 return (s->regs[SONIC_RBWC1] << 16) | s->regs[SONIC_RBWC0];
199}
200
201static uint32_t dp8393x_rrp(dp8393xState *s)
202{
203 return (s->regs[SONIC_URRA] << 16) | s->regs[SONIC_RRP];
204}
205
206static uint32_t dp8393x_tsa(dp8393xState *s)
207{
208 return (s->regs[SONIC_TSA1] << 16) | s->regs[SONIC_TSA0];
209}
210
211static uint32_t dp8393x_ttda(dp8393xState *s)
212{
213 return (s->regs[SONIC_UTDA] << 16) |
214 (s->regs[SONIC_TTDA] & SONIC_DESC_ADDR);
215}
216
217static uint32_t dp8393x_wt(dp8393xState *s)
218{
219 return s->regs[SONIC_WT1] << 16 | s->regs[SONIC_WT0];
220}
221
222static uint16_t dp8393x_get(dp8393xState *s, hwaddr addr, int offset)
223{
224 const MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED;
225 uint16_t val;
226
227 if (s->regs[SONIC_DCR] & SONIC_DCR_DW) {
228 addr += offset << 2;
229 if (s->big_endian) {
230 val = address_space_ldl_be(&s->as, addr, attrs, NULL);
231 } else {
232 val = address_space_ldl_le(&s->as, addr, attrs, NULL);
233 }
234 } else {
235 addr += offset << 1;
236 if (s->big_endian) {
237 val = address_space_lduw_be(&s->as, addr, attrs, NULL);
238 } else {
239 val = address_space_lduw_le(&s->as, addr, attrs, NULL);
240 }
241 }
242
243 return val;
244}
245
246static void dp8393x_put(dp8393xState *s,
247 hwaddr addr, int offset, uint16_t val)
248{
249 const MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED;
250
251 if (s->regs[SONIC_DCR] & SONIC_DCR_DW) {
252 addr += offset << 2;
253 if (s->big_endian) {
254 address_space_stl_be(&s->as, addr, val, attrs, NULL);
255 } else {
256 address_space_stl_le(&s->as, addr, val, attrs, NULL);
257 }
258 } else {
259 addr += offset << 1;
260 if (s->big_endian) {
261 address_space_stw_be(&s->as, addr, val, attrs, NULL);
262 } else {
263 address_space_stw_le(&s->as, addr, val, attrs, NULL);
264 }
265 }
266}
267
268static void dp8393x_update_irq(dp8393xState *s)
269{
270 int level = (s->regs[SONIC_IMR] & s->regs[SONIC_ISR]) ? 1 : 0;
271
272 if (level != s->irq_level) {
273 s->irq_level = level;
274 if (level) {
275 trace_dp8393x_raise_irq(s->regs[SONIC_ISR]);
276 } else {
277 trace_dp8393x_lower_irq();
278 }
279 }
280
281 qemu_set_irq(s->irq, level);
282}
283
284static void dp8393x_do_load_cam(dp8393xState *s)
285{
286 int width, size;
287 uint16_t index;
288
289 width = (s->regs[SONIC_DCR] & SONIC_DCR_DW) ? 2 : 1;
290 size = sizeof(uint16_t) * 4 * width;
291
292 while (s->regs[SONIC_CDC] & 0x1f) {
293
294 index = dp8393x_get(s, dp8393x_cdp(s), 0) & 0xf;
295 s->cam[index][0] = dp8393x_get(s, dp8393x_cdp(s), 1);
296 s->cam[index][1] = dp8393x_get(s, dp8393x_cdp(s), 2);
297 s->cam[index][2] = dp8393x_get(s, dp8393x_cdp(s), 3);
298 trace_dp8393x_load_cam(index,
299 s->cam[index][0] >> 8, s->cam[index][0] & 0xff,
300 s->cam[index][1] >> 8, s->cam[index][1] & 0xff,
301 s->cam[index][2] >> 8, s->cam[index][2] & 0xff);
302
303 s->regs[SONIC_CDC]--;
304 s->regs[SONIC_CDP] += size;
305 }
306
307
308 s->regs[SONIC_CE] = dp8393x_get(s, dp8393x_cdp(s), 0);
309 trace_dp8393x_load_cam_done(s->regs[SONIC_CE]);
310
311
312 s->regs[SONIC_CR] &= ~SONIC_CR_LCAM;
313 s->regs[SONIC_ISR] |= SONIC_ISR_LCD;
314 dp8393x_update_irq(s);
315}
316
317static void dp8393x_do_read_rra(dp8393xState *s)
318{
319 int width, size;
320
321
322 width = (s->regs[SONIC_DCR] & SONIC_DCR_DW) ? 2 : 1;
323 size = sizeof(uint16_t) * 4 * width;
324
325
326 s->regs[SONIC_CRBA0] = dp8393x_get(s, dp8393x_rrp(s), 0);
327 s->regs[SONIC_CRBA1] = dp8393x_get(s, dp8393x_rrp(s), 1);
328 s->regs[SONIC_RBWC0] = dp8393x_get(s, dp8393x_rrp(s), 2);
329 s->regs[SONIC_RBWC1] = dp8393x_get(s, dp8393x_rrp(s), 3);
330 trace_dp8393x_read_rra_regs(s->regs[SONIC_CRBA0], s->regs[SONIC_CRBA1],
331 s->regs[SONIC_RBWC0], s->regs[SONIC_RBWC1]);
332
333
334 s->regs[SONIC_RRP] += size;
335
336
337 if (s->regs[SONIC_RRP] == s->regs[SONIC_REA]) {
338 s->regs[SONIC_RRP] = s->regs[SONIC_RSA];
339 }
340
341
342 if (s->regs[SONIC_RRP] == s->regs[SONIC_RWP]) {
343 s->regs[SONIC_ISR] |= SONIC_ISR_RBE;
344 dp8393x_update_irq(s);
345 }
346
347
348 s->last_rba_is_full = false;
349}
350
351static void dp8393x_do_software_reset(dp8393xState *s)
352{
353 timer_del(s->watchdog);
354
355 s->regs[SONIC_CR] &= ~(SONIC_CR_LCAM | SONIC_CR_RRRA | SONIC_CR_TXP |
356 SONIC_CR_HTX);
357 s->regs[SONIC_CR] |= SONIC_CR_RST | SONIC_CR_RXDIS;
358}
359
360static void dp8393x_set_next_tick(dp8393xState *s)
361{
362 uint32_t ticks;
363 int64_t delay;
364
365 if (s->regs[SONIC_CR] & SONIC_CR_STP) {
366 timer_del(s->watchdog);
367 return;
368 }
369
370 ticks = dp8393x_wt(s);
371 s->wt_last_update = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
372 delay = NANOSECONDS_PER_SECOND * ticks / 5000000;
373 timer_mod(s->watchdog, s->wt_last_update + delay);
374}
375
376static void dp8393x_update_wt_regs(dp8393xState *s)
377{
378 int64_t elapsed;
379 uint32_t val;
380
381 if (s->regs[SONIC_CR] & SONIC_CR_STP) {
382 timer_del(s->watchdog);
383 return;
384 }
385
386 elapsed = s->wt_last_update - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
387 val = dp8393x_wt(s);
388 val -= elapsed / 5000000;
389 s->regs[SONIC_WT1] = (val >> 16) & 0xffff;
390 s->regs[SONIC_WT0] = (val >> 0) & 0xffff;
391 dp8393x_set_next_tick(s);
392
393}
394
395static void dp8393x_do_start_timer(dp8393xState *s)
396{
397 s->regs[SONIC_CR] &= ~SONIC_CR_STP;
398 dp8393x_set_next_tick(s);
399}
400
401static void dp8393x_do_stop_timer(dp8393xState *s)
402{
403 s->regs[SONIC_CR] &= ~SONIC_CR_ST;
404 dp8393x_update_wt_regs(s);
405}
406
407static bool dp8393x_can_receive(NetClientState *nc);
408
409static void dp8393x_do_receiver_enable(dp8393xState *s)
410{
411 s->regs[SONIC_CR] &= ~SONIC_CR_RXDIS;
412 if (dp8393x_can_receive(s->nic->ncs)) {
413 qemu_flush_queued_packets(qemu_get_queue(s->nic));
414 }
415}
416
417static void dp8393x_do_receiver_disable(dp8393xState *s)
418{
419 s->regs[SONIC_CR] &= ~SONIC_CR_RXEN;
420}
421
422static void dp8393x_do_transmit_packets(dp8393xState *s)
423{
424 NetClientState *nc = qemu_get_queue(s->nic);
425 int tx_len, len;
426 uint16_t i;
427
428 while (1) {
429
430 s->regs[SONIC_TTDA] = s->regs[SONIC_CTDA];
431 trace_dp8393x_transmit_packet(dp8393x_ttda(s));
432 tx_len = 0;
433
434
435 s->regs[SONIC_TCR] = dp8393x_get(s, dp8393x_ttda(s), 1) & 0xf000;
436 s->regs[SONIC_TPS] = dp8393x_get(s, dp8393x_ttda(s), 2);
437 s->regs[SONIC_TFC] = dp8393x_get(s, dp8393x_ttda(s), 3);
438 s->regs[SONIC_TSA0] = dp8393x_get(s, dp8393x_ttda(s), 4);
439 s->regs[SONIC_TSA1] = dp8393x_get(s, dp8393x_ttda(s), 5);
440 s->regs[SONIC_TFS] = dp8393x_get(s, dp8393x_ttda(s), 6);
441
442
443 if (s->regs[SONIC_TCR] & SONIC_TCR_PINT) {
444 s->regs[SONIC_ISR] |= SONIC_ISR_PINT;
445 } else {
446 s->regs[SONIC_ISR] &= ~SONIC_ISR_PINT;
447 }
448
449 for (i = 0; i < s->regs[SONIC_TFC]; ) {
450
451 len = s->regs[SONIC_TFS];
452 if (tx_len + len > sizeof(s->tx_buffer)) {
453 len = sizeof(s->tx_buffer) - tx_len;
454 }
455 address_space_read(&s->as, dp8393x_tsa(s), MEMTXATTRS_UNSPECIFIED,
456 &s->tx_buffer[tx_len], len);
457 tx_len += len;
458
459 i++;
460 if (i != s->regs[SONIC_TFC]) {
461
462 s->regs[SONIC_TSA0] = dp8393x_get(s, dp8393x_ttda(s),
463 4 + 3 * i);
464 s->regs[SONIC_TSA1] = dp8393x_get(s, dp8393x_ttda(s),
465 5 + 3 * i);
466 s->regs[SONIC_TFS] = dp8393x_get(s, dp8393x_ttda(s),
467 6 + 3 * i);
468 }
469 }
470
471
472 if (!(s->regs[SONIC_TCR] & SONIC_TCR_CRCI)) {
473
474
475
476
477 } else {
478
479 tx_len -= 4;
480 if (tx_len < 0) {
481 trace_dp8393x_transmit_txlen_error(tx_len);
482 break;
483 }
484 }
485
486 if (s->regs[SONIC_RCR] & (SONIC_RCR_LB1 | SONIC_RCR_LB0)) {
487
488 s->regs[SONIC_TCR] |= SONIC_TCR_CRSL;
489 if (nc->info->can_receive(nc)) {
490 s->loopback_packet = 1;
491 qemu_receive_packet(nc, s->tx_buffer, tx_len);
492 }
493 } else {
494
495 qemu_send_packet(nc, s->tx_buffer, tx_len);
496 }
497 s->regs[SONIC_TCR] |= SONIC_TCR_PTX;
498
499
500 dp8393x_put(s, dp8393x_ttda(s), 0, s->regs[SONIC_TCR] & 0x0fff);
501
502 if (!(s->regs[SONIC_CR] & SONIC_CR_HTX)) {
503
504 s->regs[SONIC_CTDA] = dp8393x_get(s, dp8393x_ttda(s),
505 4 + 3 * s->regs[SONIC_TFC]);
506 if (s->regs[SONIC_CTDA] & SONIC_DESC_EOL) {
507
508 break;
509 }
510 }
511 }
512
513
514 s->regs[SONIC_CR] &= ~SONIC_CR_TXP;
515 s->regs[SONIC_ISR] |= SONIC_ISR_TXDN;
516 dp8393x_update_irq(s);
517}
518
519static void dp8393x_do_halt_transmission(dp8393xState *s)
520{
521
522}
523
524static void dp8393x_do_command(dp8393xState *s, uint16_t command)
525{
526 if ((s->regs[SONIC_CR] & SONIC_CR_RST) && !(command & SONIC_CR_RST)) {
527 s->regs[SONIC_CR] &= ~SONIC_CR_RST;
528 return;
529 }
530
531 s->regs[SONIC_CR] |= (command & SONIC_CR_MASK);
532
533 if (command & SONIC_CR_HTX) {
534 dp8393x_do_halt_transmission(s);
535 }
536 if (command & SONIC_CR_TXP) {
537 dp8393x_do_transmit_packets(s);
538 }
539 if (command & SONIC_CR_RXDIS) {
540 dp8393x_do_receiver_disable(s);
541 }
542 if (command & SONIC_CR_RXEN) {
543 dp8393x_do_receiver_enable(s);
544 }
545 if (command & SONIC_CR_STP) {
546 dp8393x_do_stop_timer(s);
547 }
548 if (command & SONIC_CR_ST) {
549 dp8393x_do_start_timer(s);
550 }
551 if (command & SONIC_CR_RST) {
552 dp8393x_do_software_reset(s);
553 }
554 if (command & SONIC_CR_RRRA) {
555 dp8393x_do_read_rra(s);
556 s->regs[SONIC_CR] &= ~SONIC_CR_RRRA;
557 }
558 if (command & SONIC_CR_LCAM) {
559 dp8393x_do_load_cam(s);
560 }
561}
562
563static uint64_t dp8393x_read(void *opaque, hwaddr addr, unsigned int size)
564{
565 dp8393xState *s = opaque;
566 int reg = addr >> s->it_shift;
567 uint16_t val = 0;
568
569 switch (reg) {
570
571 case SONIC_WT0:
572 case SONIC_WT1:
573 dp8393x_update_wt_regs(s);
574 val = s->regs[reg];
575 break;
576
577 case SONIC_CAP2:
578 case SONIC_CAP1:
579 case SONIC_CAP0:
580 if (s->regs[SONIC_CR] & SONIC_CR_RST) {
581 val = s->cam[s->regs[SONIC_CEP] & 0xf][SONIC_CAP0 - reg];
582 }
583 break;
584
585 default:
586 val = s->regs[reg];
587 }
588
589 trace_dp8393x_read(reg, reg_names[reg], val, size);
590
591 return val;
592}
593
594static void dp8393x_write(void *opaque, hwaddr addr, uint64_t val,
595 unsigned int size)
596{
597 dp8393xState *s = opaque;
598 int reg = addr >> s->it_shift;
599
600 trace_dp8393x_write(reg, reg_names[reg], val, size);
601
602 switch (reg) {
603
604 case SONIC_CR:
605 dp8393x_do_command(s, val);
606 break;
607
608 case SONIC_CAP2:
609 case SONIC_CAP1:
610 case SONIC_CAP0:
611 case SONIC_SR:
612 case SONIC_MDT:
613 trace_dp8393x_write_invalid(reg);
614 break;
615
616 case SONIC_DCR:
617 if (s->regs[SONIC_CR] & SONIC_CR_RST) {
618 s->regs[reg] = val & 0xbfff;
619 } else {
620 trace_dp8393x_write_invalid_dcr("DCR");
621 }
622 break;
623 case SONIC_DCR2:
624 if (s->regs[SONIC_CR] & SONIC_CR_RST) {
625 s->regs[reg] = val & 0xf017;
626 } else {
627 trace_dp8393x_write_invalid_dcr("DCR2");
628 }
629 break;
630
631 case SONIC_TCR:
632 s->regs[reg] = val & 0xf000;
633 break;
634
635 case SONIC_RCR:
636 s->regs[reg] = val & 0xffe0;
637 break;
638
639 case SONIC_IMR:
640 s->regs[reg] = val & 0x7fff;
641 dp8393x_update_irq(s);
642 break;
643
644 case SONIC_ISR:
645 val &= s->regs[reg];
646 s->regs[reg] &= ~val;
647 if (val & SONIC_ISR_RBE) {
648 dp8393x_do_read_rra(s);
649 }
650 dp8393x_update_irq(s);
651 break;
652
653 case SONIC_RSA:
654 case SONIC_REA:
655 case SONIC_RRP:
656 case SONIC_RWP:
657 if (s->regs[SONIC_DCR] & SONIC_DCR_DW) {
658 s->regs[reg] = val & 0xfffc;
659 } else {
660 s->regs[reg] = val & 0xfffe;
661 }
662 break;
663
664 case SONIC_CRCT:
665 case SONIC_FAET:
666 case SONIC_MPT:
667 s->regs[reg] = val ^ 0xffff;
668 break;
669
670 default:
671 s->regs[reg] = val;
672 }
673
674 if (reg == SONIC_WT0 || reg == SONIC_WT1) {
675 dp8393x_set_next_tick(s);
676 }
677}
678
679
680
681
682
683
684
685static const MemoryRegionOps dp8393x_ops = {
686 .read = dp8393x_read,
687 .write = dp8393x_write,
688 .impl.min_access_size = 2,
689 .endianness = DEVICE_NATIVE_ENDIAN,
690};
691
692static void dp8393x_watchdog(void *opaque)
693{
694 dp8393xState *s = opaque;
695
696 if (s->regs[SONIC_CR] & SONIC_CR_STP) {
697 return;
698 }
699
700 s->regs[SONIC_WT1] = 0xffff;
701 s->regs[SONIC_WT0] = 0xffff;
702 dp8393x_set_next_tick(s);
703
704
705 s->regs[SONIC_ISR] |= SONIC_ISR_TC;
706 dp8393x_update_irq(s);
707}
708
709static bool dp8393x_can_receive(NetClientState *nc)
710{
711 dp8393xState *s = qemu_get_nic_opaque(nc);
712
713 return !!(s->regs[SONIC_CR] & SONIC_CR_RXEN);
714}
715
716static int dp8393x_receive_filter(dp8393xState *s, const uint8_t * buf,
717 int size)
718{
719 static const uint8_t bcast[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
720 int i;
721
722
723 if ((s->regs[SONIC_RCR] & SONIC_RCR_PRO) && (buf[0] & 1) == 0) {
724 return 0;
725 }
726
727
728 if ((s->regs[SONIC_RCR] & SONIC_RCR_AMC) && (buf[0] & 1) == 1) {
729 return SONIC_RCR_MC;
730 }
731
732
733 if ((s->regs[SONIC_RCR] & SONIC_RCR_BRD) &&
734 !memcmp(buf, bcast, sizeof(bcast))) {
735 return SONIC_RCR_BC;
736 }
737
738
739 for (i = 0; i < 16; i++) {
740 if (s->regs[SONIC_CE] & (1 << i)) {
741
742 if (!memcmp(buf, s->cam[i], sizeof(s->cam[i]))) {
743 return 0;
744 }
745 }
746 }
747
748 return -1;
749}
750
751static ssize_t dp8393x_receive(NetClientState *nc, const uint8_t * buf,
752 size_t pkt_size)
753{
754 dp8393xState *s = qemu_get_nic_opaque(nc);
755 int packet_type;
756 uint32_t available, address;
757 int rx_len, padded_len;
758 uint32_t checksum;
759 int size;
760
761 s->regs[SONIC_RCR] &= ~(SONIC_RCR_PRX | SONIC_RCR_LBK | SONIC_RCR_FAER |
762 SONIC_RCR_CRCR | SONIC_RCR_LPKT | SONIC_RCR_BC | SONIC_RCR_MC);
763
764 if (s->last_rba_is_full) {
765 return pkt_size;
766 }
767
768 rx_len = pkt_size + sizeof(checksum);
769 if (s->regs[SONIC_DCR] & SONIC_DCR_DW) {
770 padded_len = ((rx_len - 1) | 3) + 1;
771 } else {
772 padded_len = ((rx_len - 1) | 1) + 1;
773 }
774
775 if (padded_len > dp8393x_rbwc(s) * 2) {
776 trace_dp8393x_receive_oversize(pkt_size);
777 s->regs[SONIC_ISR] |= SONIC_ISR_RBAE;
778 dp8393x_update_irq(s);
779 s->regs[SONIC_RCR] |= SONIC_RCR_LPKT;
780 goto done;
781 }
782
783 packet_type = dp8393x_receive_filter(s, buf, pkt_size);
784 if (packet_type < 0) {
785 trace_dp8393x_receive_not_netcard();
786 return -1;
787 }
788
789
790 if (s->regs[SONIC_LLFA] & SONIC_DESC_EOL) {
791
792 s->regs[SONIC_LLFA] = dp8393x_get(s, dp8393x_crda(s), 5);
793 if (s->regs[SONIC_LLFA] & SONIC_DESC_EOL) {
794
795 return -1;
796 }
797
798
799
800 dp8393x_put(s, dp8393x_crda(s), 6, 0x0000);
801
802
803 s->regs[SONIC_CRDA] = s->regs[SONIC_LLFA];
804 s->regs[SONIC_ISR] |= SONIC_ISR_PKTRX;
805 }
806
807
808 s->regs[SONIC_TRBA1] = s->regs[SONIC_CRBA1];
809 s->regs[SONIC_TRBA0] = s->regs[SONIC_CRBA0];
810
811
812 checksum = cpu_to_le32(crc32(0, buf, pkt_size));
813
814
815 trace_dp8393x_receive_packet(dp8393x_crba(s));
816 address = dp8393x_crba(s);
817 address_space_write(&s->as, address, MEMTXATTRS_UNSPECIFIED,
818 buf, pkt_size);
819 address += pkt_size;
820
821
822 address_space_write(&s->as, address, MEMTXATTRS_UNSPECIFIED,
823 &checksum, sizeof(checksum));
824 address += sizeof(checksum);
825
826
827 if (rx_len < padded_len) {
828 size = padded_len - rx_len;
829 address_space_write(&s->as, address, MEMTXATTRS_UNSPECIFIED,
830 "\xFF\xFF\xFF", size);
831 address += size;
832 }
833
834 s->regs[SONIC_CRBA1] = address >> 16;
835 s->regs[SONIC_CRBA0] = address & 0xffff;
836 available = dp8393x_rbwc(s);
837 available -= padded_len >> 1;
838 s->regs[SONIC_RBWC1] = available >> 16;
839 s->regs[SONIC_RBWC0] = available & 0xffff;
840
841
842 if (dp8393x_rbwc(s) < s->regs[SONIC_EOBC]) {
843 s->regs[SONIC_RCR] |= SONIC_RCR_LPKT;
844 }
845 s->regs[SONIC_RCR] |= packet_type;
846 s->regs[SONIC_RCR] |= SONIC_RCR_PRX;
847 if (s->loopback_packet) {
848 s->regs[SONIC_RCR] |= SONIC_RCR_LBK;
849 s->loopback_packet = 0;
850 }
851
852
853 trace_dp8393x_receive_write_status(dp8393x_crda(s));
854 dp8393x_put(s, dp8393x_crda(s), 0, s->regs[SONIC_RCR]);
855 dp8393x_put(s, dp8393x_crda(s), 1, rx_len);
856 dp8393x_put(s, dp8393x_crda(s), 2, s->regs[SONIC_TRBA0]);
857 dp8393x_put(s, dp8393x_crda(s), 3, s->regs[SONIC_TRBA1]);
858 dp8393x_put(s, dp8393x_crda(s), 4, s->regs[SONIC_RSC]);
859
860
861 s->regs[SONIC_LLFA] = dp8393x_get(s, dp8393x_crda(s), 5);
862 if (s->regs[SONIC_LLFA] & SONIC_DESC_EOL) {
863
864 s->regs[SONIC_ISR] |= SONIC_ISR_RDE;
865 } else {
866
867 dp8393x_put(s, dp8393x_crda(s), 6, 0x0000);
868
869
870 s->regs[SONIC_CRDA] = s->regs[SONIC_LLFA];
871 s->regs[SONIC_ISR] |= SONIC_ISR_PKTRX;
872 }
873
874 dp8393x_update_irq(s);
875
876 s->regs[SONIC_RSC] = (s->regs[SONIC_RSC] & 0xff00) |
877 ((s->regs[SONIC_RSC] + 1) & 0x00ff);
878
879done:
880
881 if (s->regs[SONIC_RCR] & SONIC_RCR_LPKT) {
882 if (s->regs[SONIC_RRP] == s->regs[SONIC_RWP]) {
883
884 s->last_rba_is_full = true;
885 } else {
886
887 dp8393x_do_read_rra(s);
888 }
889 }
890
891 return pkt_size;
892}
893
894static void dp8393x_reset(DeviceState *dev)
895{
896 dp8393xState *s = DP8393X(dev);
897 timer_del(s->watchdog);
898
899 memset(s->regs, 0, sizeof(s->regs));
900 s->regs[SONIC_SR] = 0x0004;
901 s->regs[SONIC_CR] = SONIC_CR_RST | SONIC_CR_STP | SONIC_CR_RXDIS;
902 s->regs[SONIC_DCR] &= ~(SONIC_DCR_EXBUS | SONIC_DCR_LBR);
903 s->regs[SONIC_RCR] &= ~(SONIC_RCR_LB0 | SONIC_RCR_LB1 | SONIC_RCR_BRD |
904 SONIC_RCR_RNT);
905 s->regs[SONIC_TCR] |= SONIC_TCR_NCRS | SONIC_TCR_PTX;
906 s->regs[SONIC_TCR] &= ~SONIC_TCR_BCM;
907 s->regs[SONIC_IMR] = 0;
908 s->regs[SONIC_ISR] = 0;
909 s->regs[SONIC_DCR2] = 0;
910 s->regs[SONIC_EOBC] = 0x02F8;
911 s->regs[SONIC_RSC] = 0;
912 s->regs[SONIC_CE] = 0;
913 s->regs[SONIC_RSC] = 0;
914
915
916 s->regs[SONIC_RCR] |= SONIC_RCR_CRS;
917
918 dp8393x_update_irq(s);
919}
920
921static NetClientInfo net_dp83932_info = {
922 .type = NET_CLIENT_DRIVER_NIC,
923 .size = sizeof(NICState),
924 .can_receive = dp8393x_can_receive,
925 .receive = dp8393x_receive,
926};
927
928static void dp8393x_instance_init(Object *obj)
929{
930 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
931 dp8393xState *s = DP8393X(obj);
932
933 sysbus_init_mmio(sbd, &s->mmio);
934 sysbus_init_irq(sbd, &s->irq);
935}
936
937static void dp8393x_realize(DeviceState *dev, Error **errp)
938{
939 dp8393xState *s = DP8393X(dev);
940
941 address_space_init(&s->as, s->dma_mr, "dp8393x");
942 memory_region_init_io(&s->mmio, OBJECT(dev), &dp8393x_ops, s,
943 "dp8393x-regs", SONIC_REG_COUNT << s->it_shift);
944
945 s->nic = qemu_new_nic(&net_dp83932_info, &s->conf,
946 object_get_typename(OBJECT(dev)), dev->id, s);
947 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
948
949 s->watchdog = timer_new_ns(QEMU_CLOCK_VIRTUAL, dp8393x_watchdog, s);
950}
951
952static const VMStateDescription vmstate_dp8393x = {
953 .name = "dp8393x",
954 .version_id = 1,
955 .minimum_version_id = 1,
956 .fields = (VMStateField []) {
957 VMSTATE_UINT16_2DARRAY(cam, dp8393xState, 16, 3),
958 VMSTATE_UINT16_ARRAY(regs, dp8393xState, SONIC_REG_COUNT),
959 VMSTATE_END_OF_LIST()
960 }
961};
962
963static Property dp8393x_properties[] = {
964 DEFINE_NIC_PROPERTIES(dp8393xState, conf),
965 DEFINE_PROP_LINK("dma_mr", dp8393xState, dma_mr,
966 TYPE_MEMORY_REGION, MemoryRegion *),
967 DEFINE_PROP_UINT8("it_shift", dp8393xState, it_shift, 0),
968 DEFINE_PROP_BOOL("big_endian", dp8393xState, big_endian, false),
969 DEFINE_PROP_END_OF_LIST(),
970};
971
972static void dp8393x_class_init(ObjectClass *klass, void *data)
973{
974 DeviceClass *dc = DEVICE_CLASS(klass);
975
976 set_bit(DEVICE_CATEGORY_NETWORK, dc->categories);
977 dc->realize = dp8393x_realize;
978 dc->reset = dp8393x_reset;
979 dc->vmsd = &vmstate_dp8393x;
980 device_class_set_props(dc, dp8393x_properties);
981}
982
983static const TypeInfo dp8393x_info = {
984 .name = TYPE_DP8393X,
985 .parent = TYPE_SYS_BUS_DEVICE,
986 .instance_size = sizeof(dp8393xState),
987 .instance_init = dp8393x_instance_init,
988 .class_init = dp8393x_class_init,
989};
990
991static void dp8393x_register_types(void)
992{
993 type_register_static(&dp8393x_info);
994}
995
996type_init(dp8393x_register_types)
997
