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17#include "qemu/osdep.h"
18#include "qemu/datadir.h"
19#include "qemu/units.h"
20#include "qemu/guest-random.h"
21#include "qapi/error.h"
22#include "e500.h"
23#include "e500-ccsr.h"
24#include "net/net.h"
25#include "qemu/config-file.h"
26#include "hw/block/flash.h"
27#include "hw/char/serial.h"
28#include "hw/pci/pci.h"
29#include "sysemu/block-backend-io.h"
30#include "sysemu/sysemu.h"
31#include "sysemu/kvm.h"
32#include "sysemu/reset.h"
33#include "sysemu/runstate.h"
34#include "kvm_ppc.h"
35#include "sysemu/device_tree.h"
36#include "hw/ppc/openpic.h"
37#include "hw/ppc/openpic_kvm.h"
38#include "hw/ppc/ppc.h"
39#include "hw/qdev-properties.h"
40#include "hw/loader.h"
41#include "elf.h"
42#include "hw/sysbus.h"
43#include "qemu/host-utils.h"
44#include "qemu/option.h"
45#include "hw/pci-host/ppce500.h"
46#include "qemu/error-report.h"
47#include "hw/platform-bus.h"
48#include "hw/net/fsl_etsec/etsec.h"
49#include "hw/i2c/i2c.h"
50#include "hw/irq.h"
51
52#define EPAPR_MAGIC (0x45504150)
53#define DTC_LOAD_PAD 0x1800000
54#define DTC_PAD_MASK 0xFFFFF
55#define DTB_MAX_SIZE (8 * MiB)
56#define INITRD_LOAD_PAD 0x2000000
57#define INITRD_PAD_MASK 0xFFFFFF
58
59#define RAM_SIZES_ALIGN (64 * MiB)
60
61
62#define MPC8544_CCSRBAR_SIZE 0x00100000ULL
63#define MPC8544_MPIC_REGS_OFFSET 0x40000ULL
64#define MPC8544_MSI_REGS_OFFSET 0x41600ULL
65#define MPC8544_SERIAL0_REGS_OFFSET 0x4500ULL
66#define MPC8544_SERIAL1_REGS_OFFSET 0x4600ULL
67#define MPC8544_PCI_REGS_OFFSET 0x8000ULL
68#define MPC8544_PCI_REGS_SIZE 0x1000ULL
69#define MPC8544_UTIL_OFFSET 0xe0000ULL
70#define MPC8XXX_GPIO_OFFSET 0x000FF000ULL
71#define MPC8544_I2C_REGS_OFFSET 0x3000ULL
72#define MPC8XXX_GPIO_IRQ 47
73#define MPC8544_I2C_IRQ 43
74#define RTC_REGS_OFFSET 0x68
75
76#define PLATFORM_CLK_FREQ_HZ (400 * 1000 * 1000)
77
78struct boot_info
79{
80 uint32_t dt_base;
81 uint32_t dt_size;
82 uint32_t entry;
83};
84
85static uint32_t *pci_map_create(void *fdt, uint32_t mpic, int first_slot,
86 int nr_slots, int *len)
87{
88 int i = 0;
89 int slot;
90 int pci_irq;
91 int host_irq;
92 int last_slot = first_slot + nr_slots;
93 uint32_t *pci_map;
94
95 *len = nr_slots * 4 * 7 * sizeof(uint32_t);
96 pci_map = g_malloc(*len);
97
98 for (slot = first_slot; slot < last_slot; slot++) {
99 for (pci_irq = 0; pci_irq < 4; pci_irq++) {
100 pci_map[i++] = cpu_to_be32(slot << 11);
101 pci_map[i++] = cpu_to_be32(0x0);
102 pci_map[i++] = cpu_to_be32(0x0);
103 pci_map[i++] = cpu_to_be32(pci_irq + 1);
104 pci_map[i++] = cpu_to_be32(mpic);
105 host_irq = ppce500_pci_map_irq_slot(slot, pci_irq);
106 pci_map[i++] = cpu_to_be32(host_irq + 1);
107 pci_map[i++] = cpu_to_be32(0x1);
108 }
109 }
110
111 assert((i * sizeof(uint32_t)) == *len);
112
113 return pci_map;
114}
115
116static void dt_serial_create(void *fdt, unsigned long long offset,
117 const char *soc, const char *mpic,
118 const char *alias, int idx, bool defcon)
119{
120 char *ser;
121
122 ser = g_strdup_printf("%s/serial@%llx", soc, offset);
123 qemu_fdt_add_subnode(fdt, ser);
124 qemu_fdt_setprop_string(fdt, ser, "device_type", "serial");
125 qemu_fdt_setprop_string(fdt, ser, "compatible", "ns16550");
126 qemu_fdt_setprop_cells(fdt, ser, "reg", offset, 0x100);
127 qemu_fdt_setprop_cell(fdt, ser, "cell-index", idx);
128 qemu_fdt_setprop_cell(fdt, ser, "clock-frequency", PLATFORM_CLK_FREQ_HZ);
129 qemu_fdt_setprop_cells(fdt, ser, "interrupts", 42, 2);
130 qemu_fdt_setprop_phandle(fdt, ser, "interrupt-parent", mpic);
131 qemu_fdt_setprop_string(fdt, "/aliases", alias, ser);
132
133 if (defcon) {
134
135
136
137
138
139
140 qemu_fdt_setprop_string(fdt, "/chosen", "linux,stdout-path", ser);
141 qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", ser);
142 }
143 g_free(ser);
144}
145
146static void create_dt_mpc8xxx_gpio(void *fdt, const char *soc, const char *mpic)
147{
148 hwaddr mmio0 = MPC8XXX_GPIO_OFFSET;
149 int irq0 = MPC8XXX_GPIO_IRQ;
150 gchar *node = g_strdup_printf("%s/gpio@%"PRIx64, soc, mmio0);
151 gchar *poweroff = g_strdup_printf("%s/power-off", soc);
152 int gpio_ph;
153
154 qemu_fdt_add_subnode(fdt, node);
155 qemu_fdt_setprop_string(fdt, node, "compatible", "fsl,qoriq-gpio");
156 qemu_fdt_setprop_cells(fdt, node, "reg", mmio0, 0x1000);
157 qemu_fdt_setprop_cells(fdt, node, "interrupts", irq0, 0x2);
158 qemu_fdt_setprop_phandle(fdt, node, "interrupt-parent", mpic);
159 qemu_fdt_setprop_cells(fdt, node, "#gpio-cells", 2);
160 qemu_fdt_setprop(fdt, node, "gpio-controller", NULL, 0);
161 gpio_ph = qemu_fdt_alloc_phandle(fdt);
162 qemu_fdt_setprop_cell(fdt, node, "phandle", gpio_ph);
163 qemu_fdt_setprop_cell(fdt, node, "linux,phandle", gpio_ph);
164
165
166 qemu_fdt_add_subnode(fdt, poweroff);
167 qemu_fdt_setprop_string(fdt, poweroff, "compatible", "gpio-poweroff");
168 qemu_fdt_setprop_cells(fdt, poweroff, "gpios", gpio_ph, 0, 0);
169
170 g_free(node);
171 g_free(poweroff);
172}
173
174static void dt_rtc_create(void *fdt, const char *i2c, const char *alias)
175{
176 int offset = RTC_REGS_OFFSET;
177
178 gchar *rtc = g_strdup_printf("%s/rtc@%"PRIx32, i2c, offset);
179 qemu_fdt_add_subnode(fdt, rtc);
180 qemu_fdt_setprop_string(fdt, rtc, "compatible", "pericom,pt7c4338");
181 qemu_fdt_setprop_cells(fdt, rtc, "reg", offset);
182 qemu_fdt_setprop_string(fdt, "/aliases", alias, rtc);
183
184 g_free(rtc);
185}
186
187static void dt_i2c_create(void *fdt, const char *soc, const char *mpic,
188 const char *alias)
189{
190 hwaddr mmio0 = MPC8544_I2C_REGS_OFFSET;
191 int irq0 = MPC8544_I2C_IRQ;
192
193 gchar *i2c = g_strdup_printf("%s/i2c@%"PRIx64, soc, mmio0);
194 qemu_fdt_add_subnode(fdt, i2c);
195 qemu_fdt_setprop_string(fdt, i2c, "device_type", "i2c");
196 qemu_fdt_setprop_string(fdt, i2c, "compatible", "fsl-i2c");
197 qemu_fdt_setprop_cells(fdt, i2c, "reg", mmio0, 0x14);
198 qemu_fdt_setprop_cells(fdt, i2c, "cell-index", 0);
199 qemu_fdt_setprop_cells(fdt, i2c, "interrupts", irq0, 0x2);
200 qemu_fdt_setprop_phandle(fdt, i2c, "interrupt-parent", mpic);
201 qemu_fdt_setprop_string(fdt, "/aliases", alias, i2c);
202
203 g_free(i2c);
204}
205
206
207typedef struct PlatformDevtreeData {
208 void *fdt;
209 const char *mpic;
210 int irq_start;
211 const char *node;
212 PlatformBusDevice *pbus;
213} PlatformDevtreeData;
214
215static int create_devtree_etsec(SysBusDevice *sbdev, PlatformDevtreeData *data)
216{
217 eTSEC *etsec = ETSEC_COMMON(sbdev);
218 PlatformBusDevice *pbus = data->pbus;
219 hwaddr mmio0 = platform_bus_get_mmio_addr(pbus, sbdev, 0);
220 int irq0 = platform_bus_get_irqn(pbus, sbdev, 0);
221 int irq1 = platform_bus_get_irqn(pbus, sbdev, 1);
222 int irq2 = platform_bus_get_irqn(pbus, sbdev, 2);
223 gchar *node = g_strdup_printf("/platform/ethernet@%"PRIx64, mmio0);
224 gchar *group = g_strdup_printf("%s/queue-group", node);
225 void *fdt = data->fdt;
226
227 assert((int64_t)mmio0 >= 0);
228 assert(irq0 >= 0);
229 assert(irq1 >= 0);
230 assert(irq2 >= 0);
231
232 qemu_fdt_add_subnode(fdt, node);
233 qemu_fdt_setprop(fdt, node, "ranges", NULL, 0);
234 qemu_fdt_setprop_string(fdt, node, "device_type", "network");
235 qemu_fdt_setprop_string(fdt, node, "compatible", "fsl,etsec2");
236 qemu_fdt_setprop_string(fdt, node, "model", "eTSEC");
237 qemu_fdt_setprop(fdt, node, "local-mac-address", etsec->conf.macaddr.a, 6);
238 qemu_fdt_setprop_cells(fdt, node, "fixed-link", 0, 1, 1000, 0, 0);
239 qemu_fdt_setprop_cells(fdt, node, "#size-cells", 1);
240 qemu_fdt_setprop_cells(fdt, node, "#address-cells", 1);
241
242 qemu_fdt_add_subnode(fdt, group);
243 qemu_fdt_setprop_cells(fdt, group, "reg", mmio0, 0x1000);
244 qemu_fdt_setprop_cells(fdt, group, "interrupts",
245 data->irq_start + irq0, 0x2,
246 data->irq_start + irq1, 0x2,
247 data->irq_start + irq2, 0x2);
248
249 g_free(node);
250 g_free(group);
251
252 return 0;
253}
254
255static void sysbus_device_create_devtree(SysBusDevice *sbdev, void *opaque)
256{
257 PlatformDevtreeData *data = opaque;
258 bool matched = false;
259
260 if (object_dynamic_cast(OBJECT(sbdev), TYPE_ETSEC_COMMON)) {
261 create_devtree_etsec(sbdev, data);
262 matched = true;
263 }
264
265 if (!matched) {
266 error_report("Device %s is not supported by this machine yet.",
267 qdev_fw_name(DEVICE(sbdev)));
268 exit(1);
269 }
270}
271
272static void create_devtree_flash(SysBusDevice *sbdev,
273 PlatformDevtreeData *data)
274{
275 g_autofree char *name = NULL;
276 uint64_t num_blocks = object_property_get_uint(OBJECT(sbdev),
277 "num-blocks",
278 &error_fatal);
279 uint64_t sector_length = object_property_get_uint(OBJECT(sbdev),
280 "sector-length",
281 &error_fatal);
282 uint64_t bank_width = object_property_get_uint(OBJECT(sbdev),
283 "width",
284 &error_fatal);
285 hwaddr flashbase = 0;
286 hwaddr flashsize = num_blocks * sector_length;
287 void *fdt = data->fdt;
288
289 name = g_strdup_printf("%s/nor@%" PRIx64, data->node, flashbase);
290 qemu_fdt_add_subnode(fdt, name);
291 qemu_fdt_setprop_string(fdt, name, "compatible", "cfi-flash");
292 qemu_fdt_setprop_sized_cells(fdt, name, "reg",
293 1, flashbase, 1, flashsize);
294 qemu_fdt_setprop_cell(fdt, name, "bank-width", bank_width);
295}
296
297static void platform_bus_create_devtree(PPCE500MachineState *pms,
298 void *fdt, const char *mpic)
299{
300 const PPCE500MachineClass *pmc = PPCE500_MACHINE_GET_CLASS(pms);
301 gchar *node = g_strdup_printf("/platform@%"PRIx64, pmc->platform_bus_base);
302 const char platcomp[] = "qemu,platform\0simple-bus";
303 uint64_t addr = pmc->platform_bus_base;
304 uint64_t size = pmc->platform_bus_size;
305 int irq_start = pmc->platform_bus_first_irq;
306 SysBusDevice *sbdev;
307 bool ambiguous;
308
309
310
311 qemu_fdt_add_subnode(fdt, node);
312 qemu_fdt_setprop(fdt, node, "compatible", platcomp, sizeof(platcomp));
313
314
315
316 qemu_fdt_setprop_cells(fdt, node, "#size-cells", 1);
317 qemu_fdt_setprop_cells(fdt, node, "#address-cells", 1);
318 qemu_fdt_setprop_cells(fdt, node, "ranges", 0, addr >> 32, addr, size);
319
320 qemu_fdt_setprop_phandle(fdt, node, "interrupt-parent", mpic);
321
322
323 PlatformDevtreeData data = {
324 .fdt = fdt,
325 .mpic = mpic,
326 .irq_start = irq_start,
327 .node = node,
328 .pbus = pms->pbus_dev,
329 };
330
331
332 foreach_dynamic_sysbus_device(sysbus_device_create_devtree, &data);
333
334 sbdev = SYS_BUS_DEVICE(object_resolve_path_type("", TYPE_PFLASH_CFI01,
335 &ambiguous));
336 if (sbdev) {
337 assert(!ambiguous);
338 create_devtree_flash(sbdev, &data);
339 }
340
341 g_free(node);
342}
343
344static int ppce500_load_device_tree(PPCE500MachineState *pms,
345 hwaddr addr,
346 hwaddr initrd_base,
347 hwaddr initrd_size,
348 hwaddr kernel_base,
349 hwaddr kernel_size,
350 bool dry_run)
351{
352 MachineState *machine = MACHINE(pms);
353 unsigned int smp_cpus = machine->smp.cpus;
354 const PPCE500MachineClass *pmc = PPCE500_MACHINE_GET_CLASS(pms);
355 CPUPPCState *env = first_cpu->env_ptr;
356 int ret = -1;
357 uint64_t mem_reg_property[] = { 0, cpu_to_be64(machine->ram_size) };
358 int fdt_size;
359 void *fdt;
360 uint8_t hypercall[16];
361 uint32_t clock_freq = PLATFORM_CLK_FREQ_HZ;
362 uint32_t tb_freq = PLATFORM_CLK_FREQ_HZ;
363 int i;
364 char compatible_sb[] = "fsl,mpc8544-immr\0simple-bus";
365 char *soc;
366 char *mpic;
367 uint32_t mpic_ph;
368 uint32_t msi_ph;
369 char *gutil;
370 char *pci;
371 char *msi;
372 uint32_t *pci_map = NULL;
373 int len;
374 uint32_t pci_ranges[14] =
375 {
376 0x2000000, 0x0, pmc->pci_mmio_bus_base,
377 pmc->pci_mmio_base >> 32, pmc->pci_mmio_base,
378 0x0, 0x20000000,
379
380 0x1000000, 0x0, 0x0,
381 pmc->pci_pio_base >> 32, pmc->pci_pio_base,
382 0x0, 0x10000,
383 };
384 const char *dtb_file = machine->dtb;
385 const char *toplevel_compat = machine->dt_compatible;
386 uint8_t rng_seed[32];
387
388 if (dtb_file) {
389 char *filename;
390 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, dtb_file);
391 if (!filename) {
392 goto out;
393 }
394
395 fdt = load_device_tree(filename, &fdt_size);
396 g_free(filename);
397 if (!fdt) {
398 goto out;
399 }
400 goto done;
401 }
402
403 fdt = create_device_tree(&fdt_size);
404 if (fdt == NULL) {
405 goto out;
406 }
407
408
409 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 2);
410 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 2);
411
412 qemu_fdt_add_subnode(fdt, "/memory");
413 qemu_fdt_setprop_string(fdt, "/memory", "device_type", "memory");
414 qemu_fdt_setprop(fdt, "/memory", "reg", mem_reg_property,
415 sizeof(mem_reg_property));
416
417 qemu_fdt_add_subnode(fdt, "/chosen");
418 if (initrd_size) {
419 ret = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start",
420 initrd_base);
421 if (ret < 0) {
422 fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n");
423 }
424
425 ret = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end",
426 (initrd_base + initrd_size));
427 if (ret < 0) {
428 fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n");
429 }
430
431 }
432
433 if (kernel_base != -1ULL) {
434 qemu_fdt_setprop_cells(fdt, "/chosen", "qemu,boot-kernel",
435 kernel_base >> 32, kernel_base,
436 kernel_size >> 32, kernel_size);
437 }
438
439 ret = qemu_fdt_setprop_string(fdt, "/chosen", "bootargs",
440 machine->kernel_cmdline);
441 if (ret < 0)
442 fprintf(stderr, "couldn't set /chosen/bootargs\n");
443
444 qemu_guest_getrandom_nofail(rng_seed, sizeof(rng_seed));
445 qemu_fdt_setprop(fdt, "/chosen", "rng-seed", rng_seed, sizeof(rng_seed));
446
447 if (kvm_enabled()) {
448
449 clock_freq = kvmppc_get_clockfreq();
450 tb_freq = kvmppc_get_tbfreq();
451
452
453 qemu_fdt_add_subnode(fdt, "/hypervisor");
454 qemu_fdt_setprop_string(fdt, "/hypervisor", "compatible",
455 "linux,kvm");
456 kvmppc_get_hypercall(env, hypercall, sizeof(hypercall));
457 qemu_fdt_setprop(fdt, "/hypervisor", "hcall-instructions",
458 hypercall, sizeof(hypercall));
459
460 if (kvmppc_get_hasidle(env)) {
461 qemu_fdt_setprop(fdt, "/hypervisor", "has-idle", NULL, 0);
462 }
463 }
464
465
466 qemu_fdt_add_subnode(fdt, "/cpus");
467 qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 1);
468 qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0);
469
470
471
472 for (i = smp_cpus - 1; i >= 0; i--) {
473 CPUState *cpu;
474 char *cpu_name;
475 uint64_t cpu_release_addr = pmc->spin_base + (i * 0x20);
476
477 cpu = qemu_get_cpu(i);
478 if (cpu == NULL) {
479 continue;
480 }
481 env = cpu->env_ptr;
482
483 cpu_name = g_strdup_printf("/cpus/PowerPC,8544@%x", i);
484 qemu_fdt_add_subnode(fdt, cpu_name);
485 qemu_fdt_setprop_cell(fdt, cpu_name, "clock-frequency", clock_freq);
486 qemu_fdt_setprop_cell(fdt, cpu_name, "timebase-frequency", tb_freq);
487 qemu_fdt_setprop_string(fdt, cpu_name, "device_type", "cpu");
488 qemu_fdt_setprop_cell(fdt, cpu_name, "reg", i);
489 qemu_fdt_setprop_cell(fdt, cpu_name, "d-cache-line-size",
490 env->dcache_line_size);
491 qemu_fdt_setprop_cell(fdt, cpu_name, "i-cache-line-size",
492 env->icache_line_size);
493 qemu_fdt_setprop_cell(fdt, cpu_name, "d-cache-size", 0x8000);
494 qemu_fdt_setprop_cell(fdt, cpu_name, "i-cache-size", 0x8000);
495 qemu_fdt_setprop_cell(fdt, cpu_name, "bus-frequency", 0);
496 if (cpu->cpu_index) {
497 qemu_fdt_setprop_string(fdt, cpu_name, "status", "disabled");
498 qemu_fdt_setprop_string(fdt, cpu_name, "enable-method",
499 "spin-table");
500 qemu_fdt_setprop_u64(fdt, cpu_name, "cpu-release-addr",
501 cpu_release_addr);
502 } else {
503 qemu_fdt_setprop_string(fdt, cpu_name, "status", "okay");
504 }
505 g_free(cpu_name);
506 }
507
508 qemu_fdt_add_subnode(fdt, "/aliases");
509
510 soc = g_strdup_printf("/soc@%"PRIx64, pmc->ccsrbar_base);
511 qemu_fdt_add_subnode(fdt, soc);
512 qemu_fdt_setprop_string(fdt, soc, "device_type", "soc");
513 qemu_fdt_setprop(fdt, soc, "compatible", compatible_sb,
514 sizeof(compatible_sb));
515 qemu_fdt_setprop_cell(fdt, soc, "#address-cells", 1);
516 qemu_fdt_setprop_cell(fdt, soc, "#size-cells", 1);
517 qemu_fdt_setprop_cells(fdt, soc, "ranges", 0x0,
518 pmc->ccsrbar_base >> 32, pmc->ccsrbar_base,
519 MPC8544_CCSRBAR_SIZE);
520
521 qemu_fdt_setprop_cell(fdt, soc, "bus-frequency", 0);
522
523 mpic = g_strdup_printf("%s/pic@%llx", soc, MPC8544_MPIC_REGS_OFFSET);
524 qemu_fdt_add_subnode(fdt, mpic);
525 qemu_fdt_setprop_string(fdt, mpic, "device_type", "open-pic");
526 qemu_fdt_setprop_string(fdt, mpic, "compatible", "fsl,mpic");
527 qemu_fdt_setprop_cells(fdt, mpic, "reg", MPC8544_MPIC_REGS_OFFSET,
528 0x40000);
529 qemu_fdt_setprop_cell(fdt, mpic, "#address-cells", 0);
530 qemu_fdt_setprop_cell(fdt, mpic, "#interrupt-cells", 2);
531 mpic_ph = qemu_fdt_alloc_phandle(fdt);
532 qemu_fdt_setprop_cell(fdt, mpic, "phandle", mpic_ph);
533 qemu_fdt_setprop_cell(fdt, mpic, "linux,phandle", mpic_ph);
534 qemu_fdt_setprop(fdt, mpic, "interrupt-controller", NULL, 0);
535
536
537
538
539
540
541 if (serial_hd(1)) {
542 dt_serial_create(fdt, MPC8544_SERIAL1_REGS_OFFSET,
543 soc, mpic, "serial1", 1, false);
544 }
545
546 if (serial_hd(0)) {
547 dt_serial_create(fdt, MPC8544_SERIAL0_REGS_OFFSET,
548 soc, mpic, "serial0", 0, true);
549 }
550
551
552 dt_i2c_create(fdt, soc, mpic, "i2c");
553
554 dt_rtc_create(fdt, "i2c", "rtc");
555
556
557 gutil = g_strdup_printf("%s/global-utilities@%llx", soc,
558 MPC8544_UTIL_OFFSET);
559 qemu_fdt_add_subnode(fdt, gutil);
560 qemu_fdt_setprop_string(fdt, gutil, "compatible", "fsl,mpc8544-guts");
561 qemu_fdt_setprop_cells(fdt, gutil, "reg", MPC8544_UTIL_OFFSET, 0x1000);
562 qemu_fdt_setprop(fdt, gutil, "fsl,has-rstcr", NULL, 0);
563 g_free(gutil);
564
565 msi = g_strdup_printf("/%s/msi@%llx", soc, MPC8544_MSI_REGS_OFFSET);
566 qemu_fdt_add_subnode(fdt, msi);
567 qemu_fdt_setprop_string(fdt, msi, "compatible", "fsl,mpic-msi");
568 qemu_fdt_setprop_cells(fdt, msi, "reg", MPC8544_MSI_REGS_OFFSET, 0x200);
569 msi_ph = qemu_fdt_alloc_phandle(fdt);
570 qemu_fdt_setprop_cells(fdt, msi, "msi-available-ranges", 0x0, 0x100);
571 qemu_fdt_setprop_phandle(fdt, msi, "interrupt-parent", mpic);
572 qemu_fdt_setprop_cells(fdt, msi, "interrupts",
573 0xe0, 0x0,
574 0xe1, 0x0,
575 0xe2, 0x0,
576 0xe3, 0x0,
577 0xe4, 0x0,
578 0xe5, 0x0,
579 0xe6, 0x0,
580 0xe7, 0x0);
581 qemu_fdt_setprop_cell(fdt, msi, "phandle", msi_ph);
582 qemu_fdt_setprop_cell(fdt, msi, "linux,phandle", msi_ph);
583 g_free(msi);
584
585 pci = g_strdup_printf("/pci@%llx",
586 pmc->ccsrbar_base + MPC8544_PCI_REGS_OFFSET);
587 qemu_fdt_add_subnode(fdt, pci);
588 qemu_fdt_setprop_cell(fdt, pci, "cell-index", 0);
589 qemu_fdt_setprop_string(fdt, pci, "compatible", "fsl,mpc8540-pci");
590 qemu_fdt_setprop_string(fdt, pci, "device_type", "pci");
591 qemu_fdt_setprop_cells(fdt, pci, "interrupt-map-mask", 0xf800, 0x0,
592 0x0, 0x7);
593 pci_map = pci_map_create(fdt, qemu_fdt_get_phandle(fdt, mpic),
594 pmc->pci_first_slot, pmc->pci_nr_slots,
595 &len);
596 qemu_fdt_setprop(fdt, pci, "interrupt-map", pci_map, len);
597 qemu_fdt_setprop_phandle(fdt, pci, "interrupt-parent", mpic);
598 qemu_fdt_setprop_cells(fdt, pci, "interrupts", 24, 2);
599 qemu_fdt_setprop_cells(fdt, pci, "bus-range", 0, 255);
600 for (i = 0; i < 14; i++) {
601 pci_ranges[i] = cpu_to_be32(pci_ranges[i]);
602 }
603 qemu_fdt_setprop_cell(fdt, pci, "fsl,msi", msi_ph);
604 qemu_fdt_setprop(fdt, pci, "ranges", pci_ranges, sizeof(pci_ranges));
605 qemu_fdt_setprop_cells(fdt, pci, "reg",
606 (pmc->ccsrbar_base + MPC8544_PCI_REGS_OFFSET) >> 32,
607 (pmc->ccsrbar_base + MPC8544_PCI_REGS_OFFSET),
608 0, 0x1000);
609 qemu_fdt_setprop_cell(fdt, pci, "clock-frequency", 66666666);
610 qemu_fdt_setprop_cell(fdt, pci, "#interrupt-cells", 1);
611 qemu_fdt_setprop_cell(fdt, pci, "#size-cells", 2);
612 qemu_fdt_setprop_cell(fdt, pci, "#address-cells", 3);
613 qemu_fdt_setprop_string(fdt, "/aliases", "pci0", pci);
614 g_free(pci);
615
616 if (pmc->has_mpc8xxx_gpio) {
617 create_dt_mpc8xxx_gpio(fdt, soc, mpic);
618 }
619 g_free(soc);
620
621 if (pms->pbus_dev) {
622 platform_bus_create_devtree(pms, fdt, mpic);
623 }
624 g_free(mpic);
625
626 pmc->fixup_devtree(fdt);
627
628 if (toplevel_compat) {
629 qemu_fdt_setprop(fdt, "/", "compatible", toplevel_compat,
630 strlen(toplevel_compat) + 1);
631 }
632
633done:
634 if (!dry_run) {
635 qemu_fdt_dumpdtb(fdt, fdt_size);
636 cpu_physical_memory_write(addr, fdt, fdt_size);
637 }
638 ret = fdt_size;
639 g_free(fdt);
640
641out:
642 g_free(pci_map);
643
644 return ret;
645}
646
647typedef struct DeviceTreeParams {
648 PPCE500MachineState *machine;
649 hwaddr addr;
650 hwaddr initrd_base;
651 hwaddr initrd_size;
652 hwaddr kernel_base;
653 hwaddr kernel_size;
654 Notifier notifier;
655} DeviceTreeParams;
656
657static void ppce500_reset_device_tree(void *opaque)
658{
659 DeviceTreeParams *p = opaque;
660 ppce500_load_device_tree(p->machine, p->addr, p->initrd_base,
661 p->initrd_size, p->kernel_base, p->kernel_size,
662 false);
663}
664
665static void ppce500_init_notify(Notifier *notifier, void *data)
666{
667 DeviceTreeParams *p = container_of(notifier, DeviceTreeParams, notifier);
668 ppce500_reset_device_tree(p);
669}
670
671static int ppce500_prep_device_tree(PPCE500MachineState *machine,
672 hwaddr addr,
673 hwaddr initrd_base,
674 hwaddr initrd_size,
675 hwaddr kernel_base,
676 hwaddr kernel_size)
677{
678 DeviceTreeParams *p = g_new(DeviceTreeParams, 1);
679 p->machine = machine;
680 p->addr = addr;
681 p->initrd_base = initrd_base;
682 p->initrd_size = initrd_size;
683 p->kernel_base = kernel_base;
684 p->kernel_size = kernel_size;
685
686 qemu_register_reset(ppce500_reset_device_tree, p);
687 p->notifier.notify = ppce500_init_notify;
688 qemu_add_machine_init_done_notifier(&p->notifier);
689
690
691 return ppce500_load_device_tree(machine, addr, initrd_base, initrd_size,
692 kernel_base, kernel_size, true);
693}
694
695
696hwaddr booke206_page_size_to_tlb(uint64_t size)
697{
698 return 63 - clz64(size / KiB);
699}
700
701static int booke206_initial_map_tsize(CPUPPCState *env)
702{
703 struct boot_info *bi = env->load_info;
704 hwaddr dt_end;
705 int ps;
706
707
708
709 dt_end = bi->dt_base + bi->dt_size;
710 ps = booke206_page_size_to_tlb(dt_end) + 1;
711 if (ps & 1) {
712
713 ps++;
714 }
715 return ps;
716}
717
718static uint64_t mmubooke_initial_mapsize(CPUPPCState *env)
719{
720 int tsize;
721
722 tsize = booke206_initial_map_tsize(env);
723 return (1ULL << 10 << tsize);
724}
725
726static void mmubooke_create_initial_mapping(CPUPPCState *env)
727{
728 ppcmas_tlb_t *tlb = booke206_get_tlbm(env, 1, 0, 0);
729 hwaddr size;
730 int ps;
731
732 ps = booke206_initial_map_tsize(env);
733 size = (ps << MAS1_TSIZE_SHIFT);
734 tlb->mas1 = MAS1_VALID | size;
735 tlb->mas2 = 0;
736 tlb->mas7_3 = 0;
737 tlb->mas7_3 |= MAS3_UR | MAS3_UW | MAS3_UX | MAS3_SR | MAS3_SW | MAS3_SX;
738
739 env->tlb_dirty = true;
740}
741
742static void ppce500_cpu_reset_sec(void *opaque)
743{
744 PowerPCCPU *cpu = opaque;
745 CPUState *cs = CPU(cpu);
746
747 cpu_reset(cs);
748
749 cs->exception_index = EXCP_HLT;
750}
751
752static void ppce500_cpu_reset(void *opaque)
753{
754 PowerPCCPU *cpu = opaque;
755 CPUState *cs = CPU(cpu);
756 CPUPPCState *env = &cpu->env;
757 struct boot_info *bi = env->load_info;
758
759 cpu_reset(cs);
760
761
762 cs->halted = 0;
763 env->gpr[1] = (16 * MiB) - 8;
764 env->gpr[3] = bi->dt_base;
765 env->gpr[4] = 0;
766 env->gpr[5] = 0;
767 env->gpr[6] = EPAPR_MAGIC;
768 env->gpr[7] = mmubooke_initial_mapsize(env);
769 env->gpr[8] = 0;
770 env->gpr[9] = 0;
771 env->nip = bi->entry;
772 mmubooke_create_initial_mapping(env);
773}
774
775static DeviceState *ppce500_init_mpic_qemu(PPCE500MachineState *pms,
776 IrqLines *irqs)
777{
778 DeviceState *dev;
779 SysBusDevice *s;
780 int i, j, k;
781 MachineState *machine = MACHINE(pms);
782 unsigned int smp_cpus = machine->smp.cpus;
783 const PPCE500MachineClass *pmc = PPCE500_MACHINE_GET_CLASS(pms);
784
785 dev = qdev_new(TYPE_OPENPIC);
786 object_property_add_child(OBJECT(machine), "pic", OBJECT(dev));
787 qdev_prop_set_uint32(dev, "model", pmc->mpic_version);
788 qdev_prop_set_uint32(dev, "nb_cpus", smp_cpus);
789
790 s = SYS_BUS_DEVICE(dev);
791 sysbus_realize_and_unref(s, &error_fatal);
792
793 k = 0;
794 for (i = 0; i < smp_cpus; i++) {
795 for (j = 0; j < OPENPIC_OUTPUT_NB; j++) {
796 sysbus_connect_irq(s, k++, irqs[i].irq[j]);
797 }
798 }
799
800 return dev;
801}
802
803static DeviceState *ppce500_init_mpic_kvm(const PPCE500MachineClass *pmc,
804 IrqLines *irqs, Error **errp)
805{
806 DeviceState *dev;
807 CPUState *cs;
808
809 dev = qdev_new(TYPE_KVM_OPENPIC);
810 qdev_prop_set_uint32(dev, "model", pmc->mpic_version);
811
812 if (!sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), errp)) {
813 object_unparent(OBJECT(dev));
814 return NULL;
815 }
816
817 CPU_FOREACH(cs) {
818 if (kvm_openpic_connect_vcpu(dev, cs)) {
819 fprintf(stderr, "%s: failed to connect vcpu to irqchip\n",
820 __func__);
821 abort();
822 }
823 }
824
825 return dev;
826}
827
828static DeviceState *ppce500_init_mpic(PPCE500MachineState *pms,
829 MemoryRegion *ccsr,
830 IrqLines *irqs)
831{
832 const PPCE500MachineClass *pmc = PPCE500_MACHINE_GET_CLASS(pms);
833 DeviceState *dev = NULL;
834 SysBusDevice *s;
835
836 if (kvm_enabled()) {
837 Error *err = NULL;
838
839 if (kvm_kernel_irqchip_allowed()) {
840 dev = ppce500_init_mpic_kvm(pmc, irqs, &err);
841 }
842 if (kvm_kernel_irqchip_required() && !dev) {
843 error_reportf_err(err,
844 "kernel_irqchip requested but unavailable: ");
845 exit(1);
846 }
847 }
848
849 if (!dev) {
850 dev = ppce500_init_mpic_qemu(pms, irqs);
851 }
852
853 s = SYS_BUS_DEVICE(dev);
854 memory_region_add_subregion(ccsr, MPC8544_MPIC_REGS_OFFSET,
855 s->mmio[0].memory);
856
857 return dev;
858}
859
860static void ppce500_power_off(void *opaque, int line, int on)
861{
862 if (on) {
863 qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
864 }
865}
866
867void ppce500_init(MachineState *machine)
868{
869 MemoryRegion *address_space_mem = get_system_memory();
870 PPCE500MachineState *pms = PPCE500_MACHINE(machine);
871 const PPCE500MachineClass *pmc = PPCE500_MACHINE_GET_CLASS(machine);
872 PCIBus *pci_bus;
873 CPUPPCState *env = NULL;
874 uint64_t loadaddr;
875 hwaddr kernel_base = -1LL;
876 int kernel_size = 0;
877 hwaddr dt_base = 0;
878 hwaddr initrd_base = 0;
879 int initrd_size = 0;
880 hwaddr cur_base = 0;
881 char *filename;
882 const char *payload_name;
883 bool kernel_as_payload;
884 hwaddr bios_entry = 0;
885 target_long payload_size;
886 struct boot_info *boot_info;
887 int dt_size;
888 int i;
889 unsigned int smp_cpus = machine->smp.cpus;
890
891
892 unsigned int pci_irq_nrs[PCI_NUM_PINS] = {1, 2, 3, 4};
893 IrqLines *irqs;
894 DeviceState *dev, *mpicdev;
895 DriveInfo *dinfo;
896 CPUPPCState *firstenv = NULL;
897 MemoryRegion *ccsr_addr_space;
898 SysBusDevice *s;
899 PPCE500CCSRState *ccsr;
900 I2CBus *i2c;
901
902 irqs = g_new0(IrqLines, smp_cpus);
903 for (i = 0; i < smp_cpus; i++) {
904 PowerPCCPU *cpu;
905 CPUState *cs;
906
907 cpu = POWERPC_CPU(object_new(machine->cpu_type));
908 env = &cpu->env;
909 cs = CPU(cpu);
910
911 if (env->mmu_model != POWERPC_MMU_BOOKE206) {
912 error_report("MMU model %i not supported by this machine",
913 env->mmu_model);
914 exit(1);
915 }
916
917
918
919
920
921 object_property_set_bool(OBJECT(cs), "start-powered-off", i != 0,
922 &error_fatal);
923 qdev_realize_and_unref(DEVICE(cs), NULL, &error_fatal);
924
925 if (!firstenv) {
926 firstenv = env;
927 }
928
929 irqs[i].irq[OPENPIC_OUTPUT_INT] =
930 qdev_get_gpio_in(DEVICE(cpu), PPCE500_INPUT_INT);
931 irqs[i].irq[OPENPIC_OUTPUT_CINT] =
932 qdev_get_gpio_in(DEVICE(cpu), PPCE500_INPUT_CINT);
933 env->spr_cb[SPR_BOOKE_PIR].default_value = cs->cpu_index = i;
934 env->mpic_iack = pmc->ccsrbar_base + MPC8544_MPIC_REGS_OFFSET + 0xa0;
935
936 ppc_booke_timers_init(cpu, PLATFORM_CLK_FREQ_HZ, PPC_TIMER_E500);
937
938
939 if (!i) {
940
941 struct boot_info *boot_info;
942 boot_info = g_new0(struct boot_info, 1);
943 qemu_register_reset(ppce500_cpu_reset, cpu);
944 env->load_info = boot_info;
945 } else {
946
947 qemu_register_reset(ppce500_cpu_reset_sec, cpu);
948 }
949 }
950
951 env = firstenv;
952
953 if (!QEMU_IS_ALIGNED(machine->ram_size, RAM_SIZES_ALIGN)) {
954 error_report("RAM size must be multiple of %" PRIu64, RAM_SIZES_ALIGN);
955 exit(EXIT_FAILURE);
956 }
957
958
959 memory_region_add_subregion(address_space_mem, 0, machine->ram);
960
961 dev = qdev_new("e500-ccsr");
962 object_property_add_child(qdev_get_machine(), "e500-ccsr",
963 OBJECT(dev));
964 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
965 ccsr = CCSR(dev);
966 ccsr_addr_space = &ccsr->ccsr_space;
967 memory_region_add_subregion(address_space_mem, pmc->ccsrbar_base,
968 ccsr_addr_space);
969
970 mpicdev = ppce500_init_mpic(pms, ccsr_addr_space, irqs);
971 g_free(irqs);
972
973
974 if (serial_hd(0)) {
975 serial_mm_init(ccsr_addr_space, MPC8544_SERIAL0_REGS_OFFSET,
976 0, qdev_get_gpio_in(mpicdev, 42), 399193,
977 serial_hd(0), DEVICE_BIG_ENDIAN);
978 }
979
980 if (serial_hd(1)) {
981 serial_mm_init(ccsr_addr_space, MPC8544_SERIAL1_REGS_OFFSET,
982 0, qdev_get_gpio_in(mpicdev, 42), 399193,
983 serial_hd(1), DEVICE_BIG_ENDIAN);
984 }
985
986 dev = qdev_new("mpc-i2c");
987 s = SYS_BUS_DEVICE(dev);
988 sysbus_realize_and_unref(s, &error_fatal);
989 sysbus_connect_irq(s, 0, qdev_get_gpio_in(mpicdev, MPC8544_I2C_IRQ));
990 memory_region_add_subregion(ccsr_addr_space, MPC8544_I2C_REGS_OFFSET,
991 sysbus_mmio_get_region(s, 0));
992 i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c");
993 i2c_slave_create_simple(i2c, "ds1338", RTC_REGS_OFFSET);
994
995
996
997 dev = qdev_new("mpc8544-guts");
998 s = SYS_BUS_DEVICE(dev);
999 sysbus_realize_and_unref(s, &error_fatal);
1000 memory_region_add_subregion(ccsr_addr_space, MPC8544_UTIL_OFFSET,
1001 sysbus_mmio_get_region(s, 0));
1002
1003
1004 dev = qdev_new("e500-pcihost");
1005 object_property_add_child(qdev_get_machine(), "pci-host", OBJECT(dev));
1006 qdev_prop_set_uint32(dev, "first_slot", pmc->pci_first_slot);
1007 qdev_prop_set_uint32(dev, "first_pin_irq", pci_irq_nrs[0]);
1008 s = SYS_BUS_DEVICE(dev);
1009 sysbus_realize_and_unref(s, &error_fatal);
1010 for (i = 0; i < PCI_NUM_PINS; i++) {
1011 sysbus_connect_irq(s, i, qdev_get_gpio_in(mpicdev, pci_irq_nrs[i]));
1012 }
1013
1014 memory_region_add_subregion(ccsr_addr_space, MPC8544_PCI_REGS_OFFSET,
1015 sysbus_mmio_get_region(s, 0));
1016
1017 pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci.0");
1018 if (!pci_bus)
1019 printf("couldn't create PCI controller!\n");
1020
1021 if (pci_bus) {
1022
1023 for (i = 0; i < nb_nics; i++) {
1024 pci_nic_init_nofail(&nd_table[i], pci_bus, "virtio-net-pci", NULL);
1025 }
1026 }
1027
1028
1029 sysbus_create_simple("e500-spin", pmc->spin_base, NULL);
1030
1031 if (pmc->has_mpc8xxx_gpio) {
1032 qemu_irq poweroff_irq;
1033
1034 dev = qdev_new("mpc8xxx_gpio");
1035 s = SYS_BUS_DEVICE(dev);
1036 sysbus_realize_and_unref(s, &error_fatal);
1037 sysbus_connect_irq(s, 0, qdev_get_gpio_in(mpicdev, MPC8XXX_GPIO_IRQ));
1038 memory_region_add_subregion(ccsr_addr_space, MPC8XXX_GPIO_OFFSET,
1039 sysbus_mmio_get_region(s, 0));
1040
1041
1042 poweroff_irq = qemu_allocate_irq(ppce500_power_off, NULL, 0);
1043 qdev_connect_gpio_out(dev, 0, poweroff_irq);
1044 }
1045
1046
1047 dev = qdev_new(TYPE_PLATFORM_BUS_DEVICE);
1048 dev->id = g_strdup(TYPE_PLATFORM_BUS_DEVICE);
1049 qdev_prop_set_uint32(dev, "num_irqs", pmc->platform_bus_num_irqs);
1050 qdev_prop_set_uint32(dev, "mmio_size", pmc->platform_bus_size);
1051 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
1052 pms->pbus_dev = PLATFORM_BUS_DEVICE(dev);
1053
1054 s = SYS_BUS_DEVICE(pms->pbus_dev);
1055 for (i = 0; i < pmc->platform_bus_num_irqs; i++) {
1056 int irqn = pmc->platform_bus_first_irq + i;
1057 sysbus_connect_irq(s, i, qdev_get_gpio_in(mpicdev, irqn));
1058 }
1059
1060 memory_region_add_subregion(address_space_mem,
1061 pmc->platform_bus_base,
1062 &pms->pbus_dev->mmio);
1063
1064 dinfo = drive_get(IF_PFLASH, 0, 0);
1065 if (dinfo) {
1066 BlockBackend *blk = blk_by_legacy_dinfo(dinfo);
1067 BlockDriverState *bs = blk_bs(blk);
1068 uint64_t mmio_size = memory_region_size(&pms->pbus_dev->mmio);
1069 uint64_t size = bdrv_getlength(bs);
1070 uint32_t sector_len = 64 * KiB;
1071
1072 if (!is_power_of_2(size)) {
1073 error_report("Size of pflash file must be a power of two.");
1074 exit(1);
1075 }
1076
1077 if (size > mmio_size) {
1078 error_report("Size of pflash file must not be bigger than %" PRIu64
1079 " bytes.", mmio_size);
1080 exit(1);
1081 }
1082
1083 if (!QEMU_IS_ALIGNED(size, sector_len)) {
1084 error_report("Size of pflash file must be a multiple of %" PRIu32
1085 ".", sector_len);
1086 exit(1);
1087 }
1088
1089 dev = qdev_new(TYPE_PFLASH_CFI01);
1090 qdev_prop_set_drive(dev, "drive", blk);
1091 qdev_prop_set_uint32(dev, "num-blocks", size / sector_len);
1092 qdev_prop_set_uint64(dev, "sector-length", sector_len);
1093 qdev_prop_set_uint8(dev, "width", 2);
1094 qdev_prop_set_bit(dev, "big-endian", true);
1095 qdev_prop_set_uint16(dev, "id0", 0x89);
1096 qdev_prop_set_uint16(dev, "id1", 0x18);
1097 qdev_prop_set_uint16(dev, "id2", 0x0000);
1098 qdev_prop_set_uint16(dev, "id3", 0x0);
1099 qdev_prop_set_string(dev, "name", "e500.flash");
1100 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
1101
1102 memory_region_add_subregion(&pms->pbus_dev->mmio, 0,
1103 pflash_cfi01_get_memory(PFLASH_CFI01(dev)));
1104 }
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121 kernel_as_payload = false;
1122 if (machine->firmware == NULL) {
1123 if (machine->kernel_filename) {
1124 payload_name = machine->kernel_filename;
1125 kernel_as_payload = true;
1126 } else {
1127 payload_name = "u-boot.e500";
1128 }
1129 } else {
1130 payload_name = machine->firmware;
1131 }
1132
1133 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, payload_name);
1134 if (!filename) {
1135 error_report("could not find firmware/kernel file '%s'", payload_name);
1136 exit(1);
1137 }
1138
1139 payload_size = load_elf(filename, NULL, NULL, NULL,
1140 &bios_entry, &loadaddr, NULL, NULL,
1141 1, PPC_ELF_MACHINE, 0, 0);
1142 if (payload_size < 0) {
1143
1144
1145
1146
1147 loadaddr = LOAD_UIMAGE_LOADADDR_INVALID;
1148 payload_size = load_uimage(filename, &bios_entry, &loadaddr, NULL,
1149 NULL, NULL);
1150 if (payload_size < 0) {
1151 error_report("could not load firmware '%s'", filename);
1152 exit(1);
1153 }
1154 }
1155
1156 g_free(filename);
1157
1158 if (kernel_as_payload) {
1159 kernel_base = loadaddr;
1160 kernel_size = payload_size;
1161 }
1162
1163 cur_base = loadaddr + payload_size;
1164 if (cur_base < 32 * MiB) {
1165
1166 cur_base = 32 * MiB;
1167 }
1168
1169
1170 if (machine->kernel_filename && !kernel_as_payload) {
1171 kernel_base = cur_base;
1172 kernel_size = load_image_targphys(machine->kernel_filename,
1173 cur_base,
1174 machine->ram_size - cur_base);
1175 if (kernel_size < 0) {
1176 error_report("could not load kernel '%s'",
1177 machine->kernel_filename);
1178 exit(1);
1179 }
1180
1181 cur_base += kernel_size;
1182 }
1183
1184
1185 if (machine->initrd_filename) {
1186 initrd_base = (cur_base + INITRD_LOAD_PAD) & ~INITRD_PAD_MASK;
1187 initrd_size = load_image_targphys(machine->initrd_filename, initrd_base,
1188 machine->ram_size - initrd_base);
1189
1190 if (initrd_size < 0) {
1191 error_report("could not load initial ram disk '%s'",
1192 machine->initrd_filename);
1193 exit(1);
1194 }
1195
1196 cur_base = initrd_base + initrd_size;
1197 }
1198
1199
1200
1201
1202
1203
1204
1205 dt_base = (loadaddr + payload_size + DTC_LOAD_PAD) & ~DTC_PAD_MASK;
1206 if (dt_base + DTB_MAX_SIZE > machine->ram_size) {
1207 error_report("not enough memory for device tree");
1208 exit(1);
1209 }
1210
1211 dt_size = ppce500_prep_device_tree(pms, dt_base,
1212 initrd_base, initrd_size,
1213 kernel_base, kernel_size);
1214 if (dt_size < 0) {
1215 error_report("couldn't load device tree");
1216 exit(1);
1217 }
1218 assert(dt_size < DTB_MAX_SIZE);
1219
1220 boot_info = env->load_info;
1221 boot_info->entry = bios_entry;
1222 boot_info->dt_base = dt_base;
1223 boot_info->dt_size = dt_size;
1224}
1225
1226static void e500_ccsr_initfn(Object *obj)
1227{
1228 PPCE500CCSRState *ccsr = CCSR(obj);
1229 memory_region_init(&ccsr->ccsr_space, obj, "e500-ccsr",
1230 MPC8544_CCSRBAR_SIZE);
1231}
1232
1233static const TypeInfo e500_ccsr_info = {
1234 .name = TYPE_CCSR,
1235 .parent = TYPE_SYS_BUS_DEVICE,
1236 .instance_size = sizeof(PPCE500CCSRState),
1237 .instance_init = e500_ccsr_initfn,
1238};
1239
1240static const TypeInfo ppce500_info = {
1241 .name = TYPE_PPCE500_MACHINE,
1242 .parent = TYPE_MACHINE,
1243 .abstract = true,
1244 .instance_size = sizeof(PPCE500MachineState),
1245 .class_size = sizeof(PPCE500MachineClass),
1246};
1247
1248static void e500_register_types(void)
1249{
1250 type_register_static(&e500_ccsr_info);
1251 type_register_static(&ppce500_info);
1252}
1253
1254type_init(e500_register_types)
1255