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26#include "qemu/osdep.h"
27#include "qapi/error.h"
28#include "hw/irq.h"
29#include "hw/sysbus.h"
30#include "migration/vmstate.h"
31#include "hw/pci/pci.h"
32#include "hw/pci/msi.h"
33#include "hw/pci/msix.h"
34#include "hw/pci/pci_host.h"
35#include "hw/ppc/spapr.h"
36#include "hw/pci-host/spapr.h"
37#include "exec/ram_addr.h"
38#include <libfdt.h>
39#include "trace.h"
40#include "qemu/error-report.h"
41#include "qemu/module.h"
42#include "qapi/qmp/qerror.h"
43#include "hw/ppc/fdt.h"
44#include "hw/pci/pci_bridge.h"
45#include "hw/pci/pci_bus.h"
46#include "hw/pci/pci_ids.h"
47#include "hw/ppc/spapr_drc.h"
48#include "hw/qdev-properties.h"
49#include "sysemu/device_tree.h"
50#include "sysemu/kvm.h"
51#include "sysemu/hostmem.h"
52#include "sysemu/numa.h"
53#include "hw/ppc/spapr_numa.h"
54#include "qemu/log.h"
55
56
57#define RTAS_QUERY_FN 0
58#define RTAS_CHANGE_FN 1
59#define RTAS_RESET_FN 2
60#define RTAS_CHANGE_MSI_FN 3
61#define RTAS_CHANGE_MSIX_FN 4
62
63
64#define RTAS_TYPE_MSI 1
65#define RTAS_TYPE_MSIX 2
66
67SpaprPhbState *spapr_pci_find_phb(SpaprMachineState *spapr, uint64_t buid)
68{
69 SpaprPhbState *sphb;
70
71 QLIST_FOREACH(sphb, &spapr->phbs, list) {
72 if (sphb->buid != buid) {
73 continue;
74 }
75 return sphb;
76 }
77
78 return NULL;
79}
80
81PCIDevice *spapr_pci_find_dev(SpaprMachineState *spapr, uint64_t buid,
82 uint32_t config_addr)
83{
84 SpaprPhbState *sphb = spapr_pci_find_phb(spapr, buid);
85 PCIHostState *phb = PCI_HOST_BRIDGE(sphb);
86 int bus_num = (config_addr >> 16) & 0xFF;
87 int devfn = (config_addr >> 8) & 0xFF;
88
89 if (!phb) {
90 return NULL;
91 }
92
93 return pci_find_device(phb->bus, bus_num, devfn);
94}
95
96static uint32_t rtas_pci_cfgaddr(uint32_t arg)
97{
98
99 return ((arg >> 20) & 0xf00) | (arg & 0xff);
100}
101
102static void finish_read_pci_config(SpaprMachineState *spapr, uint64_t buid,
103 uint32_t addr, uint32_t size,
104 target_ulong rets)
105{
106 PCIDevice *pci_dev;
107 uint32_t val;
108
109 if ((size != 1) && (size != 2) && (size != 4)) {
110
111 rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
112 return;
113 }
114
115 pci_dev = spapr_pci_find_dev(spapr, buid, addr);
116 addr = rtas_pci_cfgaddr(addr);
117
118 if (!pci_dev || (addr % size) || (addr >= pci_config_size(pci_dev))) {
119
120
121 rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
122 return;
123 }
124
125 val = pci_host_config_read_common(pci_dev, addr,
126 pci_config_size(pci_dev), size);
127
128 rtas_st(rets, 0, RTAS_OUT_SUCCESS);
129 rtas_st(rets, 1, val);
130}
131
132static void rtas_ibm_read_pci_config(PowerPCCPU *cpu, SpaprMachineState *spapr,
133 uint32_t token, uint32_t nargs,
134 target_ulong args,
135 uint32_t nret, target_ulong rets)
136{
137 uint64_t buid;
138 uint32_t size, addr;
139
140 if ((nargs != 4) || (nret != 2)) {
141 rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
142 return;
143 }
144
145 buid = rtas_ldq(args, 1);
146 size = rtas_ld(args, 3);
147 addr = rtas_ld(args, 0);
148
149 finish_read_pci_config(spapr, buid, addr, size, rets);
150}
151
152static void rtas_read_pci_config(PowerPCCPU *cpu, SpaprMachineState *spapr,
153 uint32_t token, uint32_t nargs,
154 target_ulong args,
155 uint32_t nret, target_ulong rets)
156{
157 uint32_t size, addr;
158
159 if ((nargs != 2) || (nret != 2)) {
160 rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
161 return;
162 }
163
164 size = rtas_ld(args, 1);
165 addr = rtas_ld(args, 0);
166
167 finish_read_pci_config(spapr, 0, addr, size, rets);
168}
169
170static void finish_write_pci_config(SpaprMachineState *spapr, uint64_t buid,
171 uint32_t addr, uint32_t size,
172 uint32_t val, target_ulong rets)
173{
174 PCIDevice *pci_dev;
175
176 if ((size != 1) && (size != 2) && (size != 4)) {
177
178 rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
179 return;
180 }
181
182 pci_dev = spapr_pci_find_dev(spapr, buid, addr);
183 addr = rtas_pci_cfgaddr(addr);
184
185 if (!pci_dev || (addr % size) || (addr >= pci_config_size(pci_dev))) {
186
187
188 rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
189 return;
190 }
191
192 pci_host_config_write_common(pci_dev, addr, pci_config_size(pci_dev),
193 val, size);
194
195 rtas_st(rets, 0, RTAS_OUT_SUCCESS);
196}
197
198static void rtas_ibm_write_pci_config(PowerPCCPU *cpu, SpaprMachineState *spapr,
199 uint32_t token, uint32_t nargs,
200 target_ulong args,
201 uint32_t nret, target_ulong rets)
202{
203 uint64_t buid;
204 uint32_t val, size, addr;
205
206 if ((nargs != 5) || (nret != 1)) {
207 rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
208 return;
209 }
210
211 buid = rtas_ldq(args, 1);
212 val = rtas_ld(args, 4);
213 size = rtas_ld(args, 3);
214 addr = rtas_ld(args, 0);
215
216 finish_write_pci_config(spapr, buid, addr, size, val, rets);
217}
218
219static void rtas_write_pci_config(PowerPCCPU *cpu, SpaprMachineState *spapr,
220 uint32_t token, uint32_t nargs,
221 target_ulong args,
222 uint32_t nret, target_ulong rets)
223{
224 uint32_t val, size, addr;
225
226 if ((nargs != 3) || (nret != 1)) {
227 rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
228 return;
229 }
230
231
232 val = rtas_ld(args, 2);
233 size = rtas_ld(args, 1);
234 addr = rtas_ld(args, 0);
235
236 finish_write_pci_config(spapr, 0, addr, size, val, rets);
237}
238
239
240
241
242
243
244
245
246
247static void spapr_msi_setmsg(PCIDevice *pdev, hwaddr addr, bool msix,
248 unsigned first_irq, unsigned req_num)
249{
250 unsigned i;
251 MSIMessage msg = { .address = addr, .data = first_irq };
252
253 if (!msix) {
254 msi_set_message(pdev, msg);
255 trace_spapr_pci_msi_setup(pdev->name, 0, msg.address);
256 return;
257 }
258
259 for (i = 0; i < req_num; ++i) {
260 msix_set_message(pdev, i, msg);
261 trace_spapr_pci_msi_setup(pdev->name, i, msg.address);
262 if (addr) {
263 ++msg.data;
264 }
265 }
266}
267
268static void rtas_ibm_change_msi(PowerPCCPU *cpu, SpaprMachineState *spapr,
269 uint32_t token, uint32_t nargs,
270 target_ulong args, uint32_t nret,
271 target_ulong rets)
272{
273 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
274 uint32_t config_addr = rtas_ld(args, 0);
275 uint64_t buid = rtas_ldq(args, 1);
276 unsigned int func = rtas_ld(args, 3);
277 unsigned int req_num = rtas_ld(args, 4);
278 unsigned int seq_num = rtas_ld(args, 5);
279 unsigned int ret_intr_type;
280 unsigned int irq, max_irqs = 0;
281 SpaprPhbState *phb = NULL;
282 PCIDevice *pdev = NULL;
283 SpaprPciMsi *msi;
284 int *config_addr_key;
285 Error *err = NULL;
286 int i;
287
288
289 phb = spapr_pci_find_phb(spapr, buid);
290 if (phb) {
291 pdev = spapr_pci_find_dev(spapr, buid, config_addr);
292 }
293 if (!phb || !pdev) {
294 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
295 return;
296 }
297
298 switch (func) {
299 case RTAS_CHANGE_FN:
300 if (msi_present(pdev)) {
301 ret_intr_type = RTAS_TYPE_MSI;
302 } else if (msix_present(pdev)) {
303 ret_intr_type = RTAS_TYPE_MSIX;
304 } else {
305 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
306 return;
307 }
308 break;
309 case RTAS_CHANGE_MSI_FN:
310 if (msi_present(pdev)) {
311 ret_intr_type = RTAS_TYPE_MSI;
312 } else {
313 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
314 return;
315 }
316 break;
317 case RTAS_CHANGE_MSIX_FN:
318 if (msix_present(pdev)) {
319 ret_intr_type = RTAS_TYPE_MSIX;
320 } else {
321 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
322 return;
323 }
324 break;
325 default:
326 error_report("rtas_ibm_change_msi(%u) is not implemented", func);
327 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
328 return;
329 }
330
331 msi = (SpaprPciMsi *) g_hash_table_lookup(phb->msi, &config_addr);
332
333
334 if (!req_num) {
335 if (!msi) {
336 trace_spapr_pci_msi("Releasing wrong config", config_addr);
337 rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
338 return;
339 }
340
341 if (msi_present(pdev)) {
342 spapr_msi_setmsg(pdev, 0, false, 0, 0);
343 }
344 if (msix_present(pdev)) {
345 spapr_msi_setmsg(pdev, 0, true, 0, 0);
346 }
347 g_hash_table_remove(phb->msi, &config_addr);
348
349 trace_spapr_pci_msi("Released MSIs", config_addr);
350 rtas_st(rets, 0, RTAS_OUT_SUCCESS);
351 rtas_st(rets, 1, 0);
352 return;
353 }
354
355
356
357
358 if (ret_intr_type == RTAS_TYPE_MSI) {
359 max_irqs = msi_nr_vectors_allocated(pdev);
360 } else if (ret_intr_type == RTAS_TYPE_MSIX) {
361 max_irqs = pdev->msix_entries_nr;
362 }
363 if (!max_irqs) {
364 error_report("Requested interrupt type %d is not enabled for device %x",
365 ret_intr_type, config_addr);
366 rtas_st(rets, 0, -1);
367 return;
368 }
369
370 if (req_num > max_irqs) {
371 trace_spapr_pci_msi_retry(config_addr, req_num, max_irqs);
372 req_num = max_irqs;
373 irq = 0;
374 goto out;
375 }
376
377
378 if (smc->legacy_irq_allocation) {
379 irq = spapr_irq_find(spapr, req_num, ret_intr_type == RTAS_TYPE_MSI,
380 &err);
381 } else {
382 irq = spapr_irq_msi_alloc(spapr, req_num,
383 ret_intr_type == RTAS_TYPE_MSI, &err);
384 }
385 if (err) {
386 error_reportf_err(err, "Can't allocate MSIs for device %x: ",
387 config_addr);
388 rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
389 return;
390 }
391
392 for (i = 0; i < req_num; i++) {
393 spapr_irq_claim(spapr, irq + i, false, &err);
394 if (err) {
395 if (i) {
396 spapr_irq_free(spapr, irq, i);
397 }
398 if (!smc->legacy_irq_allocation) {
399 spapr_irq_msi_free(spapr, irq, req_num);
400 }
401 error_reportf_err(err, "Can't allocate MSIs for device %x: ",
402 config_addr);
403 rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
404 return;
405 }
406 }
407
408
409 if (msi) {
410 g_hash_table_remove(phb->msi, &config_addr);
411 }
412
413
414 spapr_msi_setmsg(pdev, SPAPR_PCI_MSI_WINDOW, ret_intr_type == RTAS_TYPE_MSIX,
415 irq, req_num);
416
417
418 msi = g_new(SpaprPciMsi, 1);
419 msi->first_irq = irq;
420 msi->num = req_num;
421 config_addr_key = g_new(int, 1);
422 *config_addr_key = config_addr;
423 g_hash_table_insert(phb->msi, config_addr_key, msi);
424
425out:
426 rtas_st(rets, 0, RTAS_OUT_SUCCESS);
427 rtas_st(rets, 1, req_num);
428 rtas_st(rets, 2, ++seq_num);
429 if (nret > 3) {
430 rtas_st(rets, 3, ret_intr_type);
431 }
432
433 trace_spapr_pci_rtas_ibm_change_msi(config_addr, func, req_num, irq);
434}
435
436static void rtas_ibm_query_interrupt_source_number(PowerPCCPU *cpu,
437 SpaprMachineState *spapr,
438 uint32_t token,
439 uint32_t nargs,
440 target_ulong args,
441 uint32_t nret,
442 target_ulong rets)
443{
444 uint32_t config_addr = rtas_ld(args, 0);
445 uint64_t buid = rtas_ldq(args, 1);
446 unsigned int intr_src_num = -1, ioa_intr_num = rtas_ld(args, 3);
447 SpaprPhbState *phb = NULL;
448 PCIDevice *pdev = NULL;
449 SpaprPciMsi *msi;
450
451
452 phb = spapr_pci_find_phb(spapr, buid);
453 if (phb) {
454 pdev = spapr_pci_find_dev(spapr, buid, config_addr);
455 }
456 if (!phb || !pdev) {
457 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
458 return;
459 }
460
461
462 msi = (SpaprPciMsi *) g_hash_table_lookup(phb->msi, &config_addr);
463 if (!msi || !msi->first_irq || !msi->num || (ioa_intr_num >= msi->num)) {
464 trace_spapr_pci_msi("Failed to return vector", config_addr);
465 rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
466 return;
467 }
468 intr_src_num = msi->first_irq + ioa_intr_num;
469 trace_spapr_pci_rtas_ibm_query_interrupt_source_number(ioa_intr_num,
470 intr_src_num);
471
472 rtas_st(rets, 0, RTAS_OUT_SUCCESS);
473 rtas_st(rets, 1, intr_src_num);
474 rtas_st(rets, 2, 1);
475}
476
477static void rtas_ibm_set_eeh_option(PowerPCCPU *cpu,
478 SpaprMachineState *spapr,
479 uint32_t token, uint32_t nargs,
480 target_ulong args, uint32_t nret,
481 target_ulong rets)
482{
483 SpaprPhbState *sphb;
484 uint32_t addr, option;
485 uint64_t buid;
486 int ret;
487
488 if ((nargs != 4) || (nret != 1)) {
489 goto param_error_exit;
490 }
491
492 buid = rtas_ldq(args, 1);
493 addr = rtas_ld(args, 0);
494 option = rtas_ld(args, 3);
495
496 sphb = spapr_pci_find_phb(spapr, buid);
497 if (!sphb) {
498 goto param_error_exit;
499 }
500
501 if (!spapr_phb_eeh_available(sphb)) {
502 goto param_error_exit;
503 }
504
505 ret = spapr_phb_vfio_eeh_set_option(sphb, addr, option);
506 rtas_st(rets, 0, ret);
507 return;
508
509param_error_exit:
510 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
511}
512
513static void rtas_ibm_get_config_addr_info2(PowerPCCPU *cpu,
514 SpaprMachineState *spapr,
515 uint32_t token, uint32_t nargs,
516 target_ulong args, uint32_t nret,
517 target_ulong rets)
518{
519 SpaprPhbState *sphb;
520 PCIDevice *pdev;
521 uint32_t addr, option;
522 uint64_t buid;
523
524 if ((nargs != 4) || (nret != 2)) {
525 goto param_error_exit;
526 }
527
528 buid = rtas_ldq(args, 1);
529 sphb = spapr_pci_find_phb(spapr, buid);
530 if (!sphb) {
531 goto param_error_exit;
532 }
533
534 if (!spapr_phb_eeh_available(sphb)) {
535 goto param_error_exit;
536 }
537
538
539
540
541
542 option = rtas_ld(args, 3);
543 switch (option) {
544 case RTAS_GET_PE_ADDR:
545 addr = rtas_ld(args, 0);
546 pdev = spapr_pci_find_dev(spapr, buid, addr);
547 if (!pdev) {
548 goto param_error_exit;
549 }
550
551 rtas_st(rets, 1, (pci_bus_num(pci_get_bus(pdev)) << 16) + 1);
552 break;
553 case RTAS_GET_PE_MODE:
554 rtas_st(rets, 1, RTAS_PE_MODE_SHARED);
555 break;
556 default:
557 goto param_error_exit;
558 }
559
560 rtas_st(rets, 0, RTAS_OUT_SUCCESS);
561 return;
562
563param_error_exit:
564 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
565}
566
567static void rtas_ibm_read_slot_reset_state2(PowerPCCPU *cpu,
568 SpaprMachineState *spapr,
569 uint32_t token, uint32_t nargs,
570 target_ulong args, uint32_t nret,
571 target_ulong rets)
572{
573 SpaprPhbState *sphb;
574 uint64_t buid;
575 int state, ret;
576
577 if ((nargs != 3) || (nret != 4 && nret != 5)) {
578 goto param_error_exit;
579 }
580
581 buid = rtas_ldq(args, 1);
582 sphb = spapr_pci_find_phb(spapr, buid);
583 if (!sphb) {
584 goto param_error_exit;
585 }
586
587 if (!spapr_phb_eeh_available(sphb)) {
588 goto param_error_exit;
589 }
590
591 ret = spapr_phb_vfio_eeh_get_state(sphb, &state);
592 rtas_st(rets, 0, ret);
593 if (ret != RTAS_OUT_SUCCESS) {
594 return;
595 }
596
597 rtas_st(rets, 1, state);
598 rtas_st(rets, 2, RTAS_EEH_SUPPORT);
599 rtas_st(rets, 3, RTAS_EEH_PE_UNAVAIL_INFO);
600 if (nret >= 5) {
601 rtas_st(rets, 4, RTAS_EEH_PE_RECOVER_INFO);
602 }
603 return;
604
605param_error_exit:
606 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
607}
608
609static void rtas_ibm_set_slot_reset(PowerPCCPU *cpu,
610 SpaprMachineState *spapr,
611 uint32_t token, uint32_t nargs,
612 target_ulong args, uint32_t nret,
613 target_ulong rets)
614{
615 SpaprPhbState *sphb;
616 uint32_t option;
617 uint64_t buid;
618 int ret;
619
620 if ((nargs != 4) || (nret != 1)) {
621 goto param_error_exit;
622 }
623
624 buid = rtas_ldq(args, 1);
625 option = rtas_ld(args, 3);
626 sphb = spapr_pci_find_phb(spapr, buid);
627 if (!sphb) {
628 goto param_error_exit;
629 }
630
631 if (!spapr_phb_eeh_available(sphb)) {
632 goto param_error_exit;
633 }
634
635 ret = spapr_phb_vfio_eeh_reset(sphb, option);
636 rtas_st(rets, 0, ret);
637 return;
638
639param_error_exit:
640 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
641}
642
643static void rtas_ibm_configure_pe(PowerPCCPU *cpu,
644 SpaprMachineState *spapr,
645 uint32_t token, uint32_t nargs,
646 target_ulong args, uint32_t nret,
647 target_ulong rets)
648{
649 SpaprPhbState *sphb;
650 uint64_t buid;
651 int ret;
652
653 if ((nargs != 3) || (nret != 1)) {
654 goto param_error_exit;
655 }
656
657 buid = rtas_ldq(args, 1);
658 sphb = spapr_pci_find_phb(spapr, buid);
659 if (!sphb) {
660 goto param_error_exit;
661 }
662
663 if (!spapr_phb_eeh_available(sphb)) {
664 goto param_error_exit;
665 }
666
667 ret = spapr_phb_vfio_eeh_configure(sphb);
668 rtas_st(rets, 0, ret);
669 return;
670
671param_error_exit:
672 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
673}
674
675
676static void rtas_ibm_slot_error_detail(PowerPCCPU *cpu,
677 SpaprMachineState *spapr,
678 uint32_t token, uint32_t nargs,
679 target_ulong args, uint32_t nret,
680 target_ulong rets)
681{
682 SpaprPhbState *sphb;
683 int option;
684 uint64_t buid;
685
686 if ((nargs != 8) || (nret != 1)) {
687 goto param_error_exit;
688 }
689
690 buid = rtas_ldq(args, 1);
691 sphb = spapr_pci_find_phb(spapr, buid);
692 if (!sphb) {
693 goto param_error_exit;
694 }
695
696 if (!spapr_phb_eeh_available(sphb)) {
697 goto param_error_exit;
698 }
699
700 option = rtas_ld(args, 7);
701 switch (option) {
702 case RTAS_SLOT_TEMP_ERR_LOG:
703 case RTAS_SLOT_PERM_ERR_LOG:
704 break;
705 default:
706 goto param_error_exit;
707 }
708
709
710 rtas_st(rets, 0, RTAS_OUT_NO_ERRORS_FOUND);
711 return;
712
713param_error_exit:
714 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
715}
716
717static void pci_spapr_set_irq(void *opaque, int irq_num, int level)
718{
719
720
721
722
723 SpaprPhbState *phb = opaque;
724 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
725
726 trace_spapr_pci_lsi_set(phb->dtbusname, irq_num, phb->lsi_table[irq_num].irq);
727 qemu_set_irq(spapr_qirq(spapr, phb->lsi_table[irq_num].irq), level);
728}
729
730static PCIINTxRoute spapr_route_intx_pin_to_irq(void *opaque, int pin)
731{
732 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(opaque);
733 PCIINTxRoute route;
734
735 route.mode = PCI_INTX_ENABLED;
736 route.irq = sphb->lsi_table[pin].irq;
737
738 return route;
739}
740
741static uint64_t spapr_msi_read(void *opaque, hwaddr addr, unsigned size)
742{
743 qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid access\n", __func__);
744 return 0;
745}
746
747
748
749
750
751
752static void spapr_msi_write(void *opaque, hwaddr addr,
753 uint64_t data, unsigned size)
754{
755 SpaprMachineState *spapr = opaque;
756 uint32_t irq = data;
757
758 trace_spapr_pci_msi_write(addr, data, irq);
759
760 qemu_irq_pulse(spapr_qirq(spapr, irq));
761}
762
763static const MemoryRegionOps spapr_msi_ops = {
764
765
766
767
768 .read = spapr_msi_read,
769 .write = spapr_msi_write,
770 .endianness = DEVICE_LITTLE_ENDIAN
771};
772
773
774
775
776static AddressSpace *spapr_pci_dma_iommu(PCIBus *bus, void *opaque, int devfn)
777{
778 SpaprPhbState *phb = opaque;
779
780 return &phb->iommu_as;
781}
782
783static char *spapr_phb_vfio_get_loc_code(SpaprPhbState *sphb, PCIDevice *pdev)
784{
785 g_autofree char *path = NULL;
786 g_autofree char *host = NULL;
787 g_autofree char *devspec = NULL;
788 char *buf = NULL;
789
790
791 host = object_property_get_str(OBJECT(pdev), "host", NULL);
792 if (!host) {
793 return NULL;
794 }
795
796
797 path = g_strdup_printf("/sys/bus/pci/devices/%s/devspec", host);
798 if (!g_file_get_contents(path, &devspec, NULL, NULL)) {
799 return NULL;
800 }
801
802
803 g_free(path);
804 path = g_strdup_printf("/proc/device-tree%s/ibm,loc-code", devspec);
805 if (!g_file_get_contents(path, &buf, NULL, NULL)) {
806 return NULL;
807 }
808 return buf;
809}
810
811static char *spapr_phb_get_loc_code(SpaprPhbState *sphb, PCIDevice *pdev)
812{
813 char *buf;
814 const char *devtype = "qemu";
815 uint32_t busnr = pci_bus_num(PCI_BUS(qdev_get_parent_bus(DEVICE(pdev))));
816
817 if (object_dynamic_cast(OBJECT(pdev), "vfio-pci")) {
818 buf = spapr_phb_vfio_get_loc_code(sphb, pdev);
819 if (buf) {
820 return buf;
821 }
822 devtype = "vfio";
823 }
824
825
826
827
828 buf = g_strdup_printf("%s_%s:%04x:%02x:%02x.%x",
829 devtype, pdev->name, sphb->index, busnr,
830 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn));
831 return buf;
832}
833
834
835#define b_x(x, p, l) (((x) & ((1<<(l))-1)) << (p))
836#define b_n(x) b_x((x), 31, 1)
837#define b_p(x) b_x((x), 30, 1)
838#define b_t(x) b_x((x), 29, 1)
839#define b_ss(x) b_x((x), 24, 2)
840#define b_bbbbbbbb(x) b_x((x), 16, 8)
841#define b_ddddd(x) b_x((x), 11, 5)
842#define b_fff(x) b_x((x), 8, 3)
843#define b_rrrrrrrr(x) b_x((x), 0, 8)
844
845
846#define RESOURCE_CELLS_SIZE 2
847#define RESOURCE_CELLS_ADDRESS 3
848
849typedef struct ResourceFields {
850 uint32_t phys_hi;
851 uint32_t phys_mid;
852 uint32_t phys_lo;
853 uint32_t size_hi;
854 uint32_t size_lo;
855} QEMU_PACKED ResourceFields;
856
857typedef struct ResourceProps {
858 ResourceFields reg[8];
859 uint32_t reg_len;
860} ResourceProps;
861
862
863
864
865
866
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869
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880
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901
902
903static void populate_resource_props(PCIDevice *d, ResourceProps *rp)
904{
905 int bus_num = pci_bus_num(PCI_BUS(qdev_get_parent_bus(DEVICE(d))));
906 uint32_t dev_id = (b_bbbbbbbb(bus_num) |
907 b_ddddd(PCI_SLOT(d->devfn)) |
908 b_fff(PCI_FUNC(d->devfn)));
909 ResourceFields *reg;
910 int i, reg_idx = 0;
911
912
913 reg = &rp->reg[reg_idx++];
914 reg->phys_hi = cpu_to_be32(dev_id);
915 reg->phys_mid = 0;
916 reg->phys_lo = 0;
917 reg->size_hi = 0;
918 reg->size_lo = 0;
919
920 for (i = 0; i < PCI_NUM_REGIONS; i++) {
921 if (!d->io_regions[i].size) {
922 continue;
923 }
924
925 reg = &rp->reg[reg_idx++];
926
927 reg->phys_hi = cpu_to_be32(dev_id | b_rrrrrrrr(pci_bar(d, i)));
928 if (d->io_regions[i].type & PCI_BASE_ADDRESS_SPACE_IO) {
929 reg->phys_hi |= cpu_to_be32(b_ss(1));
930 } else if (d->io_regions[i].type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
931 reg->phys_hi |= cpu_to_be32(b_ss(3));
932 } else {
933 reg->phys_hi |= cpu_to_be32(b_ss(2));
934 }
935 reg->phys_mid = 0;
936 reg->phys_lo = 0;
937 reg->size_hi = cpu_to_be32(d->io_regions[i].size >> 32);
938 reg->size_lo = cpu_to_be32(d->io_regions[i].size);
939 }
940
941 rp->reg_len = reg_idx * sizeof(ResourceFields);
942}
943
944typedef struct PCIClass PCIClass;
945typedef struct PCISubClass PCISubClass;
946typedef struct PCIIFace PCIIFace;
947
948struct PCIIFace {
949 int iface;
950 const char *name;
951};
952
953struct PCISubClass {
954 int subclass;
955 const char *name;
956 const PCIIFace *iface;
957};
958
959struct PCIClass {
960 const char *name;
961 const PCISubClass *subc;
962};
963
964static const PCISubClass undef_subclass[] = {
965 { PCI_CLASS_NOT_DEFINED_VGA, "display", NULL },
966 { 0xFF, NULL, NULL },
967};
968
969static const PCISubClass mass_subclass[] = {
970 { PCI_CLASS_STORAGE_SCSI, "scsi", NULL },
971 { PCI_CLASS_STORAGE_IDE, "ide", NULL },
972 { PCI_CLASS_STORAGE_FLOPPY, "fdc", NULL },
973 { PCI_CLASS_STORAGE_IPI, "ipi", NULL },
974 { PCI_CLASS_STORAGE_RAID, "raid", NULL },
975 { PCI_CLASS_STORAGE_ATA, "ata", NULL },
976 { PCI_CLASS_STORAGE_SATA, "sata", NULL },
977 { PCI_CLASS_STORAGE_SAS, "sas", NULL },
978 { 0xFF, NULL, NULL },
979};
980
981static const PCISubClass net_subclass[] = {
982 { PCI_CLASS_NETWORK_ETHERNET, "ethernet", NULL },
983 { PCI_CLASS_NETWORK_TOKEN_RING, "token-ring", NULL },
984 { PCI_CLASS_NETWORK_FDDI, "fddi", NULL },
985 { PCI_CLASS_NETWORK_ATM, "atm", NULL },
986 { PCI_CLASS_NETWORK_ISDN, "isdn", NULL },
987 { PCI_CLASS_NETWORK_WORLDFIP, "worldfip", NULL },
988 { PCI_CLASS_NETWORK_PICMG214, "picmg", NULL },
989 { 0xFF, NULL, NULL },
990};
991
992static const PCISubClass displ_subclass[] = {
993 { PCI_CLASS_DISPLAY_VGA, "vga", NULL },
994 { PCI_CLASS_DISPLAY_XGA, "xga", NULL },
995 { PCI_CLASS_DISPLAY_3D, "3d-controller", NULL },
996 { 0xFF, NULL, NULL },
997};
998
999static const PCISubClass media_subclass[] = {
1000 { PCI_CLASS_MULTIMEDIA_VIDEO, "video", NULL },
1001 { PCI_CLASS_MULTIMEDIA_AUDIO, "sound", NULL },
1002 { PCI_CLASS_MULTIMEDIA_PHONE, "telephony", NULL },
1003 { 0xFF, NULL, NULL },
1004};
1005
1006static const PCISubClass mem_subclass[] = {
1007 { PCI_CLASS_MEMORY_RAM, "memory", NULL },
1008 { PCI_CLASS_MEMORY_FLASH, "flash", NULL },
1009 { 0xFF, NULL, NULL },
1010};
1011
1012static const PCISubClass bridg_subclass[] = {
1013 { PCI_CLASS_BRIDGE_HOST, "host", NULL },
1014 { PCI_CLASS_BRIDGE_ISA, "isa", NULL },
1015 { PCI_CLASS_BRIDGE_EISA, "eisa", NULL },
1016 { PCI_CLASS_BRIDGE_MC, "mca", NULL },
1017 { PCI_CLASS_BRIDGE_PCI, "pci", NULL },
1018 { PCI_CLASS_BRIDGE_PCMCIA, "pcmcia", NULL },
1019 { PCI_CLASS_BRIDGE_NUBUS, "nubus", NULL },
1020 { PCI_CLASS_BRIDGE_CARDBUS, "cardbus", NULL },
1021 { PCI_CLASS_BRIDGE_RACEWAY, "raceway", NULL },
1022 { PCI_CLASS_BRIDGE_PCI_SEMITP, "semi-transparent-pci", NULL },
1023 { PCI_CLASS_BRIDGE_IB_PCI, "infiniband", NULL },
1024 { 0xFF, NULL, NULL },
1025};
1026
1027static const PCISubClass comm_subclass[] = {
1028 { PCI_CLASS_COMMUNICATION_SERIAL, "serial", NULL },
1029 { PCI_CLASS_COMMUNICATION_PARALLEL, "parallel", NULL },
1030 { PCI_CLASS_COMMUNICATION_MULTISERIAL, "multiport-serial", NULL },
1031 { PCI_CLASS_COMMUNICATION_MODEM, "modem", NULL },
1032 { PCI_CLASS_COMMUNICATION_GPIB, "gpib", NULL },
1033 { PCI_CLASS_COMMUNICATION_SC, "smart-card", NULL },
1034 { 0xFF, NULL, NULL, },
1035};
1036
1037static const PCIIFace pic_iface[] = {
1038 { PCI_CLASS_SYSTEM_PIC_IOAPIC, "io-apic" },
1039 { PCI_CLASS_SYSTEM_PIC_IOXAPIC, "io-xapic" },
1040 { 0xFF, NULL },
1041};
1042
1043static const PCISubClass sys_subclass[] = {
1044 { PCI_CLASS_SYSTEM_PIC, "interrupt-controller", pic_iface },
1045 { PCI_CLASS_SYSTEM_DMA, "dma-controller", NULL },
1046 { PCI_CLASS_SYSTEM_TIMER, "timer", NULL },
1047 { PCI_CLASS_SYSTEM_RTC, "rtc", NULL },
1048 { PCI_CLASS_SYSTEM_PCI_HOTPLUG, "hot-plug-controller", NULL },
1049 { PCI_CLASS_SYSTEM_SDHCI, "sd-host-controller", NULL },
1050 { 0xFF, NULL, NULL },
1051};
1052
1053static const PCISubClass inp_subclass[] = {
1054 { PCI_CLASS_INPUT_KEYBOARD, "keyboard", NULL },
1055 { PCI_CLASS_INPUT_PEN, "pen", NULL },
1056 { PCI_CLASS_INPUT_MOUSE, "mouse", NULL },
1057 { PCI_CLASS_INPUT_SCANNER, "scanner", NULL },
1058 { PCI_CLASS_INPUT_GAMEPORT, "gameport", NULL },
1059 { 0xFF, NULL, NULL },
1060};
1061
1062static const PCISubClass dock_subclass[] = {
1063 { PCI_CLASS_DOCKING_GENERIC, "dock", NULL },
1064 { 0xFF, NULL, NULL },
1065};
1066
1067static const PCISubClass cpu_subclass[] = {
1068 { PCI_CLASS_PROCESSOR_PENTIUM, "pentium", NULL },
1069 { PCI_CLASS_PROCESSOR_POWERPC, "powerpc", NULL },
1070 { PCI_CLASS_PROCESSOR_MIPS, "mips", NULL },
1071 { PCI_CLASS_PROCESSOR_CO, "co-processor", NULL },
1072 { 0xFF, NULL, NULL },
1073};
1074
1075static const PCIIFace usb_iface[] = {
1076 { PCI_CLASS_SERIAL_USB_UHCI, "usb-uhci" },
1077 { PCI_CLASS_SERIAL_USB_OHCI, "usb-ohci", },
1078 { PCI_CLASS_SERIAL_USB_EHCI, "usb-ehci" },
1079 { PCI_CLASS_SERIAL_USB_XHCI, "usb-xhci" },
1080 { PCI_CLASS_SERIAL_USB_UNKNOWN, "usb-unknown" },
1081 { PCI_CLASS_SERIAL_USB_DEVICE, "usb-device" },
1082 { 0xFF, NULL },
1083};
1084
1085static const PCISubClass ser_subclass[] = {
1086 { PCI_CLASS_SERIAL_FIREWIRE, "firewire", NULL },
1087 { PCI_CLASS_SERIAL_ACCESS, "access-bus", NULL },
1088 { PCI_CLASS_SERIAL_SSA, "ssa", NULL },
1089 { PCI_CLASS_SERIAL_USB, "usb", usb_iface },
1090 { PCI_CLASS_SERIAL_FIBER, "fibre-channel", NULL },
1091 { PCI_CLASS_SERIAL_SMBUS, "smb", NULL },
1092 { PCI_CLASS_SERIAL_IB, "infiniband", NULL },
1093 { PCI_CLASS_SERIAL_IPMI, "ipmi", NULL },
1094 { PCI_CLASS_SERIAL_SERCOS, "sercos", NULL },
1095 { PCI_CLASS_SERIAL_CANBUS, "canbus", NULL },
1096 { 0xFF, NULL, NULL },
1097};
1098
1099static const PCISubClass wrl_subclass[] = {
1100 { PCI_CLASS_WIRELESS_IRDA, "irda", NULL },
1101 { PCI_CLASS_WIRELESS_CIR, "consumer-ir", NULL },
1102 { PCI_CLASS_WIRELESS_RF_CONTROLLER, "rf-controller", NULL },
1103 { PCI_CLASS_WIRELESS_BLUETOOTH, "bluetooth", NULL },
1104 { PCI_CLASS_WIRELESS_BROADBAND, "broadband", NULL },
1105 { 0xFF, NULL, NULL },
1106};
1107
1108static const PCISubClass sat_subclass[] = {
1109 { PCI_CLASS_SATELLITE_TV, "satellite-tv", NULL },
1110 { PCI_CLASS_SATELLITE_AUDIO, "satellite-audio", NULL },
1111 { PCI_CLASS_SATELLITE_VOICE, "satellite-voice", NULL },
1112 { PCI_CLASS_SATELLITE_DATA, "satellite-data", NULL },
1113 { 0xFF, NULL, NULL },
1114};
1115
1116static const PCISubClass crypt_subclass[] = {
1117 { PCI_CLASS_CRYPT_NETWORK, "network-encryption", NULL },
1118 { PCI_CLASS_CRYPT_ENTERTAINMENT,
1119 "entertainment-encryption", NULL },
1120 { 0xFF, NULL, NULL },
1121};
1122
1123static const PCISubClass spc_subclass[] = {
1124 { PCI_CLASS_SP_DPIO, "dpio", NULL },
1125 { PCI_CLASS_SP_PERF, "counter", NULL },
1126 { PCI_CLASS_SP_SYNCH, "measurement", NULL },
1127 { PCI_CLASS_SP_MANAGEMENT, "management-card", NULL },
1128 { 0xFF, NULL, NULL },
1129};
1130
1131static const PCIClass pci_classes[] = {
1132 { "legacy-device", undef_subclass },
1133 { "mass-storage", mass_subclass },
1134 { "network", net_subclass },
1135 { "display", displ_subclass, },
1136 { "multimedia-device", media_subclass },
1137 { "memory-controller", mem_subclass },
1138 { "unknown-bridge", bridg_subclass },
1139 { "communication-controller", comm_subclass},
1140 { "system-peripheral", sys_subclass },
1141 { "input-controller", inp_subclass },
1142 { "docking-station", dock_subclass },
1143 { "cpu", cpu_subclass },
1144 { "serial-bus", ser_subclass },
1145 { "wireless-controller", wrl_subclass },
1146 { "intelligent-io", NULL },
1147 { "satellite-device", sat_subclass },
1148 { "encryption", crypt_subclass },
1149 { "data-processing-controller", spc_subclass },
1150};
1151
1152static const char *dt_name_from_class(uint8_t class, uint8_t subclass,
1153 uint8_t iface)
1154{
1155 const PCIClass *pclass;
1156 const PCISubClass *psubclass;
1157 const PCIIFace *piface;
1158 const char *name;
1159
1160 if (class >= ARRAY_SIZE(pci_classes)) {
1161 return "pci";
1162 }
1163
1164 pclass = pci_classes + class;
1165 name = pclass->name;
1166
1167 if (pclass->subc == NULL) {
1168 return name;
1169 }
1170
1171 psubclass = pclass->subc;
1172 while ((psubclass->subclass & 0xff) != 0xff) {
1173 if ((psubclass->subclass & 0xff) == subclass) {
1174 name = psubclass->name;
1175 break;
1176 }
1177 psubclass++;
1178 }
1179
1180 piface = psubclass->iface;
1181 if (piface == NULL) {
1182 return name;
1183 }
1184 while ((piface->iface & 0xff) != 0xff) {
1185 if ((piface->iface & 0xff) == iface) {
1186 name = piface->name;
1187 break;
1188 }
1189 piface++;
1190 }
1191
1192 return name;
1193}
1194
1195
1196
1197
1198
1199static uint32_t drc_id_from_devfn(SpaprPhbState *phb,
1200 uint8_t chassis, int32_t devfn)
1201{
1202 return (phb->index << 16) | (chassis << 8) | devfn;
1203}
1204
1205static SpaprDrc *drc_from_devfn(SpaprPhbState *phb,
1206 uint8_t chassis, int32_t devfn)
1207{
1208 return spapr_drc_by_id(TYPE_SPAPR_DRC_PCI,
1209 drc_id_from_devfn(phb, chassis, devfn));
1210}
1211
1212static uint8_t chassis_from_bus(PCIBus *bus)
1213{
1214 if (pci_bus_is_root(bus)) {
1215 return 0;
1216 } else {
1217 PCIDevice *bridge = pci_bridge_get_device(bus);
1218
1219 return object_property_get_uint(OBJECT(bridge), "chassis_nr",
1220 &error_abort);
1221 }
1222}
1223
1224static SpaprDrc *drc_from_dev(SpaprPhbState *phb, PCIDevice *dev)
1225{
1226 uint8_t chassis = chassis_from_bus(pci_get_bus(dev));
1227
1228 return drc_from_devfn(phb, chassis, dev->devfn);
1229}
1230
1231static void add_drcs(SpaprPhbState *phb, PCIBus *bus)
1232{
1233 Object *owner;
1234 int i;
1235 uint8_t chassis;
1236
1237 if (!phb->dr_enabled) {
1238 return;
1239 }
1240
1241 chassis = chassis_from_bus(bus);
1242
1243 if (pci_bus_is_root(bus)) {
1244 owner = OBJECT(phb);
1245 } else {
1246 owner = OBJECT(pci_bridge_get_device(bus));
1247 }
1248
1249 for (i = 0; i < PCI_SLOT_MAX * PCI_FUNC_MAX; i++) {
1250 spapr_dr_connector_new(owner, TYPE_SPAPR_DRC_PCI,
1251 drc_id_from_devfn(phb, chassis, i));
1252 }
1253}
1254
1255static void remove_drcs(SpaprPhbState *phb, PCIBus *bus)
1256{
1257 int i;
1258 uint8_t chassis;
1259
1260 if (!phb->dr_enabled) {
1261 return;
1262 }
1263
1264 chassis = chassis_from_bus(bus);
1265
1266 for (i = PCI_SLOT_MAX * PCI_FUNC_MAX - 1; i >= 0; i--) {
1267 SpaprDrc *drc = drc_from_devfn(phb, chassis, i);
1268
1269 if (drc) {
1270 object_unparent(OBJECT(drc));
1271 }
1272 }
1273}
1274
1275typedef struct PciWalkFdt {
1276 void *fdt;
1277 int offset;
1278 SpaprPhbState *sphb;
1279 int err;
1280} PciWalkFdt;
1281
1282static int spapr_dt_pci_device(SpaprPhbState *sphb, PCIDevice *dev,
1283 void *fdt, int parent_offset);
1284
1285static void spapr_dt_pci_device_cb(PCIBus *bus, PCIDevice *pdev,
1286 void *opaque)
1287{
1288 PciWalkFdt *p = opaque;
1289 int err;
1290
1291 if (p->err) {
1292
1293 return;
1294 }
1295
1296 err = spapr_dt_pci_device(p->sphb, pdev, p->fdt, p->offset);
1297 if (err < 0) {
1298 p->err = err;
1299 }
1300}
1301
1302
1303static int spapr_dt_pci_bus(SpaprPhbState *sphb, PCIBus *bus,
1304 void *fdt, int offset)
1305{
1306 Object *owner;
1307 PciWalkFdt cbinfo = {
1308 .fdt = fdt,
1309 .offset = offset,
1310 .sphb = sphb,
1311 .err = 0,
1312 };
1313 int ret;
1314
1315 _FDT(fdt_setprop_cell(fdt, offset, "#address-cells",
1316 RESOURCE_CELLS_ADDRESS));
1317 _FDT(fdt_setprop_cell(fdt, offset, "#size-cells",
1318 RESOURCE_CELLS_SIZE));
1319
1320 assert(bus);
1321 pci_for_each_device_under_bus_reverse(bus, spapr_dt_pci_device_cb, &cbinfo);
1322 if (cbinfo.err) {
1323 return cbinfo.err;
1324 }
1325
1326 if (pci_bus_is_root(bus)) {
1327 owner = OBJECT(sphb);
1328 } else {
1329 owner = OBJECT(pci_bridge_get_device(bus));
1330 }
1331
1332 ret = spapr_dt_drc(fdt, offset, owner,
1333 SPAPR_DR_CONNECTOR_TYPE_PCI);
1334 if (ret) {
1335 return ret;
1336 }
1337
1338 return offset;
1339}
1340
1341char *spapr_pci_fw_dev_name(PCIDevice *dev)
1342{
1343 const gchar *basename;
1344 int slot = PCI_SLOT(dev->devfn);
1345 int func = PCI_FUNC(dev->devfn);
1346 uint32_t ccode = pci_default_read_config(dev, PCI_CLASS_PROG, 3);
1347
1348 basename = dt_name_from_class((ccode >> 16) & 0xff, (ccode >> 8) & 0xff,
1349 ccode & 0xff);
1350
1351 if (func != 0) {
1352 return g_strdup_printf("%s@%x,%x", basename, slot, func);
1353 } else {
1354 return g_strdup_printf("%s@%x", basename, slot);
1355 }
1356}
1357
1358
1359static int spapr_dt_pci_device(SpaprPhbState *sphb, PCIDevice *dev,
1360 void *fdt, int parent_offset)
1361{
1362 int offset;
1363 g_autofree gchar *nodename = spapr_pci_fw_dev_name(dev);
1364 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev);
1365 ResourceProps rp;
1366 SpaprDrc *drc = drc_from_dev(sphb, dev);
1367 uint32_t vendor_id = pci_default_read_config(dev, PCI_VENDOR_ID, 2);
1368 uint32_t device_id = pci_default_read_config(dev, PCI_DEVICE_ID, 2);
1369 uint32_t revision_id = pci_default_read_config(dev, PCI_REVISION_ID, 1);
1370 uint32_t ccode = pci_default_read_config(dev, PCI_CLASS_PROG, 3);
1371 uint32_t irq_pin = pci_default_read_config(dev, PCI_INTERRUPT_PIN, 1);
1372 uint32_t subsystem_id = pci_default_read_config(dev, PCI_SUBSYSTEM_ID, 2);
1373 uint32_t subsystem_vendor_id =
1374 pci_default_read_config(dev, PCI_SUBSYSTEM_VENDOR_ID, 2);
1375 uint32_t cache_line_size =
1376 pci_default_read_config(dev, PCI_CACHE_LINE_SIZE, 1);
1377 uint32_t pci_status = pci_default_read_config(dev, PCI_STATUS, 2);
1378 gchar *loc_code;
1379
1380 _FDT(offset = fdt_add_subnode(fdt, parent_offset, nodename));
1381
1382
1383 _FDT(fdt_setprop_cell(fdt, offset, "vendor-id", vendor_id));
1384 _FDT(fdt_setprop_cell(fdt, offset, "device-id", device_id));
1385 _FDT(fdt_setprop_cell(fdt, offset, "revision-id", revision_id));
1386
1387 _FDT(fdt_setprop_cell(fdt, offset, "class-code", ccode));
1388 if (irq_pin) {
1389 _FDT(fdt_setprop_cell(fdt, offset, "interrupts", irq_pin));
1390 }
1391
1392 if (subsystem_id) {
1393 _FDT(fdt_setprop_cell(fdt, offset, "subsystem-id", subsystem_id));
1394 }
1395
1396 if (subsystem_vendor_id) {
1397 _FDT(fdt_setprop_cell(fdt, offset, "subsystem-vendor-id",
1398 subsystem_vendor_id));
1399 }
1400
1401 _FDT(fdt_setprop_cell(fdt, offset, "cache-line-size", cache_line_size));
1402
1403
1404
1405 _FDT(fdt_setprop_cell(fdt, offset, "devsel-speed",
1406 PCI_STATUS_DEVSEL_MASK & pci_status));
1407
1408 if (pci_status & PCI_STATUS_FAST_BACK) {
1409 _FDT(fdt_setprop(fdt, offset, "fast-back-to-back", NULL, 0));
1410 }
1411 if (pci_status & PCI_STATUS_66MHZ) {
1412 _FDT(fdt_setprop(fdt, offset, "66mhz-capable", NULL, 0));
1413 }
1414 if (pci_status & PCI_STATUS_UDF) {
1415 _FDT(fdt_setprop(fdt, offset, "udf-supported", NULL, 0));
1416 }
1417
1418 loc_code = spapr_phb_get_loc_code(sphb, dev);
1419 _FDT(fdt_setprop_string(fdt, offset, "ibm,loc-code", loc_code));
1420 g_free(loc_code);
1421
1422 if (drc) {
1423 _FDT(fdt_setprop_cell(fdt, offset, "ibm,my-drc-index",
1424 spapr_drc_index(drc)));
1425 }
1426
1427 if (msi_present(dev)) {
1428 uint32_t max_msi = msi_nr_vectors_allocated(dev);
1429 if (max_msi) {
1430 _FDT(fdt_setprop_cell(fdt, offset, "ibm,req#msi", max_msi));
1431 }
1432 }
1433 if (msix_present(dev)) {
1434 uint32_t max_msix = dev->msix_entries_nr;
1435 if (max_msix) {
1436 _FDT(fdt_setprop_cell(fdt, offset, "ibm,req#msi-x", max_msix));
1437 }
1438 }
1439
1440 populate_resource_props(dev, &rp);
1441 _FDT(fdt_setprop(fdt, offset, "reg", (uint8_t *)rp.reg, rp.reg_len));
1442
1443 if (sphb->pcie_ecs && pci_is_express(dev)) {
1444 _FDT(fdt_setprop_cell(fdt, offset, "ibm,pci-config-space-type", 0x1));
1445 }
1446
1447 spapr_phb_nvgpu_populate_pcidev_dt(dev, fdt, offset, sphb);
1448
1449 if (!pc->is_bridge) {
1450
1451 uint32_t min_grant = pci_default_read_config(dev, PCI_MIN_GNT, 1);
1452 uint32_t max_latency = pci_default_read_config(dev, PCI_MAX_LAT, 1);
1453 _FDT(fdt_setprop_cell(fdt, offset, "min-grant", min_grant));
1454 _FDT(fdt_setprop_cell(fdt, offset, "max-latency", max_latency));
1455 return offset;
1456 } else {
1457 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(dev));
1458
1459 return spapr_dt_pci_bus(sphb, sec_bus, fdt, offset);
1460 }
1461}
1462
1463
1464void spapr_phb_remove_pci_device_cb(DeviceState *dev)
1465{
1466 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev);
1467
1468 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort);
1469 object_unparent(OBJECT(dev));
1470}
1471
1472int spapr_pci_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr,
1473 void *fdt, int *fdt_start_offset, Error **errp)
1474{
1475 HotplugHandler *plug_handler = qdev_get_hotplug_handler(drc->dev);
1476 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(plug_handler);
1477 PCIDevice *pdev = PCI_DEVICE(drc->dev);
1478
1479 *fdt_start_offset = spapr_dt_pci_device(sphb, pdev, fdt, 0);
1480 return 0;
1481}
1482
1483static void spapr_pci_bridge_plug(SpaprPhbState *phb,
1484 PCIBridge *bridge)
1485{
1486 PCIBus *bus = pci_bridge_get_sec_bus(bridge);
1487
1488 add_drcs(phb, bus);
1489}
1490
1491
1492static int check_chassis_nr(Object *obj, void *opaque)
1493{
1494 int new_chassis_nr =
1495 object_property_get_uint(opaque, "chassis_nr", &error_abort);
1496 int chassis_nr =
1497 object_property_get_uint(obj, "chassis_nr", NULL);
1498
1499 if (!object_dynamic_cast(obj, TYPE_PCI_BRIDGE)) {
1500 return 0;
1501 }
1502
1503
1504 if (!chassis_nr) {
1505 return 0;
1506 }
1507
1508
1509 if (obj == opaque) {
1510 return 0;
1511 }
1512
1513 return chassis_nr == new_chassis_nr;
1514}
1515
1516static bool bridge_has_valid_chassis_nr(Object *bridge, Error **errp)
1517{
1518 int chassis_nr =
1519 object_property_get_uint(bridge, "chassis_nr", NULL);
1520
1521
1522
1523
1524
1525
1526 if (!chassis_nr) {
1527 error_setg(errp, "PCI Bridge lacks a \"chassis_nr\" property");
1528 error_append_hint(errp, "Try -device pci-bridge instead.\n");
1529 return false;
1530 }
1531
1532
1533 if (object_child_foreach_recursive(object_get_root(), check_chassis_nr,
1534 bridge)) {
1535 error_setg(errp, "Bridge chassis %d already in use", chassis_nr);
1536 return false;
1537 }
1538
1539 return true;
1540}
1541
1542static void spapr_pci_pre_plug(HotplugHandler *plug_handler,
1543 DeviceState *plugged_dev, Error **errp)
1544{
1545 SpaprPhbState *phb = SPAPR_PCI_HOST_BRIDGE(DEVICE(plug_handler));
1546 PCIDevice *pdev = PCI_DEVICE(plugged_dev);
1547 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(plugged_dev);
1548 SpaprDrc *drc = drc_from_dev(phb, pdev);
1549 PCIBus *bus = PCI_BUS(qdev_get_parent_bus(DEVICE(pdev)));
1550 uint32_t slotnr = PCI_SLOT(pdev->devfn);
1551
1552 if (!phb->dr_enabled) {
1553
1554
1555
1556 if (plugged_dev->hotplugged) {
1557 error_setg(errp, QERR_BUS_NO_HOTPLUG,
1558 object_get_typename(OBJECT(phb)));
1559 return;
1560 }
1561 }
1562
1563 if (pc->is_bridge) {
1564 if (!bridge_has_valid_chassis_nr(OBJECT(plugged_dev), errp)) {
1565 return;
1566 }
1567 }
1568
1569
1570
1571
1572
1573 if (plugged_dev->hotplugged && bus->devices[PCI_DEVFN(slotnr, 0)] &&
1574 PCI_FUNC(pdev->devfn) != 0) {
1575 error_setg(errp, "PCI: slot %d function 0 already occupied by %s,"
1576 " additional functions can no longer be exposed to guest.",
1577 slotnr, bus->devices[PCI_DEVFN(slotnr, 0)]->name);
1578 }
1579
1580 if (drc && drc->dev) {
1581 error_setg(errp, "PCI: slot %d already occupied by %s", slotnr,
1582 pci_get_function_0(PCI_DEVICE(drc->dev))->name);
1583 return;
1584 }
1585}
1586
1587static void spapr_pci_plug(HotplugHandler *plug_handler,
1588 DeviceState *plugged_dev, Error **errp)
1589{
1590 SpaprPhbState *phb = SPAPR_PCI_HOST_BRIDGE(DEVICE(plug_handler));
1591 PCIDevice *pdev = PCI_DEVICE(plugged_dev);
1592 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(plugged_dev);
1593 SpaprDrc *drc = drc_from_dev(phb, pdev);
1594 uint32_t slotnr = PCI_SLOT(pdev->devfn);
1595
1596
1597
1598
1599
1600 if (!phb->dr_enabled) {
1601 return;
1602 }
1603
1604 g_assert(drc);
1605
1606 if (pc->is_bridge) {
1607 spapr_pci_bridge_plug(phb, PCI_BRIDGE(plugged_dev));
1608 }
1609
1610
1611 spapr_drc_attach(drc, DEVICE(pdev));
1612
1613
1614
1615
1616 if (!spapr_drc_hotplugged(plugged_dev)) {
1617 spapr_drc_reset(drc);
1618 } else if (PCI_FUNC(pdev->devfn) == 0) {
1619 int i;
1620 uint8_t chassis = chassis_from_bus(pci_get_bus(pdev));
1621
1622 for (i = 0; i < 8; i++) {
1623 SpaprDrc *func_drc;
1624 SpaprDrcClass *func_drck;
1625 SpaprDREntitySense state;
1626
1627 func_drc = drc_from_devfn(phb, chassis, PCI_DEVFN(slotnr, i));
1628 func_drck = SPAPR_DR_CONNECTOR_GET_CLASS(func_drc);
1629 state = func_drck->dr_entity_sense(func_drc);
1630
1631 if (state == SPAPR_DR_ENTITY_SENSE_PRESENT) {
1632 spapr_hotplug_req_add_by_index(func_drc);
1633 }
1634 }
1635 }
1636}
1637
1638static void spapr_pci_bridge_unplug(SpaprPhbState *phb,
1639 PCIBridge *bridge)
1640{
1641 PCIBus *bus = pci_bridge_get_sec_bus(bridge);
1642
1643 remove_drcs(phb, bus);
1644}
1645
1646static void spapr_pci_unplug(HotplugHandler *plug_handler,
1647 DeviceState *plugged_dev, Error **errp)
1648{
1649 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(plugged_dev);
1650 SpaprPhbState *phb = SPAPR_PCI_HOST_BRIDGE(DEVICE(plug_handler));
1651
1652
1653
1654
1655
1656
1657
1658
1659
1660
1661
1662 pci_device_reset(PCI_DEVICE(plugged_dev));
1663
1664 if (pc->is_bridge) {
1665 spapr_pci_bridge_unplug(phb, PCI_BRIDGE(plugged_dev));
1666 return;
1667 }
1668
1669 qdev_unrealize(plugged_dev);
1670}
1671
1672static void spapr_pci_unplug_request(HotplugHandler *plug_handler,
1673 DeviceState *plugged_dev, Error **errp)
1674{
1675 SpaprPhbState *phb = SPAPR_PCI_HOST_BRIDGE(DEVICE(plug_handler));
1676 PCIDevice *pdev = PCI_DEVICE(plugged_dev);
1677 SpaprDrc *drc = drc_from_dev(phb, pdev);
1678
1679 if (!phb->dr_enabled) {
1680 error_setg(errp, QERR_BUS_NO_HOTPLUG,
1681 object_get_typename(OBJECT(phb)));
1682 return;
1683 }
1684
1685 g_assert(drc);
1686 g_assert(drc->dev == plugged_dev);
1687
1688 if (!spapr_drc_unplug_requested(drc)) {
1689 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(plugged_dev);
1690 uint32_t slotnr = PCI_SLOT(pdev->devfn);
1691 SpaprDrc *func_drc;
1692 SpaprDrcClass *func_drck;
1693 SpaprDREntitySense state;
1694 int i;
1695 uint8_t chassis = chassis_from_bus(pci_get_bus(pdev));
1696
1697 if (pc->is_bridge) {
1698 error_setg(errp, "PCI: Hot unplug of PCI bridges not supported");
1699 return;
1700 }
1701 if (object_property_get_uint(OBJECT(pdev), "nvlink2-tgt", NULL)) {
1702 error_setg(errp, "PCI: Cannot unplug NVLink2 devices");
1703 return;
1704 }
1705
1706
1707 if (PCI_FUNC(pdev->devfn) == 0) {
1708 for (i = 1; i < 8; i++) {
1709 func_drc = drc_from_devfn(phb, chassis, PCI_DEVFN(slotnr, i));
1710 func_drck = SPAPR_DR_CONNECTOR_GET_CLASS(func_drc);
1711 state = func_drck->dr_entity_sense(func_drc);
1712 if (state == SPAPR_DR_ENTITY_SENSE_PRESENT
1713 && !spapr_drc_unplug_requested(func_drc)) {
1714
1715
1716
1717
1718
1719
1720 spapr_drc_unplug_request(func_drc);
1721 }
1722 }
1723 }
1724
1725 spapr_drc_unplug_request(drc);
1726
1727
1728
1729
1730 if (PCI_FUNC(pdev->devfn) == 0) {
1731 for (i = 7; i >= 0; i--) {
1732 func_drc = drc_from_devfn(phb, chassis, PCI_DEVFN(slotnr, i));
1733 func_drck = SPAPR_DR_CONNECTOR_GET_CLASS(func_drc);
1734 state = func_drck->dr_entity_sense(func_drc);
1735 if (state == SPAPR_DR_ENTITY_SENSE_PRESENT) {
1736 spapr_hotplug_req_remove_by_index(func_drc);
1737 }
1738 }
1739 }
1740 } else {
1741 error_setg(errp,
1742 "PCI device unplug already in progress for device %s",
1743 drc->dev->id);
1744 }
1745}
1746
1747static void spapr_phb_finalizefn(Object *obj)
1748{
1749 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(obj);
1750
1751 g_free(sphb->dtbusname);
1752 sphb->dtbusname = NULL;
1753}
1754
1755static void spapr_phb_unrealize(DeviceState *dev)
1756{
1757 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
1758 SysBusDevice *s = SYS_BUS_DEVICE(dev);
1759 PCIHostState *phb = PCI_HOST_BRIDGE(s);
1760 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(phb);
1761 SpaprTceTable *tcet;
1762 int i;
1763 const unsigned windows_supported = spapr_phb_windows_supported(sphb);
1764
1765 spapr_phb_nvgpu_free(sphb);
1766
1767 if (sphb->msi) {
1768 g_hash_table_unref(sphb->msi);
1769 sphb->msi = NULL;
1770 }
1771
1772
1773
1774
1775
1776 for (i = windows_supported - 1; i >= 0; i--) {
1777 tcet = spapr_tce_find_by_liobn(sphb->dma_liobn[i]);
1778 if (tcet) {
1779 memory_region_del_subregion(&sphb->iommu_root,
1780 spapr_tce_get_iommu(tcet));
1781 }
1782 }
1783
1784 remove_drcs(sphb, phb->bus);
1785
1786 for (i = PCI_NUM_PINS - 1; i >= 0; i--) {
1787 if (sphb->lsi_table[i].irq) {
1788 spapr_irq_free(spapr, sphb->lsi_table[i].irq, 1);
1789 sphb->lsi_table[i].irq = 0;
1790 }
1791 }
1792
1793 QLIST_REMOVE(sphb, list);
1794
1795 memory_region_del_subregion(&sphb->iommu_root, &sphb->msiwindow);
1796
1797
1798
1799
1800
1801
1802 address_space_remove_listeners(&sphb->iommu_as);
1803 address_space_destroy(&sphb->iommu_as);
1804
1805 qbus_set_hotplug_handler(BUS(phb->bus), NULL);
1806 pci_unregister_root_bus(phb->bus);
1807
1808 memory_region_del_subregion(get_system_memory(), &sphb->iowindow);
1809 if (sphb->mem64_win_pciaddr != (hwaddr)-1) {
1810 memory_region_del_subregion(get_system_memory(), &sphb->mem64window);
1811 }
1812 memory_region_del_subregion(get_system_memory(), &sphb->mem32window);
1813}
1814
1815static void spapr_phb_destroy_msi(gpointer opaque)
1816{
1817 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
1818 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
1819 SpaprPciMsi *msi = opaque;
1820
1821 if (!smc->legacy_irq_allocation) {
1822 spapr_irq_msi_free(spapr, msi->first_irq, msi->num);
1823 }
1824 spapr_irq_free(spapr, msi->first_irq, msi->num);
1825 g_free(msi);
1826}
1827
1828static void spapr_phb_realize(DeviceState *dev, Error **errp)
1829{
1830 ERRP_GUARD();
1831
1832
1833
1834 SpaprMachineState *spapr =
1835 (SpaprMachineState *) object_dynamic_cast(qdev_get_machine(),
1836 TYPE_SPAPR_MACHINE);
1837 SpaprMachineClass *smc = spapr ? SPAPR_MACHINE_GET_CLASS(spapr) : NULL;
1838 SysBusDevice *s = SYS_BUS_DEVICE(dev);
1839 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(s);
1840 PCIHostState *phb = PCI_HOST_BRIDGE(s);
1841 MachineState *ms = MACHINE(spapr);
1842 char *namebuf;
1843 int i;
1844 PCIBus *bus;
1845 uint64_t msi_window_size = 4096;
1846 SpaprTceTable *tcet;
1847 const unsigned windows_supported = spapr_phb_windows_supported(sphb);
1848
1849 if (!spapr) {
1850 error_setg(errp, TYPE_SPAPR_PCI_HOST_BRIDGE " needs a pseries machine");
1851 return;
1852 }
1853
1854 assert(sphb->index != (uint32_t)-1);
1855
1856 if (sphb->mem64_win_size != 0) {
1857 if (sphb->mem_win_size > SPAPR_PCI_MEM32_WIN_SIZE) {
1858 error_setg(errp, "32-bit memory window of size 0x%"HWADDR_PRIx
1859 " (max 2 GiB)", sphb->mem_win_size);
1860 return;
1861 }
1862
1863
1864 sphb->mem64_win_pciaddr = sphb->mem64_win_addr;
1865 } else if (sphb->mem_win_size > SPAPR_PCI_MEM32_WIN_SIZE) {
1866
1867
1868
1869
1870
1871
1872
1873 sphb->mem64_win_size = sphb->mem_win_size - SPAPR_PCI_MEM32_WIN_SIZE;
1874 sphb->mem64_win_addr = sphb->mem_win_addr + SPAPR_PCI_MEM32_WIN_SIZE;
1875 sphb->mem64_win_pciaddr =
1876 SPAPR_PCI_MEM_WIN_BUS_OFFSET + SPAPR_PCI_MEM32_WIN_SIZE;
1877 sphb->mem_win_size = SPAPR_PCI_MEM32_WIN_SIZE;
1878 }
1879
1880 if (spapr_pci_find_phb(spapr, sphb->buid)) {
1881 SpaprPhbState *s;
1882
1883 error_setg(errp, "PCI host bridges must have unique indexes");
1884 error_append_hint(errp, "The following indexes are already in use:");
1885 QLIST_FOREACH(s, &spapr->phbs, list) {
1886 error_append_hint(errp, " %d", s->index);
1887 }
1888 error_append_hint(errp, "\nTry another value for the index property\n");
1889 return;
1890 }
1891
1892 if (sphb->numa_node != -1 &&
1893 (sphb->numa_node >= MAX_NODES ||
1894 !ms->numa_state->nodes[sphb->numa_node].present)) {
1895 error_setg(errp, "Invalid NUMA node ID for PCI host bridge");
1896 return;
1897 }
1898
1899 sphb->dtbusname = g_strdup_printf("pci@%" PRIx64, sphb->buid);
1900
1901
1902 namebuf = g_strdup_printf("%s.mmio", sphb->dtbusname);
1903 memory_region_init(&sphb->memspace, OBJECT(sphb), namebuf, UINT64_MAX);
1904 g_free(namebuf);
1905
1906 namebuf = g_strdup_printf("%s.mmio32-alias", sphb->dtbusname);
1907 memory_region_init_alias(&sphb->mem32window, OBJECT(sphb),
1908 namebuf, &sphb->memspace,
1909 SPAPR_PCI_MEM_WIN_BUS_OFFSET, sphb->mem_win_size);
1910 g_free(namebuf);
1911 memory_region_add_subregion(get_system_memory(), sphb->mem_win_addr,
1912 &sphb->mem32window);
1913
1914 if (sphb->mem64_win_size != 0) {
1915 namebuf = g_strdup_printf("%s.mmio64-alias", sphb->dtbusname);
1916 memory_region_init_alias(&sphb->mem64window, OBJECT(sphb),
1917 namebuf, &sphb->memspace,
1918 sphb->mem64_win_pciaddr, sphb->mem64_win_size);
1919 g_free(namebuf);
1920
1921 memory_region_add_subregion(get_system_memory(),
1922 sphb->mem64_win_addr,
1923 &sphb->mem64window);
1924 }
1925
1926
1927 namebuf = g_strdup_printf("%s.io", sphb->dtbusname);
1928 memory_region_init(&sphb->iospace, OBJECT(sphb),
1929 namebuf, SPAPR_PCI_IO_WIN_SIZE);
1930 g_free(namebuf);
1931
1932 namebuf = g_strdup_printf("%s.io-alias", sphb->dtbusname);
1933 memory_region_init_alias(&sphb->iowindow, OBJECT(sphb), namebuf,
1934 &sphb->iospace, 0, SPAPR_PCI_IO_WIN_SIZE);
1935 g_free(namebuf);
1936 memory_region_add_subregion(get_system_memory(), sphb->io_win_addr,
1937 &sphb->iowindow);
1938
1939 bus = pci_register_root_bus(dev, NULL,
1940 pci_spapr_set_irq, pci_swizzle_map_irq_fn, sphb,
1941 &sphb->memspace, &sphb->iospace,
1942 PCI_DEVFN(0, 0), PCI_NUM_PINS,
1943 TYPE_PCI_BUS);
1944
1945
1946
1947
1948
1949
1950 if (sphb->pcie_ecs) {
1951 bus->flags |= PCI_BUS_EXTENDED_CONFIG_SPACE;
1952 }
1953 phb->bus = bus;
1954 qbus_set_hotplug_handler(BUS(phb->bus), OBJECT(sphb));
1955
1956
1957
1958
1959
1960
1961
1962
1963 namebuf = g_strdup_printf("%s.iommu-root", sphb->dtbusname);
1964 memory_region_init(&sphb->iommu_root, OBJECT(sphb),
1965 namebuf, UINT64_MAX);
1966 g_free(namebuf);
1967 address_space_init(&sphb->iommu_as, &sphb->iommu_root,
1968 sphb->dtbusname);
1969
1970
1971
1972
1973
1974
1975
1976
1977
1978
1979
1980
1981 if (kvm_enabled()) {
1982 msi_window_size = qemu_real_host_page_size();
1983 }
1984
1985 memory_region_init_io(&sphb->msiwindow, OBJECT(sphb), &spapr_msi_ops, spapr,
1986 "msi", msi_window_size);
1987 memory_region_add_subregion(&sphb->iommu_root, SPAPR_PCI_MSI_WINDOW,
1988 &sphb->msiwindow);
1989
1990 pci_setup_iommu(bus, spapr_pci_dma_iommu, sphb);
1991
1992 pci_bus_set_route_irq_fn(bus, spapr_route_intx_pin_to_irq);
1993
1994 QLIST_INSERT_HEAD(&spapr->phbs, sphb, list);
1995
1996
1997 for (i = 0; i < PCI_NUM_PINS; i++) {
1998 int irq = SPAPR_IRQ_PCI_LSI + sphb->index * PCI_NUM_PINS + i;
1999
2000 if (smc->legacy_irq_allocation) {
2001 irq = spapr_irq_findone(spapr, errp);
2002 if (irq < 0) {
2003 error_prepend(errp, "can't allocate LSIs: ");
2004
2005
2006
2007
2008 return;
2009 }
2010 }
2011
2012 if (spapr_irq_claim(spapr, irq, true, errp) < 0) {
2013 error_prepend(errp, "can't allocate LSIs: ");
2014 goto unrealize;
2015 }
2016
2017 sphb->lsi_table[i].irq = irq;
2018 }
2019
2020
2021 add_drcs(sphb, phb->bus);
2022
2023
2024 for (i = 0; i < windows_supported; ++i) {
2025 tcet = spapr_tce_new_table(DEVICE(sphb), sphb->dma_liobn[i]);
2026 if (!tcet) {
2027 error_setg(errp, "Creating window#%d failed for %s",
2028 i, sphb->dtbusname);
2029 goto unrealize;
2030 }
2031 memory_region_add_subregion(&sphb->iommu_root, 0,
2032 spapr_tce_get_iommu(tcet));
2033 }
2034
2035 sphb->msi = g_hash_table_new_full(g_int_hash, g_int_equal, g_free,
2036 spapr_phb_destroy_msi);
2037 return;
2038
2039unrealize:
2040 spapr_phb_unrealize(dev);
2041}
2042
2043static int spapr_phb_children_reset(Object *child, void *opaque)
2044{
2045 DeviceState *dev = (DeviceState *) object_dynamic_cast(child, TYPE_DEVICE);
2046
2047 if (dev) {
2048 device_cold_reset(dev);
2049 }
2050
2051 return 0;
2052}
2053
2054void spapr_phb_dma_reset(SpaprPhbState *sphb)
2055{
2056 int i;
2057 SpaprTceTable *tcet;
2058
2059 for (i = 0; i < SPAPR_PCI_DMA_MAX_WINDOWS; ++i) {
2060 tcet = spapr_tce_find_by_liobn(sphb->dma_liobn[i]);
2061
2062 if (tcet && tcet->nb_table) {
2063 spapr_tce_table_disable(tcet);
2064 }
2065 }
2066
2067
2068 tcet = spapr_tce_find_by_liobn(sphb->dma_liobn[0]);
2069 spapr_tce_table_enable(tcet, SPAPR_TCE_PAGE_SHIFT, sphb->dma_win_addr,
2070 sphb->dma_win_size >> SPAPR_TCE_PAGE_SHIFT);
2071 tcet->def_win = true;
2072}
2073
2074static void spapr_phb_reset(DeviceState *qdev)
2075{
2076 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(qdev);
2077 Error *err = NULL;
2078
2079 spapr_phb_dma_reset(sphb);
2080 spapr_phb_nvgpu_free(sphb);
2081 spapr_phb_nvgpu_setup(sphb, &err);
2082 if (err) {
2083 error_report_err(err);
2084 }
2085
2086
2087 object_child_foreach(OBJECT(qdev), spapr_phb_children_reset, NULL);
2088
2089 if (spapr_phb_eeh_available(SPAPR_PCI_HOST_BRIDGE(qdev))) {
2090 spapr_phb_vfio_reset(qdev);
2091 }
2092
2093 g_hash_table_remove_all(sphb->msi);
2094}
2095
2096static Property spapr_phb_properties[] = {
2097 DEFINE_PROP_UINT32("index", SpaprPhbState, index, -1),
2098 DEFINE_PROP_UINT64("mem_win_size", SpaprPhbState, mem_win_size,
2099 SPAPR_PCI_MEM32_WIN_SIZE),
2100 DEFINE_PROP_UINT64("mem64_win_size", SpaprPhbState, mem64_win_size,
2101 SPAPR_PCI_MEM64_WIN_SIZE),
2102 DEFINE_PROP_UINT64("io_win_size", SpaprPhbState, io_win_size,
2103 SPAPR_PCI_IO_WIN_SIZE),
2104 DEFINE_PROP_BOOL("dynamic-reconfiguration", SpaprPhbState, dr_enabled,
2105 true),
2106
2107 DEFINE_PROP_UINT64("dma_win_addr", SpaprPhbState, dma_win_addr, 0),
2108 DEFINE_PROP_UINT64("dma_win_size", SpaprPhbState, dma_win_size, 0x40000000),
2109 DEFINE_PROP_UINT64("dma64_win_addr", SpaprPhbState, dma64_win_addr,
2110 0x800000000000000ULL),
2111 DEFINE_PROP_BOOL("ddw", SpaprPhbState, ddw_enabled, true),
2112 DEFINE_PROP_UINT64("pgsz", SpaprPhbState, page_size_mask,
2113 (1ULL << 12) | (1ULL << 16)
2114 | (1ULL << 21) | (1ULL << 24)),
2115 DEFINE_PROP_UINT32("numa_node", SpaprPhbState, numa_node, -1),
2116 DEFINE_PROP_BOOL("pre-2.8-migration", SpaprPhbState,
2117 pre_2_8_migration, false),
2118 DEFINE_PROP_BOOL("pcie-extended-configuration-space", SpaprPhbState,
2119 pcie_ecs, true),
2120 DEFINE_PROP_UINT64("gpa", SpaprPhbState, nv2_gpa_win_addr, 0),
2121 DEFINE_PROP_UINT64("atsd", SpaprPhbState, nv2_atsd_win_addr, 0),
2122 DEFINE_PROP_BOOL("pre-5.1-associativity", SpaprPhbState,
2123 pre_5_1_assoc, false),
2124 DEFINE_PROP_END_OF_LIST(),
2125};
2126
2127static const VMStateDescription vmstate_spapr_pci_lsi = {
2128 .name = "spapr_pci/lsi",
2129 .version_id = 1,
2130 .minimum_version_id = 1,
2131 .fields = (VMStateField[]) {
2132 VMSTATE_UINT32_EQUAL(irq, SpaprPciLsi, NULL),
2133
2134 VMSTATE_END_OF_LIST()
2135 },
2136};
2137
2138static const VMStateDescription vmstate_spapr_pci_msi = {
2139 .name = "spapr_pci/msi",
2140 .version_id = 1,
2141 .minimum_version_id = 1,
2142 .fields = (VMStateField []) {
2143 VMSTATE_UINT32(key, SpaprPciMsiMig),
2144 VMSTATE_UINT32(value.first_irq, SpaprPciMsiMig),
2145 VMSTATE_UINT32(value.num, SpaprPciMsiMig),
2146 VMSTATE_END_OF_LIST()
2147 },
2148};
2149
2150static int spapr_pci_pre_save(void *opaque)
2151{
2152 SpaprPhbState *sphb = opaque;
2153 GHashTableIter iter;
2154 gpointer key, value;
2155 int i;
2156
2157 if (sphb->pre_2_8_migration) {
2158 sphb->mig_liobn = sphb->dma_liobn[0];
2159 sphb->mig_mem_win_addr = sphb->mem_win_addr;
2160 sphb->mig_mem_win_size = sphb->mem_win_size;
2161 sphb->mig_io_win_addr = sphb->io_win_addr;
2162 sphb->mig_io_win_size = sphb->io_win_size;
2163
2164 if ((sphb->mem64_win_size != 0)
2165 && (sphb->mem64_win_addr
2166 == (sphb->mem_win_addr + sphb->mem_win_size))) {
2167 sphb->mig_mem_win_size += sphb->mem64_win_size;
2168 }
2169 }
2170
2171 g_free(sphb->msi_devs);
2172 sphb->msi_devs = NULL;
2173 sphb->msi_devs_num = g_hash_table_size(sphb->msi);
2174 if (!sphb->msi_devs_num) {
2175 return 0;
2176 }
2177 sphb->msi_devs = g_new(SpaprPciMsiMig, sphb->msi_devs_num);
2178
2179 g_hash_table_iter_init(&iter, sphb->msi);
2180 for (i = 0; g_hash_table_iter_next(&iter, &key, &value); ++i) {
2181 sphb->msi_devs[i].key = *(uint32_t *) key;
2182 sphb->msi_devs[i].value = *(SpaprPciMsi *) value;
2183 }
2184
2185 return 0;
2186}
2187
2188static int spapr_pci_post_save(void *opaque)
2189{
2190 SpaprPhbState *sphb = opaque;
2191
2192 g_free(sphb->msi_devs);
2193 sphb->msi_devs = NULL;
2194 sphb->msi_devs_num = 0;
2195 return 0;
2196}
2197
2198static int spapr_pci_post_load(void *opaque, int version_id)
2199{
2200 SpaprPhbState *sphb = opaque;
2201 gpointer key, value;
2202 int i;
2203
2204 for (i = 0; i < sphb->msi_devs_num; ++i) {
2205 key = g_memdup(&sphb->msi_devs[i].key,
2206 sizeof(sphb->msi_devs[i].key));
2207 value = g_memdup(&sphb->msi_devs[i].value,
2208 sizeof(sphb->msi_devs[i].value));
2209 g_hash_table_insert(sphb->msi, key, value);
2210 }
2211 g_free(sphb->msi_devs);
2212 sphb->msi_devs = NULL;
2213 sphb->msi_devs_num = 0;
2214
2215 return 0;
2216}
2217
2218static bool pre_2_8_migration(void *opaque, int version_id)
2219{
2220 SpaprPhbState *sphb = opaque;
2221
2222 return sphb->pre_2_8_migration;
2223}
2224
2225static const VMStateDescription vmstate_spapr_pci = {
2226 .name = "spapr_pci",
2227 .version_id = 2,
2228 .minimum_version_id = 2,
2229 .pre_save = spapr_pci_pre_save,
2230 .post_save = spapr_pci_post_save,
2231 .post_load = spapr_pci_post_load,
2232 .fields = (VMStateField[]) {
2233 VMSTATE_UINT64_EQUAL(buid, SpaprPhbState, NULL),
2234 VMSTATE_UINT32_TEST(mig_liobn, SpaprPhbState, pre_2_8_migration),
2235 VMSTATE_UINT64_TEST(mig_mem_win_addr, SpaprPhbState, pre_2_8_migration),
2236 VMSTATE_UINT64_TEST(mig_mem_win_size, SpaprPhbState, pre_2_8_migration),
2237 VMSTATE_UINT64_TEST(mig_io_win_addr, SpaprPhbState, pre_2_8_migration),
2238 VMSTATE_UINT64_TEST(mig_io_win_size, SpaprPhbState, pre_2_8_migration),
2239 VMSTATE_STRUCT_ARRAY(lsi_table, SpaprPhbState, PCI_NUM_PINS, 0,
2240 vmstate_spapr_pci_lsi, SpaprPciLsi),
2241 VMSTATE_INT32(msi_devs_num, SpaprPhbState),
2242 VMSTATE_STRUCT_VARRAY_ALLOC(msi_devs, SpaprPhbState, msi_devs_num, 0,
2243 vmstate_spapr_pci_msi, SpaprPciMsiMig),
2244 VMSTATE_END_OF_LIST()
2245 },
2246};
2247
2248static const char *spapr_phb_root_bus_path(PCIHostState *host_bridge,
2249 PCIBus *rootbus)
2250{
2251 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(host_bridge);
2252
2253 return sphb->dtbusname;
2254}
2255
2256static void spapr_phb_class_init(ObjectClass *klass, void *data)
2257{
2258 PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass);
2259 DeviceClass *dc = DEVICE_CLASS(klass);
2260 HotplugHandlerClass *hp = HOTPLUG_HANDLER_CLASS(klass);
2261
2262 hc->root_bus_path = spapr_phb_root_bus_path;
2263 dc->realize = spapr_phb_realize;
2264 dc->unrealize = spapr_phb_unrealize;
2265 device_class_set_props(dc, spapr_phb_properties);
2266 dc->reset = spapr_phb_reset;
2267 dc->vmsd = &vmstate_spapr_pci;
2268
2269 dc->user_creatable = true;
2270 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
2271 hp->pre_plug = spapr_pci_pre_plug;
2272 hp->plug = spapr_pci_plug;
2273 hp->unplug = spapr_pci_unplug;
2274 hp->unplug_request = spapr_pci_unplug_request;
2275}
2276
2277static const TypeInfo spapr_phb_info = {
2278 .name = TYPE_SPAPR_PCI_HOST_BRIDGE,
2279 .parent = TYPE_PCI_HOST_BRIDGE,
2280 .instance_size = sizeof(SpaprPhbState),
2281 .instance_finalize = spapr_phb_finalizefn,
2282 .class_init = spapr_phb_class_init,
2283 .interfaces = (InterfaceInfo[]) {
2284 { TYPE_HOTPLUG_HANDLER },
2285 { }
2286 }
2287};
2288
2289static void spapr_phb_pci_enumerate_bridge(PCIBus *bus, PCIDevice *pdev,
2290 void *opaque)
2291{
2292 unsigned int *bus_no = opaque;
2293 PCIBus *sec_bus = NULL;
2294
2295 if ((pci_default_read_config(pdev, PCI_HEADER_TYPE, 1) !=
2296 PCI_HEADER_TYPE_BRIDGE)) {
2297 return;
2298 }
2299
2300 (*bus_no)++;
2301 pci_default_write_config(pdev, PCI_PRIMARY_BUS, pci_dev_bus_num(pdev), 1);
2302 pci_default_write_config(pdev, PCI_SECONDARY_BUS, *bus_no, 1);
2303 pci_default_write_config(pdev, PCI_SUBORDINATE_BUS, *bus_no, 1);
2304
2305 sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(pdev));
2306 if (!sec_bus) {
2307 return;
2308 }
2309
2310 pci_for_each_device_under_bus(sec_bus, spapr_phb_pci_enumerate_bridge,
2311 bus_no);
2312 pci_default_write_config(pdev, PCI_SUBORDINATE_BUS, *bus_no, 1);
2313}
2314
2315static void spapr_phb_pci_enumerate(SpaprPhbState *phb)
2316{
2317 PCIBus *bus = PCI_HOST_BRIDGE(phb)->bus;
2318 unsigned int bus_no = 0;
2319
2320 pci_for_each_device_under_bus(bus, spapr_phb_pci_enumerate_bridge,
2321 &bus_no);
2322
2323}
2324
2325int spapr_dt_phb(SpaprMachineState *spapr, SpaprPhbState *phb,
2326 uint32_t intc_phandle, void *fdt, int *node_offset)
2327{
2328 int bus_off, i, j, ret;
2329 uint32_t bus_range[] = { cpu_to_be32(0), cpu_to_be32(0xff) };
2330 struct {
2331 uint32_t hi;
2332 uint64_t child;
2333 uint64_t parent;
2334 uint64_t size;
2335 } QEMU_PACKED ranges[] = {
2336 {
2337 cpu_to_be32(b_ss(1)), cpu_to_be64(0),
2338 cpu_to_be64(phb->io_win_addr),
2339 cpu_to_be64(memory_region_size(&phb->iospace)),
2340 },
2341 {
2342 cpu_to_be32(b_ss(2)), cpu_to_be64(SPAPR_PCI_MEM_WIN_BUS_OFFSET),
2343 cpu_to_be64(phb->mem_win_addr),
2344 cpu_to_be64(phb->mem_win_size),
2345 },
2346 {
2347 cpu_to_be32(b_ss(3)), cpu_to_be64(phb->mem64_win_pciaddr),
2348 cpu_to_be64(phb->mem64_win_addr),
2349 cpu_to_be64(phb->mem64_win_size),
2350 },
2351 };
2352 const unsigned sizeof_ranges =
2353 (phb->mem64_win_size ? 3 : 2) * sizeof(ranges[0]);
2354 uint64_t bus_reg[] = { cpu_to_be64(phb->buid), 0 };
2355 uint32_t interrupt_map_mask[] = {
2356 cpu_to_be32(b_ddddd(-1)|b_fff(0)), 0x0, 0x0, cpu_to_be32(-1)};
2357 uint32_t interrupt_map[PCI_SLOT_MAX * PCI_NUM_PINS][7];
2358 uint32_t ddw_applicable[] = {
2359 cpu_to_be32(RTAS_IBM_QUERY_PE_DMA_WINDOW),
2360 cpu_to_be32(RTAS_IBM_CREATE_PE_DMA_WINDOW),
2361 cpu_to_be32(RTAS_IBM_REMOVE_PE_DMA_WINDOW)
2362 };
2363 uint32_t ddw_extensions[] = {
2364 cpu_to_be32(2),
2365 cpu_to_be32(RTAS_IBM_RESET_PE_DMA_WINDOW),
2366 cpu_to_be32(1),
2367 };
2368 SpaprTceTable *tcet;
2369 SpaprDrc *drc;
2370 Error *err = NULL;
2371
2372
2373 _FDT(bus_off = fdt_add_subnode(fdt, 0, phb->dtbusname));
2374 if (node_offset) {
2375 *node_offset = bus_off;
2376 }
2377
2378
2379 _FDT(fdt_setprop_string(fdt, bus_off, "device_type", "pci"));
2380 _FDT(fdt_setprop_string(fdt, bus_off, "compatible", "IBM,Logical_PHB"));
2381 _FDT(fdt_setprop_cell(fdt, bus_off, "#interrupt-cells", 0x1));
2382 _FDT(fdt_setprop(fdt, bus_off, "used-by-rtas", NULL, 0));
2383 _FDT(fdt_setprop(fdt, bus_off, "bus-range", &bus_range, sizeof(bus_range)));
2384 _FDT(fdt_setprop(fdt, bus_off, "ranges", &ranges, sizeof_ranges));
2385 _FDT(fdt_setprop(fdt, bus_off, "reg", &bus_reg, sizeof(bus_reg)));
2386 _FDT(fdt_setprop_cell(fdt, bus_off, "ibm,pci-config-space-type", 0x1));
2387 _FDT(fdt_setprop_cell(fdt, bus_off, "ibm,pe-total-#msi",
2388 spapr_irq_nr_msis(spapr)));
2389
2390
2391 if (phb->ddw_enabled) {
2392 _FDT(fdt_setprop(fdt, bus_off, "ibm,ddw-applicable", &ddw_applicable,
2393 sizeof(ddw_applicable)));
2394 _FDT(fdt_setprop(fdt, bus_off, "ibm,ddw-extensions",
2395 &ddw_extensions, sizeof(ddw_extensions)));
2396 }
2397
2398
2399 if (phb->numa_node != -1) {
2400 spapr_numa_write_associativity_dt(spapr, fdt, bus_off, phb->numa_node);
2401 }
2402
2403
2404
2405
2406 _FDT(fdt_setprop(fdt, bus_off, "interrupt-map-mask",
2407 &interrupt_map_mask, sizeof(interrupt_map_mask)));
2408 for (i = 0; i < PCI_SLOT_MAX; i++) {
2409 for (j = 0; j < PCI_NUM_PINS; j++) {
2410 uint32_t *irqmap = interrupt_map[i*PCI_NUM_PINS + j];
2411 int lsi_num = pci_swizzle(i, j);
2412
2413 irqmap[0] = cpu_to_be32(b_ddddd(i)|b_fff(0));
2414 irqmap[1] = 0;
2415 irqmap[2] = 0;
2416 irqmap[3] = cpu_to_be32(j+1);
2417 irqmap[4] = cpu_to_be32(intc_phandle);
2418 spapr_dt_irq(&irqmap[5], phb->lsi_table[lsi_num].irq, true);
2419 }
2420 }
2421
2422 _FDT(fdt_setprop(fdt, bus_off, "interrupt-map", &interrupt_map,
2423 sizeof(interrupt_map)));
2424
2425 tcet = spapr_tce_find_by_liobn(phb->dma_liobn[0]);
2426 if (!tcet) {
2427 return -1;
2428 }
2429 spapr_dma_dt(fdt, bus_off, "ibm,dma-window",
2430 tcet->liobn, tcet->bus_offset,
2431 tcet->nb_table << tcet->page_shift);
2432
2433 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, phb->index);
2434 if (drc) {
2435 uint32_t drc_index = cpu_to_be32(spapr_drc_index(drc));
2436
2437 _FDT(fdt_setprop(fdt, bus_off, "ibm,my-drc-index", &drc_index,
2438 sizeof(drc_index)));
2439 }
2440
2441
2442 spapr_phb_pci_enumerate(phb);
2443 _FDT(fdt_setprop_cell(fdt, bus_off, "qemu,phb-enumerated", 0x1));
2444
2445
2446 ret = spapr_dt_pci_bus(phb, PCI_HOST_BRIDGE(phb)->bus, fdt, bus_off);
2447 if (ret < 0) {
2448 return ret;
2449 }
2450
2451 spapr_phb_nvgpu_populate_dt(phb, fdt, bus_off, &err);
2452 if (err) {
2453 error_report_err(err);
2454 }
2455 spapr_phb_nvgpu_ram_populate_dt(phb, fdt);
2456
2457 return 0;
2458}
2459
2460void spapr_pci_rtas_init(void)
2461{
2462 spapr_rtas_register(RTAS_READ_PCI_CONFIG, "read-pci-config",
2463 rtas_read_pci_config);
2464 spapr_rtas_register(RTAS_WRITE_PCI_CONFIG, "write-pci-config",
2465 rtas_write_pci_config);
2466 spapr_rtas_register(RTAS_IBM_READ_PCI_CONFIG, "ibm,read-pci-config",
2467 rtas_ibm_read_pci_config);
2468 spapr_rtas_register(RTAS_IBM_WRITE_PCI_CONFIG, "ibm,write-pci-config",
2469 rtas_ibm_write_pci_config);
2470 if (msi_nonbroken) {
2471 spapr_rtas_register(RTAS_IBM_QUERY_INTERRUPT_SOURCE_NUMBER,
2472 "ibm,query-interrupt-source-number",
2473 rtas_ibm_query_interrupt_source_number);
2474 spapr_rtas_register(RTAS_IBM_CHANGE_MSI, "ibm,change-msi",
2475 rtas_ibm_change_msi);
2476 }
2477
2478 spapr_rtas_register(RTAS_IBM_SET_EEH_OPTION,
2479 "ibm,set-eeh-option",
2480 rtas_ibm_set_eeh_option);
2481 spapr_rtas_register(RTAS_IBM_GET_CONFIG_ADDR_INFO2,
2482 "ibm,get-config-addr-info2",
2483 rtas_ibm_get_config_addr_info2);
2484 spapr_rtas_register(RTAS_IBM_READ_SLOT_RESET_STATE2,
2485 "ibm,read-slot-reset-state2",
2486 rtas_ibm_read_slot_reset_state2);
2487 spapr_rtas_register(RTAS_IBM_SET_SLOT_RESET,
2488 "ibm,set-slot-reset",
2489 rtas_ibm_set_slot_reset);
2490 spapr_rtas_register(RTAS_IBM_CONFIGURE_PE,
2491 "ibm,configure-pe",
2492 rtas_ibm_configure_pe);
2493 spapr_rtas_register(RTAS_IBM_SLOT_ERROR_DETAIL,
2494 "ibm,slot-error-detail",
2495 rtas_ibm_slot_error_detail);
2496}
2497
2498static void spapr_pci_register_types(void)
2499{
2500 type_register_static(&spapr_phb_info);
2501}
2502
2503type_init(spapr_pci_register_types)
2504
2505static int spapr_switch_one_vga(DeviceState *dev, void *opaque)
2506{
2507 bool be = *(bool *)opaque;
2508
2509 if (object_dynamic_cast(OBJECT(dev), "VGA")
2510 || object_dynamic_cast(OBJECT(dev), "secondary-vga")
2511 || object_dynamic_cast(OBJECT(dev), "bochs-display")
2512 || object_dynamic_cast(OBJECT(dev), "virtio-vga")) {
2513 object_property_set_bool(OBJECT(dev), "big-endian-framebuffer", be,
2514 &error_abort);
2515 }
2516 return 0;
2517}
2518
2519void spapr_pci_switch_vga(SpaprMachineState *spapr, bool big_endian)
2520{
2521 SpaprPhbState *sphb;
2522
2523
2524
2525
2526
2527
2528 QLIST_FOREACH(sphb, &spapr->phbs, list) {
2529 BusState *bus = &PCI_HOST_BRIDGE(sphb)->bus->qbus;
2530 qbus_walk_children(bus, spapr_switch_one_vga, NULL, NULL, NULL,
2531 &big_endian);
2532 }
2533}
2534