LXR qemu/target/arm/common-semi-target.h

   1/*
   2 * Target-specific parts of semihosting/arm-compat-semi.c.
   3 *
   4 * Copyright (c) 2005, 2007 CodeSourcery.
   5 * Copyright (c) 2019, 2022 Linaro
   6 *
   7 * SPDX-License-Identifier: GPL-2.0-or-later
   8 */
   9
  10#ifndef TARGET_ARM_COMMON_SEMI_TARGET_H
  11#define TARGET_ARM_COMMON_SEMI_TARGET_H
  12
  13#ifndef CONFIG_USER_ONLY
  14#include "hw/arm/boot.h"
  15#endif
  16
  17static inline target_ulong common_semi_arg(CPUState *cs, int argno)
  18{
  19    ARMCPU *cpu = ARM_CPU(cs);
  20    CPUARMState *env = &cpu->env;
  21    if (is_a64(env)) {
  22        return env->xregs[argno];
  23    } else {
  24        return env->regs[argno];
  25    }
  26}
  27
  28static inline void common_semi_set_ret(CPUState *cs, target_ulong ret)
  29{
  30    ARMCPU *cpu = ARM_CPU(cs);
  31    CPUARMState *env = &cpu->env;
  32    if (is_a64(env)) {
  33        env->xregs[0] = ret;
  34    } else {
  35        env->regs[0] = ret;
  36    }
  37}
  38
  39static inline bool common_semi_sys_exit_extended(CPUState *cs, int nr)
  40{
  41    return (nr == TARGET_SYS_EXIT_EXTENDED || is_a64(cs->env_ptr));
  42}
  43
  44static inline bool is_64bit_semihosting(CPUArchState *env)
  45{
  46    return is_a64(env);
  47}
  48
  49static inline target_ulong common_semi_stack_bottom(CPUState *cs)
  50{
  51    ARMCPU *cpu = ARM_CPU(cs);
  52    CPUARMState *env = &cpu->env;
  53    return is_a64(env) ? env->xregs[31] : env->regs[13];
  54}
  55
  56static inline bool common_semi_has_synccache(CPUArchState *env)
  57{
  58    /* Ok for A64, invalid for A32/T32 */
  59    return is_a64(env);
  60}
  61
  62#endif
  63