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20#include "qemu/osdep.h"
21#include "qapi/error.h"
22#include "qemu/qemu-print.h"
23#include "cpu.h"
24#include "exec/exec-all.h"
25
26static void openrisc_cpu_set_pc(CPUState *cs, vaddr value)
27{
28 OpenRISCCPU *cpu = OPENRISC_CPU(cs);
29
30 cpu->env.pc = value;
31 cpu->env.dflag = 0;
32}
33
34static vaddr openrisc_cpu_get_pc(CPUState *cs)
35{
36 OpenRISCCPU *cpu = OPENRISC_CPU(cs);
37
38 return cpu->env.pc;
39}
40
41static void openrisc_cpu_synchronize_from_tb(CPUState *cs,
42 const TranslationBlock *tb)
43{
44 OpenRISCCPU *cpu = OPENRISC_CPU(cs);
45
46 cpu->env.pc = tb_pc(tb);
47}
48
49static void openrisc_restore_state_to_opc(CPUState *cs,
50 const TranslationBlock *tb,
51 const uint64_t *data)
52{
53 OpenRISCCPU *cpu = OPENRISC_CPU(cs);
54
55 cpu->env.pc = data[0];
56 cpu->env.dflag = data[1] & 1;
57 if (data[1] & 2) {
58 cpu->env.ppc = cpu->env.pc - 4;
59 }
60}
61
62static bool openrisc_cpu_has_work(CPUState *cs)
63{
64 return cs->interrupt_request & (CPU_INTERRUPT_HARD |
65 CPU_INTERRUPT_TIMER);
66}
67
68static void openrisc_disas_set_info(CPUState *cpu, disassemble_info *info)
69{
70 info->print_insn = print_insn_or1k;
71}
72
73static void openrisc_cpu_reset(DeviceState *dev)
74{
75 CPUState *s = CPU(dev);
76 OpenRISCCPU *cpu = OPENRISC_CPU(s);
77 OpenRISCCPUClass *occ = OPENRISC_CPU_GET_CLASS(cpu);
78
79 occ->parent_reset(dev);
80
81 memset(&cpu->env, 0, offsetof(CPUOpenRISCState, end_reset_fields));
82
83 cpu->env.pc = 0x100;
84 cpu->env.sr = SR_FO | SR_SM;
85 cpu->env.lock_addr = -1;
86 s->exception_index = -1;
87 cpu_set_fpcsr(&cpu->env, 0);
88
89#ifndef CONFIG_USER_ONLY
90 cpu->env.picmr = 0x00000000;
91 cpu->env.picsr = 0x00000000;
92
93 cpu->env.ttmr = 0x00000000;
94#endif
95}
96
97#ifndef CONFIG_USER_ONLY
98static void openrisc_cpu_set_irq(void *opaque, int irq, int level)
99{
100 OpenRISCCPU *cpu = (OpenRISCCPU *)opaque;
101 CPUState *cs = CPU(cpu);
102 uint32_t irq_bit;
103
104 if (irq > 31 || irq < 0) {
105 return;
106 }
107
108 irq_bit = 1U << irq;
109
110 if (level) {
111 cpu->env.picsr |= irq_bit;
112 } else {
113 cpu->env.picsr &= ~irq_bit;
114 }
115
116 if (cpu->env.picsr & cpu->env.picmr) {
117 cpu_interrupt(cs, CPU_INTERRUPT_HARD);
118 } else {
119 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
120 }
121}
122#endif
123
124static void openrisc_cpu_realizefn(DeviceState *dev, Error **errp)
125{
126 CPUState *cs = CPU(dev);
127 OpenRISCCPUClass *occ = OPENRISC_CPU_GET_CLASS(dev);
128 Error *local_err = NULL;
129
130 cpu_exec_realizefn(cs, &local_err);
131 if (local_err != NULL) {
132 error_propagate(errp, local_err);
133 return;
134 }
135
136 qemu_init_vcpu(cs);
137 cpu_reset(cs);
138
139 occ->parent_realize(dev, errp);
140}
141
142static void openrisc_cpu_initfn(Object *obj)
143{
144 OpenRISCCPU *cpu = OPENRISC_CPU(obj);
145
146 cpu_set_cpustate_pointers(cpu);
147
148#ifndef CONFIG_USER_ONLY
149 qdev_init_gpio_in_named(DEVICE(cpu), openrisc_cpu_set_irq, "IRQ", NR_IRQS);
150#endif
151}
152
153
154
155static ObjectClass *openrisc_cpu_class_by_name(const char *cpu_model)
156{
157 ObjectClass *oc;
158 char *typename;
159
160 typename = g_strdup_printf(OPENRISC_CPU_TYPE_NAME("%s"), cpu_model);
161 oc = object_class_by_name(typename);
162 g_free(typename);
163 if (oc != NULL && (!object_class_dynamic_cast(oc, TYPE_OPENRISC_CPU) ||
164 object_class_is_abstract(oc))) {
165 return NULL;
166 }
167 return oc;
168}
169
170static void or1200_initfn(Object *obj)
171{
172 OpenRISCCPU *cpu = OPENRISC_CPU(obj);
173
174 cpu->env.vr = 0x13000008;
175 cpu->env.upr = UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP | UPR_PMP;
176 cpu->env.cpucfgr = CPUCFGR_NSGF | CPUCFGR_OB32S | CPUCFGR_OF32S |
177 CPUCFGR_EVBARP;
178
179
180 cpu->env.dmmucfgr = (DMMUCFGR_NTW & (0 << 2))
181 | (DMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2));
182 cpu->env.immucfgr = (IMMUCFGR_NTW & (0 << 2))
183 | (IMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2));
184}
185
186static void openrisc_any_initfn(Object *obj)
187{
188 OpenRISCCPU *cpu = OPENRISC_CPU(obj);
189
190 cpu->env.vr = 0x13000040;
191 cpu->env.vr2 = 0;
192 cpu->env.avr = 0x01030000;
193
194 cpu->env.upr = UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP | UPR_PMP;
195 cpu->env.cpucfgr = CPUCFGR_NSGF | CPUCFGR_OB32S | CPUCFGR_OF32S |
196 CPUCFGR_AVRP | CPUCFGR_EVBARP | CPUCFGR_OF64A32S;
197
198
199 cpu->env.dmmucfgr = (DMMUCFGR_NTW & (0 << 2))
200 | (DMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2));
201 cpu->env.immucfgr = (IMMUCFGR_NTW & (0 << 2))
202 | (IMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2));
203}
204
205#ifndef CONFIG_USER_ONLY
206#include "hw/core/sysemu-cpu-ops.h"
207
208static const struct SysemuCPUOps openrisc_sysemu_ops = {
209 .get_phys_page_debug = openrisc_cpu_get_phys_page_debug,
210};
211#endif
212
213#include "hw/core/tcg-cpu-ops.h"
214
215static const struct TCGCPUOps openrisc_tcg_ops = {
216 .initialize = openrisc_translate_init,
217 .synchronize_from_tb = openrisc_cpu_synchronize_from_tb,
218 .restore_state_to_opc = openrisc_restore_state_to_opc,
219
220#ifndef CONFIG_USER_ONLY
221 .tlb_fill = openrisc_cpu_tlb_fill,
222 .cpu_exec_interrupt = openrisc_cpu_exec_interrupt,
223 .do_interrupt = openrisc_cpu_do_interrupt,
224#endif
225};
226
227static void openrisc_cpu_class_init(ObjectClass *oc, void *data)
228{
229 OpenRISCCPUClass *occ = OPENRISC_CPU_CLASS(oc);
230 CPUClass *cc = CPU_CLASS(occ);
231 DeviceClass *dc = DEVICE_CLASS(oc);
232
233 device_class_set_parent_realize(dc, openrisc_cpu_realizefn,
234 &occ->parent_realize);
235 device_class_set_parent_reset(dc, openrisc_cpu_reset, &occ->parent_reset);
236
237 cc->class_by_name = openrisc_cpu_class_by_name;
238 cc->has_work = openrisc_cpu_has_work;
239 cc->dump_state = openrisc_cpu_dump_state;
240 cc->set_pc = openrisc_cpu_set_pc;
241 cc->get_pc = openrisc_cpu_get_pc;
242 cc->gdb_read_register = openrisc_cpu_gdb_read_register;
243 cc->gdb_write_register = openrisc_cpu_gdb_write_register;
244#ifndef CONFIG_USER_ONLY
245 dc->vmsd = &vmstate_openrisc_cpu;
246 cc->sysemu_ops = &openrisc_sysemu_ops;
247#endif
248 cc->gdb_num_core_regs = 32 + 3;
249 cc->disas_set_info = openrisc_disas_set_info;
250 cc->tcg_ops = &openrisc_tcg_ops;
251}
252
253
254static gint openrisc_cpu_list_compare(gconstpointer a, gconstpointer b)
255{
256 ObjectClass *class_a = (ObjectClass *)a;
257 ObjectClass *class_b = (ObjectClass *)b;
258 const char *name_a, *name_b;
259
260 name_a = object_class_get_name(class_a);
261 name_b = object_class_get_name(class_b);
262 if (strcmp(name_a, "any-" TYPE_OPENRISC_CPU) == 0) {
263 return 1;
264 } else if (strcmp(name_b, "any-" TYPE_OPENRISC_CPU) == 0) {
265 return -1;
266 } else {
267 return strcmp(name_a, name_b);
268 }
269}
270
271static void openrisc_cpu_list_entry(gpointer data, gpointer user_data)
272{
273 ObjectClass *oc = data;
274 const char *typename;
275 char *name;
276
277 typename = object_class_get_name(oc);
278 name = g_strndup(typename,
279 strlen(typename) - strlen("-" TYPE_OPENRISC_CPU));
280 qemu_printf(" %s\n", name);
281 g_free(name);
282}
283
284void cpu_openrisc_list(void)
285{
286 GSList *list;
287
288 list = object_class_get_list(TYPE_OPENRISC_CPU, false);
289 list = g_slist_sort(list, openrisc_cpu_list_compare);
290 qemu_printf("Available CPUs:\n");
291 g_slist_foreach(list, openrisc_cpu_list_entry, NULL);
292 g_slist_free(list);
293}
294
295#define DEFINE_OPENRISC_CPU_TYPE(cpu_model, initfn) \
296 { \
297 .parent = TYPE_OPENRISC_CPU, \
298 .instance_init = initfn, \
299 .name = OPENRISC_CPU_TYPE_NAME(cpu_model), \
300 }
301
302static const TypeInfo openrisc_cpus_type_infos[] = {
303 {
304 .name = TYPE_OPENRISC_CPU,
305 .parent = TYPE_CPU,
306 .instance_size = sizeof(OpenRISCCPU),
307 .instance_init = openrisc_cpu_initfn,
308 .abstract = true,
309 .class_size = sizeof(OpenRISCCPUClass),
310 .class_init = openrisc_cpu_class_init,
311 },
312 DEFINE_OPENRISC_CPU_TYPE("or1200", or1200_initfn),
313 DEFINE_OPENRISC_CPU_TYPE("any", openrisc_any_initfn),
314};
315
316DEFINE_TYPES(openrisc_cpus_type_infos)
317
