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26#include "qemu/osdep.h"
27#include "hw/ppc/mac_dbdma.h"
28#include "hw/qdev-properties.h"
29#include "migration/vmstate.h"
30#include "qemu/module.h"
31#include "hw/misc/macio/macio.h"
32#include "sysemu/block-backend.h"
33#include "sysemu/dma.h"
34
35#include "hw/ide/internal.h"
36
37
38
39
40#ifdef DEBUG_MACIO
41static const int debug_macio = 1;
42#else
43static const int debug_macio = 0;
44#endif
45
46#define MACIO_DPRINTF(fmt, ...) do { \
47 if (debug_macio) { \
48 printf(fmt , ## __VA_ARGS__); \
49 } \
50 } while (0)
51
52
53
54
55
56#define MACIO_PAGE_SIZE 4096
57
58static void pmac_ide_atapi_transfer_cb(void *opaque, int ret)
59{
60 DBDMA_io *io = opaque;
61 MACIOIDEState *m = io->opaque;
62 IDEState *s = idebus_active_if(&m->bus);
63 int64_t offset;
64
65 MACIO_DPRINTF("pmac_ide_atapi_transfer_cb\n");
66
67 if (ret < 0) {
68 MACIO_DPRINTF("DMA error: %d\n", ret);
69 qemu_sglist_destroy(&s->sg);
70 ide_atapi_io_error(s, ret);
71 goto done;
72 }
73
74 if (!m->dma_active) {
75 MACIO_DPRINTF("waiting for data (%#x - %#x - %x)\n",
76 s->nsector, io->len, s->status);
77
78 io->processing = false;
79 return;
80 }
81
82 if (s->io_buffer_size <= 0) {
83 MACIO_DPRINTF("End of IDE transfer\n");
84 qemu_sglist_destroy(&s->sg);
85 ide_atapi_cmd_ok(s);
86 m->dma_active = false;
87 goto done;
88 }
89
90 if (io->len == 0) {
91 MACIO_DPRINTF("End of DMA transfer\n");
92 goto done;
93 }
94
95 if (s->lba == -1) {
96
97 s->io_buffer_size = MIN(s->io_buffer_size, io->len);
98 dma_memory_write(&address_space_memory, io->addr, s->io_buffer,
99 s->io_buffer_size, MEMTXATTRS_UNSPECIFIED);
100 io->len = 0;
101 ide_atapi_cmd_ok(s);
102 m->dma_active = false;
103 goto done;
104 }
105
106
107 offset = ((int64_t)s->lba << 11) + s->io_buffer_index;
108
109 qemu_sglist_init(&s->sg, DEVICE(m), io->len / MACIO_PAGE_SIZE + 1,
110 &address_space_memory);
111 qemu_sglist_add(&s->sg, io->addr, io->len);
112 s->io_buffer_size -= io->len;
113 s->io_buffer_index += io->len;
114 io->len = 0;
115
116 s->bus->dma->aiocb = dma_blk_read(s->blk, &s->sg, offset, 0x1,
117 pmac_ide_atapi_transfer_cb, io);
118 return;
119
120done:
121 dma_memory_unmap(&address_space_memory, io->dma_mem, io->dma_len,
122 io->dir, io->dma_len);
123
124 if (ret < 0) {
125 block_acct_failed(blk_get_stats(s->blk), &s->acct);
126 } else {
127 block_acct_done(blk_get_stats(s->blk), &s->acct);
128 }
129
130 ide_set_inactive(s, false);
131 io->dma_end(opaque);
132}
133
134static void pmac_ide_transfer_cb(void *opaque, int ret)
135{
136 DBDMA_io *io = opaque;
137 MACIOIDEState *m = io->opaque;
138 IDEState *s = idebus_active_if(&m->bus);
139 int64_t offset;
140
141 MACIO_DPRINTF("pmac_ide_transfer_cb\n");
142
143 if (ret < 0) {
144 MACIO_DPRINTF("DMA error: %d\n", ret);
145 qemu_sglist_destroy(&s->sg);
146 ide_dma_error(s);
147 goto done;
148 }
149
150 if (!m->dma_active) {
151 MACIO_DPRINTF("waiting for data (%#x - %#x - %x)\n",
152 s->nsector, io->len, s->status);
153
154 io->processing = false;
155 return;
156 }
157
158 if (s->io_buffer_size <= 0) {
159 MACIO_DPRINTF("End of IDE transfer\n");
160 qemu_sglist_destroy(&s->sg);
161 s->status = READY_STAT | SEEK_STAT;
162 ide_set_irq(s->bus);
163 m->dma_active = false;
164 goto done;
165 }
166
167 if (io->len == 0) {
168 MACIO_DPRINTF("End of DMA transfer\n");
169 goto done;
170 }
171
172
173 offset = (ide_get_sector(s) << 9) + s->io_buffer_index;
174
175 qemu_sglist_init(&s->sg, DEVICE(m), io->len / MACIO_PAGE_SIZE + 1,
176 &address_space_memory);
177 qemu_sglist_add(&s->sg, io->addr, io->len);
178 s->io_buffer_size -= io->len;
179 s->io_buffer_index += io->len;
180 io->len = 0;
181
182 switch (s->dma_cmd) {
183 case IDE_DMA_READ:
184 s->bus->dma->aiocb = dma_blk_read(s->blk, &s->sg, offset, 0x1,
185 pmac_ide_atapi_transfer_cb, io);
186 break;
187 case IDE_DMA_WRITE:
188 s->bus->dma->aiocb = dma_blk_write(s->blk, &s->sg, offset, 0x1,
189 pmac_ide_transfer_cb, io);
190 break;
191 case IDE_DMA_TRIM:
192 s->bus->dma->aiocb = dma_blk_io(blk_get_aio_context(s->blk), &s->sg,
193 offset, 0x1, ide_issue_trim, s,
194 pmac_ide_transfer_cb, io,
195 DMA_DIRECTION_TO_DEVICE);
196 break;
197 default:
198 abort();
199 }
200
201 return;
202
203done:
204 dma_memory_unmap(&address_space_memory, io->dma_mem, io->dma_len,
205 io->dir, io->dma_len);
206
207 if (s->dma_cmd == IDE_DMA_READ || s->dma_cmd == IDE_DMA_WRITE) {
208 if (ret < 0) {
209 block_acct_failed(blk_get_stats(s->blk), &s->acct);
210 } else {
211 block_acct_done(blk_get_stats(s->blk), &s->acct);
212 }
213 }
214
215 ide_set_inactive(s, false);
216 io->dma_end(opaque);
217}
218
219static void pmac_ide_transfer(DBDMA_io *io)
220{
221 MACIOIDEState *m = io->opaque;
222 IDEState *s = idebus_active_if(&m->bus);
223
224 MACIO_DPRINTF("\n");
225
226 if (s->drive_kind == IDE_CD) {
227 block_acct_start(blk_get_stats(s->blk), &s->acct, io->len,
228 BLOCK_ACCT_READ);
229
230 pmac_ide_atapi_transfer_cb(io, 0);
231 return;
232 }
233
234 switch (s->dma_cmd) {
235 case IDE_DMA_READ:
236 block_acct_start(blk_get_stats(s->blk), &s->acct, io->len,
237 BLOCK_ACCT_READ);
238 break;
239 case IDE_DMA_WRITE:
240 block_acct_start(blk_get_stats(s->blk), &s->acct, io->len,
241 BLOCK_ACCT_WRITE);
242 break;
243 default:
244 break;
245 }
246
247 pmac_ide_transfer_cb(io, 0);
248}
249
250static void pmac_ide_flush(DBDMA_io *io)
251{
252 MACIOIDEState *m = io->opaque;
253 IDEState *s = idebus_active_if(&m->bus);
254
255 if (s->bus->dma->aiocb) {
256 blk_drain(s->blk);
257 }
258}
259
260
261static uint64_t pmac_ide_read(void *opaque, hwaddr addr, unsigned size)
262{
263 MACIOIDEState *d = opaque;
264 uint64_t retval = 0xffffffff;
265 int reg = addr >> 4;
266
267 switch (reg) {
268 case 0x0:
269 if (size == 1) {
270 retval = ide_data_readw(&d->bus, 0) & 0xFF;
271 } else if (size == 2) {
272 retval = ide_data_readw(&d->bus, 0);
273 } else if (size == 4) {
274 retval = ide_data_readl(&d->bus, 0);
275 }
276 break;
277 case 0x1 ... 0x7:
278 if (size == 1) {
279 retval = ide_ioport_read(&d->bus, reg);
280 }
281 break;
282 case 0x8:
283 case 0x16:
284 if (size == 1) {
285 retval = ide_status_read(&d->bus, 0);
286 }
287 break;
288 case 0x20:
289 if (size == 4) {
290 retval = d->timing_reg;
291 }
292 break;
293 case 0x30:
294
295
296
297
298
299
300
301 if (size == 4) {
302 retval = d->irq_reg;
303 }
304 break;
305 }
306
307 return retval;
308}
309
310
311static void pmac_ide_write(void *opaque, hwaddr addr, uint64_t val,
312 unsigned size)
313{
314 MACIOIDEState *d = opaque;
315 int reg = addr >> 4;
316
317 switch (reg) {
318 case 0x0:
319 if (size == 2) {
320 ide_data_writew(&d->bus, 0, val);
321 } else if (size == 4) {
322 ide_data_writel(&d->bus, 0, val);
323 }
324 break;
325 case 0x1 ... 0x7:
326 if (size == 1) {
327 ide_ioport_write(&d->bus, reg, val);
328 }
329 break;
330 case 0x8:
331 case 0x16:
332 if (size == 1) {
333 ide_ctrl_write(&d->bus, 0, val);
334 }
335 break;
336 case 0x20:
337 if (size == 4) {
338 d->timing_reg = val;
339 }
340 break;
341 case 0x30:
342 if (size == 4) {
343 if (val & 0x80000000u) {
344 d->irq_reg &= 0x7fffffff;
345 }
346 }
347 break;
348 }
349}
350
351static const MemoryRegionOps pmac_ide_ops = {
352 .read = pmac_ide_read,
353 .write = pmac_ide_write,
354 .valid.min_access_size = 1,
355 .valid.max_access_size = 4,
356 .endianness = DEVICE_LITTLE_ENDIAN,
357};
358
359static const VMStateDescription vmstate_pmac = {
360 .name = "ide",
361 .version_id = 5,
362 .minimum_version_id = 0,
363 .fields = (VMStateField[]) {
364 VMSTATE_IDE_BUS(bus, MACIOIDEState),
365 VMSTATE_IDE_DRIVES(bus.ifs, MACIOIDEState),
366 VMSTATE_BOOL(dma_active, MACIOIDEState),
367 VMSTATE_UINT32(timing_reg, MACIOIDEState),
368 VMSTATE_UINT32(irq_reg, MACIOIDEState),
369 VMSTATE_END_OF_LIST()
370 }
371};
372
373static void macio_ide_reset(DeviceState *dev)
374{
375 MACIOIDEState *d = MACIO_IDE(dev);
376
377 ide_bus_reset(&d->bus);
378}
379
380static int ide_nop_int(const IDEDMA *dma, bool is_write)
381{
382 return 0;
383}
384
385static int32_t ide_nop_int32(const IDEDMA *dma, int32_t l)
386{
387 return 0;
388}
389
390static void ide_dbdma_start(const IDEDMA *dma, IDEState *s,
391 BlockCompletionFunc *cb)
392{
393 MACIOIDEState *m = container_of(dma, MACIOIDEState, dma);
394
395 s->io_buffer_index = 0;
396 if (s->drive_kind == IDE_CD) {
397 s->io_buffer_size = s->packet_transfer_size;
398 } else {
399 s->io_buffer_size = s->nsector * BDRV_SECTOR_SIZE;
400 }
401
402 MACIO_DPRINTF("\n\n------------ IDE transfer\n");
403 MACIO_DPRINTF("buffer_size: %x buffer_index: %x\n",
404 s->io_buffer_size, s->io_buffer_index);
405 MACIO_DPRINTF("lba: %x size: %x\n", s->lba, s->io_buffer_size);
406 MACIO_DPRINTF("-------------------------\n");
407
408 m->dma_active = true;
409 DBDMA_kick(m->dbdma);
410}
411
412static const IDEDMAOps dbdma_ops = {
413 .start_dma = ide_dbdma_start,
414 .prepare_buf = ide_nop_int32,
415 .rw_buf = ide_nop_int,
416};
417
418static void macio_ide_realizefn(DeviceState *dev, Error **errp)
419{
420 MACIOIDEState *s = MACIO_IDE(dev);
421
422 ide_init2(&s->bus, s->ide_irq);
423
424
425 s->dma.ops = &dbdma_ops;
426 s->bus.dma = &s->dma;
427}
428
429static void pmac_ide_irq(void *opaque, int n, int level)
430{
431 MACIOIDEState *s = opaque;
432 uint32_t mask = 0x80000000u >> n;
433
434
435 if (level) {
436 s->irq_reg |= mask;
437 } else {
438 s->irq_reg &= ~mask;
439 }
440
441 if (n) {
442 qemu_set_irq(s->real_ide_irq, level);
443 } else {
444 qemu_set_irq(s->real_dma_irq, level);
445 }
446}
447
448static void macio_ide_initfn(Object *obj)
449{
450 SysBusDevice *d = SYS_BUS_DEVICE(obj);
451 MACIOIDEState *s = MACIO_IDE(obj);
452
453 ide_bus_init(&s->bus, sizeof(s->bus), DEVICE(obj), 0, 2);
454 memory_region_init_io(&s->mem, obj, &pmac_ide_ops, s, "pmac-ide", 0x1000);
455 sysbus_init_mmio(d, &s->mem);
456 sysbus_init_irq(d, &s->real_ide_irq);
457 sysbus_init_irq(d, &s->real_dma_irq);
458 s->dma_irq = qemu_allocate_irq(pmac_ide_irq, s, 0);
459 s->ide_irq = qemu_allocate_irq(pmac_ide_irq, s, 1);
460
461 object_property_add_link(obj, "dbdma", TYPE_MAC_DBDMA,
462 (Object **) &s->dbdma,
463 qdev_prop_allow_set_link_before_realize, 0);
464}
465
466static Property macio_ide_properties[] = {
467 DEFINE_PROP_UINT32("channel", MACIOIDEState, channel, 0),
468 DEFINE_PROP_UINT32("addr", MACIOIDEState, addr, -1),
469 DEFINE_PROP_END_OF_LIST(),
470};
471
472static void macio_ide_class_init(ObjectClass *oc, void *data)
473{
474 DeviceClass *dc = DEVICE_CLASS(oc);
475
476 dc->realize = macio_ide_realizefn;
477 dc->reset = macio_ide_reset;
478 device_class_set_props(dc, macio_ide_properties);
479 dc->vmsd = &vmstate_pmac;
480 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
481}
482
483static const TypeInfo macio_ide_type_info = {
484 .name = TYPE_MACIO_IDE,
485 .parent = TYPE_SYS_BUS_DEVICE,
486 .instance_size = sizeof(MACIOIDEState),
487 .instance_init = macio_ide_initfn,
488 .class_init = macio_ide_class_init,
489};
490
491static void macio_ide_register_types(void)
492{
493 type_register_static(&macio_ide_type_info);
494}
495
496
497void macio_ide_init_drives(MACIOIDEState *s, DriveInfo **hd_table)
498{
499 int i;
500
501 for (i = 0; i < 2; i++) {
502 if (hd_table[i]) {
503 ide_create_drive(&s->bus, i, hd_table[i]);
504 }
505 }
506}
507
508void macio_ide_register_dma(MACIOIDEState *s)
509{
510 DBDMA_register_channel(s->dbdma, s->channel, s->dma_irq,
511 pmac_ide_transfer, pmac_ide_flush, s);
512}
513
514type_init(macio_ide_register_types)
515
