LXR qemu/hw/intc/i8259

   1/*
   2 * QEMU 8259 - common bits of emulated and KVM kernel model
   3 *
   4 * Copyright (c) 2003-2004 Fabrice Bellard
   5 * Copyright (c) 2011      Jan Kiszka, Siemens AG
   6 *
   7 * Permission is hereby granted, free of charge, to any person obtaining a copy
   8 * of this software and associated documentation files (the "Software"), to deal
   9 * in the Software without restriction, including without limitation the rights
  10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11 * copies of the Software, and to permit persons to whom the Software is
  12 * furnished to do so, subject to the following conditions:
  13 *
  14 * The above copyright notice and this permission notice shall be included in
  15 * all copies or substantial portions of the Software.
  16 *
  17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23 * THE SOFTWARE.
  24 */
  25
  26#include "qemu/osdep.h"
  27#include "hw/intc/i8259.h"
  28#include "hw/isa/i8259_internal.h"
  29#include "hw/qdev-properties.h"
  30#include "migration/vmstate.h"
  31#include "monitor/monitor.h"
  32#include "qapi/error.h"
  33
  34static int irq_level[16];
  35static uint64_t irq_count[16];
  36
  37void pic_reset_common(PICCommonState *s)
  38{
  39    s->last_irr = 0;
  40    s->irr &= s->elcr;
  41    s->imr = 0;
  42    s->isr = 0;
  43    s->priority_add = 0;
  44    s->irq_base = 0;
  45    s->read_reg_select = 0;
  46    s->poll = 0;
  47    s->special_mask = 0;
  48    s->init_state = 0;
  49    s->auto_eoi = 0;
  50    s->rotate_on_auto_eoi = 0;
  51    s->special_fully_nested_mode = 0;
  52    s->init4 = 0;
  53    s->single_mode = 0;
  54    /* Note: ELCR is not reset */
  55}
  56
  57static int pic_dispatch_pre_save(void *opaque)
  58{
  59    PICCommonState *s = opaque;
  60    PICCommonClass *info = PIC_COMMON_GET_CLASS(s);
  61
  62    if (info->pre_save) {
  63        info->pre_save(s);
  64    }
  65
  66    return 0;
  67}
  68
  69static int pic_dispatch_post_load(void *opaque, int version_id)
  70{
  71    PICCommonState *s = opaque;
  72    PICCommonClass *info = PIC_COMMON_GET_CLASS(s);
  73
  74    if (info->post_load) {
  75        info->post_load(s);
  76    }
  77    return 0;
  78}
  79
  80static void pic_common_realize(DeviceState *dev, Error **errp)
  81{
  82    PICCommonState *s = PIC_COMMON(dev);
  83    ISADevice *isa = ISA_DEVICE(dev);
  84
  85    isa_register_ioport(isa, &s->base_io, s->iobase);
  86    if (s->elcr_addr != -1) {
  87        isa_register_ioport(isa, &s->elcr_io, s->elcr_addr);
  88    }
  89
  90    qdev_set_legacy_instance_id(dev, s->iobase, 1);
  91}
  92
  93ISADevice *i8259_init_chip(const char *name, ISABus *bus, bool master)
  94{
  95    DeviceState *dev;
  96    ISADevice *isadev;
  97
  98    isadev = isa_new(name);
  99    dev = DEVICE(isadev);
 100    qdev_prop_set_uint32(dev, "iobase", master ? 0x20 : 0xa0);
 101    qdev_prop_set_uint32(dev, "elcr_addr", master ? 0x4d0 : 0x4d1);
 102    qdev_prop_set_uint8(dev, "elcr_mask", master ? 0xf8 : 0xde);
 103    qdev_prop_set_bit(dev, "master", master);
 104    isa_realize_and_unref(isadev, bus, &error_fatal);
 105
 106    return isadev;
 107}
 108
 109void pic_stat_update_irq(int irq, int level)
 110{
 111    if (level != irq_level[irq]) {
 112        irq_level[irq] = level;
 113        if (level == 1) {
 114            irq_count[irq]++;
 115        }
 116    }
 117}
 118
 119static bool pic_get_statistics(InterruptStatsProvider *obj,
 120                               uint64_t **irq_counts, unsigned int *nb_irqs)
 121{
 122    PICCommonState *s = PIC_COMMON(obj);
 123
 124    if (s->master) {
 125        *irq_counts = irq_count;
 126        *nb_irqs = ARRAY_SIZE(irq_count);
 127    } else {
 128        *irq_counts = NULL;
 129        *nb_irqs = 0;
 130    }
 131
 132    return true;
 133}
 134
 135static void pic_print_info(InterruptStatsProvider *obj, Monitor *mon)
 136{
 137    PICCommonState *s = PIC_COMMON(obj);
 138
 139    pic_dispatch_pre_save(s);
 140    monitor_printf(mon, "pic%d: irr=%02x imr=%02x isr=%02x hprio=%d "
 141                   "irq_base=%02x rr_sel=%d elcr=%02x fnm=%d\n",
 142                   s->master ? 0 : 1, s->irr, s->imr, s->isr, s->priority_add,
 143                   s->irq_base, s->read_reg_select, s->elcr,
 144                   s->special_fully_nested_mode);
 145}
 146
 147static const VMStateDescription vmstate_pic_common = {
 148    .name = "i8259",
 149    .version_id = 1,
 150    .minimum_version_id = 1,
 151    .pre_save = pic_dispatch_pre_save,
 152    .post_load = pic_dispatch_post_load,
 153    .fields = (VMStateField[]) {
 154        VMSTATE_UINT8(last_irr, PICCommonState),
 155        VMSTATE_UINT8(irr, PICCommonState),
 156        VMSTATE_UINT8(imr, PICCommonState),
 157        VMSTATE_UINT8(isr, PICCommonState),
 158        VMSTATE_UINT8(priority_add, PICCommonState),
 159        VMSTATE_UINT8(irq_base, PICCommonState),
 160        VMSTATE_UINT8(read_reg_select, PICCommonState),
 161        VMSTATE_UINT8(poll, PICCommonState),
 162        VMSTATE_UINT8(special_mask, PICCommonState),
 163        VMSTATE_UINT8(init_state, PICCommonState),
 164        VMSTATE_UINT8(auto_eoi, PICCommonState),
 165        VMSTATE_UINT8(rotate_on_auto_eoi, PICCommonState),
 166        VMSTATE_UINT8(special_fully_nested_mode, PICCommonState),
 167        VMSTATE_UINT8(init4, PICCommonState),
 168        VMSTATE_UINT8(single_mode, PICCommonState),
 169        VMSTATE_UINT8(elcr, PICCommonState),
 170        VMSTATE_END_OF_LIST()
 171    }
 172};
 173
 174static Property pic_properties_common[] = {
 175    DEFINE_PROP_UINT32("iobase", PICCommonState, iobase,  -1),
 176    DEFINE_PROP_UINT32("elcr_addr", PICCommonState, elcr_addr,  -1),
 177    DEFINE_PROP_UINT8("elcr_mask", PICCommonState, elcr_mask,  -1),
 178    DEFINE_PROP_BIT("master", PICCommonState, master,  0, false),
 179    DEFINE_PROP_END_OF_LIST(),
 180};
 181
 182static void pic_common_class_init(ObjectClass *klass, void *data)
 183{
 184    DeviceClass *dc = DEVICE_CLASS(klass);
 185    InterruptStatsProviderClass *ic = INTERRUPT_STATS_PROVIDER_CLASS(klass);
 186
 187    dc->vmsd = &vmstate_pic_common;
 188    device_class_set_props(dc, pic_properties_common);
 189    dc->realize = pic_common_realize;
 190    /*
 191     * Reason: unlike ordinary ISA devices, the PICs need additional
 192     * wiring: its IRQ input lines are set up by board code, and the
 193     * wiring of the slave to the master is hard-coded in device model
 194     * code.
 195     */
 196    dc->user_creatable = false;
 197    ic->get_statistics = pic_get_statistics;
 198    ic->print_info = pic_print_info;
 199}
 200
 201static const TypeInfo pic_common_type = {
 202    .name = TYPE_PIC_COMMON,
 203    .parent = TYPE_ISA_DEVICE,
 204    .instance_size = sizeof(PICCommonState),
 205    .class_size = sizeof(PICCommonClass),
 206    .class_init = pic_common_class_init,
 207    .abstract = true,
 208    .interfaces = (InterfaceInfo[]) {
 209        { TYPE_INTERRUPT_STATS_PROVIDER },
 210        { }
 211    },
 212};
 213
 214static void pic_common_register_types(void)
 215{
 216    type_register_static(&pic_common_type);
 217}
 218
 219type_init(pic_common_register_types)
 220