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13#include "qemu/osdep.h"
14#include "qemu/error-report.h"
15#include "qemu/module.h"
16#include "qapi/error.h"
17#include "sysemu/blockdev.h"
18#include "chardev/char.h"
19#include "hw/block/fdc.h"
20#include "hw/isa/superio.h"
21#include "hw/qdev-properties.h"
22#include "hw/input/i8042.h"
23#include "hw/char/serial.h"
24#include "trace.h"
25
26static void isa_superio_realize(DeviceState *dev, Error **errp)
27{
28 ISASuperIODevice *sio = ISA_SUPERIO(dev);
29 ISASuperIOClass *k = ISA_SUPERIO_GET_CLASS(sio);
30 ISABus *bus = isa_bus_from_device(ISA_DEVICE(dev));
31 ISADevice *isa;
32 DeviceState *d;
33 Chardev *chr;
34 DriveInfo *fd[MAX_FD];
35 char *name;
36 int i;
37
38
39 for (i = 0; i < k->parallel.count; i++) {
40 if (i >= ARRAY_SIZE(sio->parallel)) {
41 warn_report("superio: ignoring %td parallel controllers",
42 k->parallel.count - ARRAY_SIZE(sio->parallel));
43 break;
44 }
45 if (!k->parallel.is_enabled || k->parallel.is_enabled(sio, i)) {
46
47 chr = parallel_hds[i];
48 if (chr == NULL) {
49 name = g_strdup_printf("discarding-parallel%d", i);
50 chr = qemu_chr_new(name, "null", NULL);
51 } else {
52 name = g_strdup_printf("parallel%d", i);
53 }
54 isa = isa_new("isa-parallel");
55 d = DEVICE(isa);
56 qdev_prop_set_uint32(d, "index", i);
57 if (k->parallel.get_iobase) {
58 qdev_prop_set_uint32(d, "iobase",
59 k->parallel.get_iobase(sio, i));
60 }
61 if (k->parallel.get_irq) {
62 qdev_prop_set_uint32(d, "irq", k->parallel.get_irq(sio, i));
63 }
64 qdev_prop_set_chr(d, "chardev", chr);
65 object_property_add_child(OBJECT(dev), name, OBJECT(isa));
66 isa_realize_and_unref(isa, bus, &error_fatal);
67 sio->parallel[i] = isa;
68 trace_superio_create_parallel(i,
69 k->parallel.get_iobase ?
70 k->parallel.get_iobase(sio, i) : -1,
71 k->parallel.get_irq ?
72 k->parallel.get_irq(sio, i) : -1);
73 g_free(name);
74 }
75 }
76
77
78 for (i = 0; i < k->serial.count; i++) {
79 if (i >= ARRAY_SIZE(sio->serial)) {
80 warn_report("superio: ignoring %td serial controllers",
81 k->serial.count - ARRAY_SIZE(sio->serial));
82 break;
83 }
84 if (!k->serial.is_enabled || k->serial.is_enabled(sio, i)) {
85
86 chr = serial_hd(i);
87 if (chr == NULL) {
88 name = g_strdup_printf("discarding-serial%d", i);
89 chr = qemu_chr_new(name, "null", NULL);
90 } else {
91 name = g_strdup_printf("serial%d", i);
92 }
93 isa = isa_new(TYPE_ISA_SERIAL);
94 d = DEVICE(isa);
95 qdev_prop_set_uint32(d, "index", i);
96 if (k->serial.get_iobase) {
97 qdev_prop_set_uint32(d, "iobase",
98 k->serial.get_iobase(sio, i));
99 }
100 if (k->serial.get_irq) {
101 qdev_prop_set_uint32(d, "irq", k->serial.get_irq(sio, i));
102 }
103 qdev_prop_set_chr(d, "chardev", chr);
104 object_property_add_child(OBJECT(dev), name, OBJECT(isa));
105 isa_realize_and_unref(isa, bus, &error_fatal);
106 sio->serial[i] = isa;
107 trace_superio_create_serial(i,
108 k->serial.get_iobase ?
109 k->serial.get_iobase(sio, i) : -1,
110 k->serial.get_irq ?
111 k->serial.get_irq(sio, i) : -1);
112 g_free(name);
113 }
114 }
115
116
117 if (!k->floppy.is_enabled || k->floppy.is_enabled(sio, 0)) {
118 isa = isa_new(TYPE_ISA_FDC);
119 d = DEVICE(isa);
120 if (k->floppy.get_iobase) {
121 qdev_prop_set_uint32(d, "iobase", k->floppy.get_iobase(sio, 0));
122 }
123 if (k->floppy.get_irq) {
124 qdev_prop_set_uint32(d, "irq", k->floppy.get_irq(sio, 0));
125 }
126
127 for (i = 0; i < MAX_FD; i++) {
128 fd[i] = drive_get(IF_FLOPPY, 0, i);
129 }
130 object_property_add_child(OBJECT(sio), "isa-fdc", OBJECT(isa));
131 isa_realize_and_unref(isa, bus, &error_fatal);
132 isa_fdc_init_drives(isa, fd);
133 sio->floppy = isa;
134 trace_superio_create_floppy(0,
135 k->floppy.get_iobase ?
136 k->floppy.get_iobase(sio, 0) : -1,
137 k->floppy.get_irq ?
138 k->floppy.get_irq(sio, 0) : -1);
139 }
140
141
142 isa = isa_new(TYPE_I8042);
143 object_property_add_child(OBJECT(sio), TYPE_I8042, OBJECT(isa));
144 isa_realize_and_unref(isa, bus, &error_fatal);
145 sio->kbc = isa;
146
147
148 if (k->ide.count && (!k->ide.is_enabled || k->ide.is_enabled(sio, 0))) {
149 isa = isa_new("isa-ide");
150 d = DEVICE(isa);
151 if (k->ide.get_iobase) {
152 qdev_prop_set_uint32(d, "iobase", k->ide.get_iobase(sio, 0));
153 }
154 if (k->ide.get_iobase) {
155 qdev_prop_set_uint32(d, "iobase2", k->ide.get_iobase(sio, 1));
156 }
157 if (k->ide.get_irq) {
158 qdev_prop_set_uint32(d, "irq", k->ide.get_irq(sio, 0));
159 }
160 object_property_add_child(OBJECT(sio), "isa-ide", OBJECT(isa));
161 isa_realize_and_unref(isa, bus, &error_fatal);
162 sio->ide = isa;
163 trace_superio_create_ide(0,
164 k->ide.get_iobase ?
165 k->ide.get_iobase(sio, 0) : -1,
166 k->ide.get_irq ?
167 k->ide.get_irq(sio, 0) : -1);
168 }
169}
170
171static void isa_superio_class_init(ObjectClass *oc, void *data)
172{
173 DeviceClass *dc = DEVICE_CLASS(oc);
174
175 dc->realize = isa_superio_realize;
176
177 dc->user_creatable = false;
178}
179
180static const TypeInfo isa_superio_type_info = {
181 .name = TYPE_ISA_SUPERIO,
182 .parent = TYPE_ISA_DEVICE,
183 .abstract = true,
184 .class_size = sizeof(ISASuperIOClass),
185 .class_init = isa_superio_class_init,
186};
187
188
189static void fdc37m81x_class_init(ObjectClass *klass, void *data)
190{
191 ISASuperIOClass *sc = ISA_SUPERIO_CLASS(klass);
192
193 sc->serial.count = 2;
194 sc->parallel.count = 1;
195 sc->floppy.count = 1;
196 sc->ide.count = 0;
197}
198
199static const TypeInfo fdc37m81x_type_info = {
200 .name = TYPE_FDC37M81X_SUPERIO,
201 .parent = TYPE_ISA_SUPERIO,
202 .instance_size = sizeof(ISASuperIODevice),
203 .class_init = fdc37m81x_class_init,
204};
205
206static void isa_superio_register_types(void)
207{
208 type_register_static(&isa_superio_type_info);
209 type_register_static(&fdc37m81x_type_info);
210}
211
212type_init(isa_superio_register_types)
213
