1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36#include "qemu/osdep.h"
37#include "qemu/units.h"
38#include "net/eth.h"
39#include "net/net.h"
40#include "net/tap.h"
41#include "qemu/module.h"
42#include "qemu/range.h"
43#include "sysemu/sysemu.h"
44#include "hw/hw.h"
45#include "hw/pci/msi.h"
46#include "hw/pci/msix.h"
47#include "hw/qdev-properties.h"
48#include "migration/vmstate.h"
49
50#include "e1000_regs.h"
51
52#include "e1000x_common.h"
53#include "e1000e_core.h"
54
55#include "trace.h"
56#include "qapi/error.h"
57#include "qom/object.h"
58
59#define TYPE_E1000E "e1000e"
60OBJECT_DECLARE_SIMPLE_TYPE(E1000EState, E1000E)
61
62struct E1000EState {
63 PCIDevice parent_obj;
64 NICState *nic;
65 NICConf conf;
66
67 MemoryRegion mmio;
68 MemoryRegion flash;
69 MemoryRegion io;
70 MemoryRegion msix;
71
72 uint32_t ioaddr;
73
74 uint16_t subsys_ven;
75 uint16_t subsys;
76
77 uint16_t subsys_ven_used;
78 uint16_t subsys_used;
79
80 bool disable_vnet;
81
82 E1000ECore core;
83 bool init_vet;
84};
85
86#define E1000E_MMIO_IDX 0
87#define E1000E_FLASH_IDX 1
88#define E1000E_IO_IDX 2
89#define E1000E_MSIX_IDX 3
90
91#define E1000E_MMIO_SIZE (128 * KiB)
92#define E1000E_FLASH_SIZE (128 * KiB)
93#define E1000E_IO_SIZE (32)
94#define E1000E_MSIX_SIZE (16 * KiB)
95
96#define E1000E_MSIX_TABLE (0x0000)
97#define E1000E_MSIX_PBA (0x2000)
98
99static uint64_t
100e1000e_mmio_read(void *opaque, hwaddr addr, unsigned size)
101{
102 E1000EState *s = opaque;
103 return e1000e_core_read(&s->core, addr, size);
104}
105
106static void
107e1000e_mmio_write(void *opaque, hwaddr addr,
108 uint64_t val, unsigned size)
109{
110 E1000EState *s = opaque;
111 e1000e_core_write(&s->core, addr, val, size);
112}
113
114static bool
115e1000e_io_get_reg_index(E1000EState *s, uint32_t *idx)
116{
117 if (s->ioaddr < 0x1FFFF) {
118 *idx = s->ioaddr;
119 return true;
120 }
121
122 if (s->ioaddr < 0x7FFFF) {
123 trace_e1000e_wrn_io_addr_undefined(s->ioaddr);
124 return false;
125 }
126
127 if (s->ioaddr < 0xFFFFF) {
128 trace_e1000e_wrn_io_addr_flash(s->ioaddr);
129 return false;
130 }
131
132 trace_e1000e_wrn_io_addr_unknown(s->ioaddr);
133 return false;
134}
135
136static uint64_t
137e1000e_io_read(void *opaque, hwaddr addr, unsigned size)
138{
139 E1000EState *s = opaque;
140 uint32_t idx = 0;
141 uint64_t val;
142
143 switch (addr) {
144 case E1000_IOADDR:
145 trace_e1000e_io_read_addr(s->ioaddr);
146 return s->ioaddr;
147 case E1000_IODATA:
148 if (e1000e_io_get_reg_index(s, &idx)) {
149 val = e1000e_core_read(&s->core, idx, sizeof(val));
150 trace_e1000e_io_read_data(idx, val);
151 return val;
152 }
153 return 0;
154 default:
155 trace_e1000e_wrn_io_read_unknown(addr);
156 return 0;
157 }
158}
159
160static void
161e1000e_io_write(void *opaque, hwaddr addr,
162 uint64_t val, unsigned size)
163{
164 E1000EState *s = opaque;
165 uint32_t idx = 0;
166
167 switch (addr) {
168 case E1000_IOADDR:
169 trace_e1000e_io_write_addr(val);
170 s->ioaddr = (uint32_t) val;
171 return;
172 case E1000_IODATA:
173 if (e1000e_io_get_reg_index(s, &idx)) {
174 trace_e1000e_io_write_data(idx, val);
175 e1000e_core_write(&s->core, idx, val, sizeof(val));
176 }
177 return;
178 default:
179 trace_e1000e_wrn_io_write_unknown(addr);
180 return;
181 }
182}
183
184static const MemoryRegionOps mmio_ops = {
185 .read = e1000e_mmio_read,
186 .write = e1000e_mmio_write,
187 .endianness = DEVICE_LITTLE_ENDIAN,
188 .impl = {
189 .min_access_size = 4,
190 .max_access_size = 4,
191 },
192};
193
194static const MemoryRegionOps io_ops = {
195 .read = e1000e_io_read,
196 .write = e1000e_io_write,
197 .endianness = DEVICE_LITTLE_ENDIAN,
198 .impl = {
199 .min_access_size = 4,
200 .max_access_size = 4,
201 },
202};
203
204static bool
205e1000e_nc_can_receive(NetClientState *nc)
206{
207 E1000EState *s = qemu_get_nic_opaque(nc);
208 return e1000e_can_receive(&s->core);
209}
210
211static ssize_t
212e1000e_nc_receive_iov(NetClientState *nc, const struct iovec *iov, int iovcnt)
213{
214 E1000EState *s = qemu_get_nic_opaque(nc);
215 return e1000e_receive_iov(&s->core, iov, iovcnt);
216}
217
218static ssize_t
219e1000e_nc_receive(NetClientState *nc, const uint8_t *buf, size_t size)
220{
221 E1000EState *s = qemu_get_nic_opaque(nc);
222 return e1000e_receive(&s->core, buf, size);
223}
224
225static void
226e1000e_set_link_status(NetClientState *nc)
227{
228 E1000EState *s = qemu_get_nic_opaque(nc);
229 e1000e_core_set_link_status(&s->core);
230}
231
232static NetClientInfo net_e1000e_info = {
233 .type = NET_CLIENT_DRIVER_NIC,
234 .size = sizeof(NICState),
235 .can_receive = e1000e_nc_can_receive,
236 .receive = e1000e_nc_receive,
237 .receive_iov = e1000e_nc_receive_iov,
238 .link_status_changed = e1000e_set_link_status,
239};
240
241
242
243
244
245static const uint16_t e1000e_eeprom_template[64] = {
246
247 0x0000, 0x0000, 0x0000, 0x0420, 0xf746, 0x2010, 0xffff, 0xffff,
248
249 0x0000, 0x0000, 0x026b, 0x0000, 0x8086, 0x0000, 0x0000, 0x8058,
250
251 0x0000, 0x2001, 0x7e7c, 0xffff, 0x1000, 0x00c8, 0x0000, 0x2704,
252
253 0x6cc9, 0x3150, 0x070e, 0x460b, 0x2d84, 0x0100, 0xf000, 0x0706,
254
255 0x6000, 0x0080, 0x0f04, 0x7fff, 0x4f01, 0xc600, 0x0000, 0x20ff,
256
257 0x0028, 0x0003, 0x0000, 0x0000, 0x0000, 0x0003, 0x0000, 0xffff,
258
259 0x0100, 0xc000, 0x121c, 0xc007, 0xffff, 0xffff, 0xffff, 0xffff,
260
261 0xffff, 0xffff, 0xffff, 0xffff, 0x0000, 0x0120, 0xffff, 0x0000,
262};
263
264static void e1000e_core_realize(E1000EState *s)
265{
266 s->core.owner = &s->parent_obj;
267 s->core.owner_nic = s->nic;
268}
269
270static void
271e1000e_unuse_msix_vectors(E1000EState *s, int num_vectors)
272{
273 int i;
274 for (i = 0; i < num_vectors; i++) {
275 msix_vector_unuse(PCI_DEVICE(s), i);
276 }
277}
278
279static void
280e1000e_use_msix_vectors(E1000EState *s, int num_vectors)
281{
282 int i;
283 for (i = 0; i < num_vectors; i++) {
284 msix_vector_use(PCI_DEVICE(s), i);
285 }
286}
287
288static void
289e1000e_init_msix(E1000EState *s)
290{
291 int res = msix_init(PCI_DEVICE(s), E1000E_MSIX_VEC_NUM,
292 &s->msix,
293 E1000E_MSIX_IDX, E1000E_MSIX_TABLE,
294 &s->msix,
295 E1000E_MSIX_IDX, E1000E_MSIX_PBA,
296 0xA0, NULL);
297
298 if (res < 0) {
299 trace_e1000e_msix_init_fail(res);
300 } else {
301 e1000e_use_msix_vectors(s, E1000E_MSIX_VEC_NUM);
302 }
303}
304
305static void
306e1000e_cleanup_msix(E1000EState *s)
307{
308 if (msix_present(PCI_DEVICE(s))) {
309 e1000e_unuse_msix_vectors(s, E1000E_MSIX_VEC_NUM);
310 msix_uninit(PCI_DEVICE(s), &s->msix, &s->msix);
311 }
312}
313
314static void
315e1000e_init_net_peer(E1000EState *s, PCIDevice *pci_dev, uint8_t *macaddr)
316{
317 DeviceState *dev = DEVICE(pci_dev);
318 NetClientState *nc;
319 int i;
320
321 s->nic = qemu_new_nic(&net_e1000e_info, &s->conf,
322 object_get_typename(OBJECT(s)), dev->id, s);
323
324 s->core.max_queue_num = s->conf.peers.queues ? s->conf.peers.queues - 1 : 0;
325
326 trace_e1000e_mac_set_permanent(MAC_ARG(macaddr));
327 memcpy(s->core.permanent_mac, macaddr, sizeof(s->core.permanent_mac));
328
329 qemu_format_nic_info_str(qemu_get_queue(s->nic), macaddr);
330
331
332 if (s->disable_vnet) {
333 s->core.has_vnet = false;
334 trace_e1000e_cfg_support_virtio(false);
335 return;
336 } else {
337 s->core.has_vnet = true;
338 }
339
340 for (i = 0; i < s->conf.peers.queues; i++) {
341 nc = qemu_get_subqueue(s->nic, i);
342 if (!nc->peer || !qemu_has_vnet_hdr(nc->peer)) {
343 s->core.has_vnet = false;
344 trace_e1000e_cfg_support_virtio(false);
345 return;
346 }
347 }
348
349 trace_e1000e_cfg_support_virtio(true);
350
351 for (i = 0; i < s->conf.peers.queues; i++) {
352 nc = qemu_get_subqueue(s->nic, i);
353 qemu_set_vnet_hdr_len(nc->peer, sizeof(struct virtio_net_hdr));
354 qemu_using_vnet_hdr(nc->peer, true);
355 }
356}
357
358static inline uint64_t
359e1000e_gen_dsn(uint8_t *mac)
360{
361 return (uint64_t)(mac[5]) |
362 (uint64_t)(mac[4]) << 8 |
363 (uint64_t)(mac[3]) << 16 |
364 (uint64_t)(0x00FF) << 24 |
365 (uint64_t)(0x00FF) << 32 |
366 (uint64_t)(mac[2]) << 40 |
367 (uint64_t)(mac[1]) << 48 |
368 (uint64_t)(mac[0]) << 56;
369}
370
371static int
372e1000e_add_pm_capability(PCIDevice *pdev, uint8_t offset, uint16_t pmc)
373{
374 Error *local_err = NULL;
375 int ret = pci_add_capability(pdev, PCI_CAP_ID_PM, offset,
376 PCI_PM_SIZEOF, &local_err);
377
378 if (local_err) {
379 error_report_err(local_err);
380 return ret;
381 }
382
383 pci_set_word(pdev->config + offset + PCI_PM_PMC,
384 PCI_PM_CAP_VER_1_1 |
385 pmc);
386
387 pci_set_word(pdev->wmask + offset + PCI_PM_CTRL,
388 PCI_PM_CTRL_STATE_MASK |
389 PCI_PM_CTRL_PME_ENABLE |
390 PCI_PM_CTRL_DATA_SEL_MASK);
391
392 pci_set_word(pdev->w1cmask + offset + PCI_PM_CTRL,
393 PCI_PM_CTRL_PME_STATUS);
394
395 return ret;
396}
397
398static void e1000e_write_config(PCIDevice *pci_dev, uint32_t address,
399 uint32_t val, int len)
400{
401 E1000EState *s = E1000E(pci_dev);
402
403 pci_default_write_config(pci_dev, address, val, len);
404
405 if (range_covers_byte(address, len, PCI_COMMAND) &&
406 (pci_dev->config[PCI_COMMAND] & PCI_COMMAND_MASTER)) {
407 e1000e_start_recv(&s->core);
408 }
409}
410
411static void e1000e_pci_realize(PCIDevice *pci_dev, Error **errp)
412{
413 static const uint16_t e1000e_pmrb_offset = 0x0C8;
414 static const uint16_t e1000e_pcie_offset = 0x0E0;
415 static const uint16_t e1000e_aer_offset = 0x100;
416 static const uint16_t e1000e_dsn_offset = 0x140;
417 E1000EState *s = E1000E(pci_dev);
418 uint8_t *macaddr;
419 int ret;
420
421 trace_e1000e_cb_pci_realize();
422
423 pci_dev->config_write = e1000e_write_config;
424
425 pci_dev->config[PCI_CACHE_LINE_SIZE] = 0x10;
426 pci_dev->config[PCI_INTERRUPT_PIN] = 1;
427
428 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID, s->subsys_ven);
429 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID, s->subsys);
430
431 s->subsys_ven_used = s->subsys_ven;
432 s->subsys_used = s->subsys;
433
434
435 memory_region_init_io(&s->mmio, OBJECT(s), &mmio_ops, s,
436 "e1000e-mmio", E1000E_MMIO_SIZE);
437 pci_register_bar(pci_dev, E1000E_MMIO_IDX,
438 PCI_BASE_ADDRESS_SPACE_MEMORY, &s->mmio);
439
440
441
442
443
444 memory_region_init(&s->flash, OBJECT(s),
445 "e1000e-flash", E1000E_FLASH_SIZE);
446 pci_register_bar(pci_dev, E1000E_FLASH_IDX,
447 PCI_BASE_ADDRESS_SPACE_MEMORY, &s->flash);
448
449 memory_region_init_io(&s->io, OBJECT(s), &io_ops, s,
450 "e1000e-io", E1000E_IO_SIZE);
451 pci_register_bar(pci_dev, E1000E_IO_IDX,
452 PCI_BASE_ADDRESS_SPACE_IO, &s->io);
453
454 memory_region_init(&s->msix, OBJECT(s), "e1000e-msix",
455 E1000E_MSIX_SIZE);
456 pci_register_bar(pci_dev, E1000E_MSIX_IDX,
457 PCI_BASE_ADDRESS_SPACE_MEMORY, &s->msix);
458
459
460 qemu_macaddr_default_if_unset(&s->conf.macaddr);
461 macaddr = s->conf.macaddr.a;
462
463 e1000e_init_msix(s);
464
465 if (pcie_endpoint_cap_v1_init(pci_dev, e1000e_pcie_offset) < 0) {
466 hw_error("Failed to initialize PCIe capability");
467 }
468
469 ret = msi_init(PCI_DEVICE(s), 0xD0, 1, true, false, NULL);
470 if (ret) {
471 trace_e1000e_msi_init_fail(ret);
472 }
473
474 if (e1000e_add_pm_capability(pci_dev, e1000e_pmrb_offset,
475 PCI_PM_CAP_DSI) < 0) {
476 hw_error("Failed to initialize PM capability");
477 }
478
479 if (pcie_aer_init(pci_dev, PCI_ERR_VER, e1000e_aer_offset,
480 PCI_ERR_SIZEOF, NULL) < 0) {
481 hw_error("Failed to initialize AER capability");
482 }
483
484 pcie_dev_ser_num_init(pci_dev, e1000e_dsn_offset,
485 e1000e_gen_dsn(macaddr));
486
487 e1000e_init_net_peer(s, pci_dev, macaddr);
488
489
490 e1000e_core_realize(s);
491
492 e1000e_core_pci_realize(&s->core,
493 e1000e_eeprom_template,
494 sizeof(e1000e_eeprom_template),
495 macaddr);
496}
497
498static void e1000e_pci_uninit(PCIDevice *pci_dev)
499{
500 E1000EState *s = E1000E(pci_dev);
501
502 trace_e1000e_cb_pci_uninit();
503
504 e1000e_core_pci_uninit(&s->core);
505
506 pcie_aer_exit(pci_dev);
507 pcie_cap_exit(pci_dev);
508
509 qemu_del_nic(s->nic);
510
511 e1000e_cleanup_msix(s);
512 msi_uninit(pci_dev);
513}
514
515static void e1000e_qdev_reset(DeviceState *dev)
516{
517 E1000EState *s = E1000E(dev);
518
519 trace_e1000e_cb_qdev_reset();
520
521 e1000e_core_reset(&s->core);
522
523 if (s->init_vet) {
524 s->core.mac[VET] = ETH_P_VLAN;
525 }
526}
527
528static int e1000e_pre_save(void *opaque)
529{
530 E1000EState *s = opaque;
531
532 trace_e1000e_cb_pre_save();
533
534 e1000e_core_pre_save(&s->core);
535
536 return 0;
537}
538
539static int e1000e_post_load(void *opaque, int version_id)
540{
541 E1000EState *s = opaque;
542
543 trace_e1000e_cb_post_load();
544
545 if ((s->subsys != s->subsys_used) ||
546 (s->subsys_ven != s->subsys_ven_used)) {
547 fprintf(stderr,
548 "ERROR: Cannot migrate while device properties "
549 "(subsys/subsys_ven) differ");
550 return -1;
551 }
552
553 return e1000e_core_post_load(&s->core);
554}
555
556static const VMStateDescription e1000e_vmstate_tx = {
557 .name = "e1000e-tx",
558 .version_id = 1,
559 .minimum_version_id = 1,
560 .fields = (VMStateField[]) {
561 VMSTATE_UINT8(sum_needed, struct e1000e_tx),
562 VMSTATE_UINT8(props.ipcss, struct e1000e_tx),
563 VMSTATE_UINT8(props.ipcso, struct e1000e_tx),
564 VMSTATE_UINT16(props.ipcse, struct e1000e_tx),
565 VMSTATE_UINT8(props.tucss, struct e1000e_tx),
566 VMSTATE_UINT8(props.tucso, struct e1000e_tx),
567 VMSTATE_UINT16(props.tucse, struct e1000e_tx),
568 VMSTATE_UINT8(props.hdr_len, struct e1000e_tx),
569 VMSTATE_UINT16(props.mss, struct e1000e_tx),
570 VMSTATE_UINT32(props.paylen, struct e1000e_tx),
571 VMSTATE_INT8(props.ip, struct e1000e_tx),
572 VMSTATE_INT8(props.tcp, struct e1000e_tx),
573 VMSTATE_BOOL(props.tse, struct e1000e_tx),
574 VMSTATE_BOOL(cptse, struct e1000e_tx),
575 VMSTATE_BOOL(skip_cp, struct e1000e_tx),
576 VMSTATE_END_OF_LIST()
577 }
578};
579
580static const VMStateDescription e1000e_vmstate_intr_timer = {
581 .name = "e1000e-intr-timer",
582 .version_id = 1,
583 .minimum_version_id = 1,
584 .fields = (VMStateField[]) {
585 VMSTATE_TIMER_PTR(timer, E1000IntrDelayTimer),
586 VMSTATE_BOOL(running, E1000IntrDelayTimer),
587 VMSTATE_END_OF_LIST()
588 }
589};
590
591#define VMSTATE_E1000E_INTR_DELAY_TIMER(_f, _s) \
592 VMSTATE_STRUCT(_f, _s, 0, \
593 e1000e_vmstate_intr_timer, E1000IntrDelayTimer)
594
595#define VMSTATE_E1000E_INTR_DELAY_TIMER_ARRAY(_f, _s, _num) \
596 VMSTATE_STRUCT_ARRAY(_f, _s, _num, 0, \
597 e1000e_vmstate_intr_timer, E1000IntrDelayTimer)
598
599static const VMStateDescription e1000e_vmstate = {
600 .name = "e1000e",
601 .version_id = 1,
602 .minimum_version_id = 1,
603 .pre_save = e1000e_pre_save,
604 .post_load = e1000e_post_load,
605 .fields = (VMStateField[]) {
606 VMSTATE_PCI_DEVICE(parent_obj, E1000EState),
607 VMSTATE_MSIX(parent_obj, E1000EState),
608
609 VMSTATE_UINT32(ioaddr, E1000EState),
610 VMSTATE_UINT32(core.rxbuf_min_shift, E1000EState),
611 VMSTATE_UINT8(core.rx_desc_len, E1000EState),
612 VMSTATE_UINT32_ARRAY(core.rxbuf_sizes, E1000EState,
613 E1000_PSRCTL_BUFFS_PER_DESC),
614 VMSTATE_UINT32(core.rx_desc_buf_size, E1000EState),
615 VMSTATE_UINT16_ARRAY(core.eeprom, E1000EState, E1000E_EEPROM_SIZE),
616 VMSTATE_UINT16_2DARRAY(core.phy, E1000EState,
617 E1000E_PHY_PAGES, E1000E_PHY_PAGE_SIZE),
618 VMSTATE_UINT32_ARRAY(core.mac, E1000EState, E1000E_MAC_SIZE),
619 VMSTATE_UINT8_ARRAY(core.permanent_mac, E1000EState, ETH_ALEN),
620
621 VMSTATE_UINT32(core.delayed_causes, E1000EState),
622
623 VMSTATE_UINT16(subsys, E1000EState),
624 VMSTATE_UINT16(subsys_ven, E1000EState),
625
626 VMSTATE_E1000E_INTR_DELAY_TIMER(core.rdtr, E1000EState),
627 VMSTATE_E1000E_INTR_DELAY_TIMER(core.radv, E1000EState),
628 VMSTATE_E1000E_INTR_DELAY_TIMER(core.raid, E1000EState),
629 VMSTATE_E1000E_INTR_DELAY_TIMER(core.tadv, E1000EState),
630 VMSTATE_E1000E_INTR_DELAY_TIMER(core.tidv, E1000EState),
631
632 VMSTATE_E1000E_INTR_DELAY_TIMER(core.itr, E1000EState),
633 VMSTATE_BOOL(core.itr_intr_pending, E1000EState),
634
635 VMSTATE_E1000E_INTR_DELAY_TIMER_ARRAY(core.eitr, E1000EState,
636 E1000E_MSIX_VEC_NUM),
637 VMSTATE_BOOL_ARRAY(core.eitr_intr_pending, E1000EState,
638 E1000E_MSIX_VEC_NUM),
639
640 VMSTATE_UINT32(core.itr_guest_value, E1000EState),
641 VMSTATE_UINT32_ARRAY(core.eitr_guest_value, E1000EState,
642 E1000E_MSIX_VEC_NUM),
643
644 VMSTATE_UINT16(core.vet, E1000EState),
645
646 VMSTATE_STRUCT_ARRAY(core.tx, E1000EState, E1000E_NUM_QUEUES, 0,
647 e1000e_vmstate_tx, struct e1000e_tx),
648 VMSTATE_END_OF_LIST()
649 }
650};
651
652static PropertyInfo e1000e_prop_disable_vnet,
653 e1000e_prop_subsys_ven,
654 e1000e_prop_subsys;
655
656static Property e1000e_properties[] = {
657 DEFINE_NIC_PROPERTIES(E1000EState, conf),
658 DEFINE_PROP_SIGNED("disable_vnet_hdr", E1000EState, disable_vnet, false,
659 e1000e_prop_disable_vnet, bool),
660 DEFINE_PROP_SIGNED("subsys_ven", E1000EState, subsys_ven,
661 PCI_VENDOR_ID_INTEL,
662 e1000e_prop_subsys_ven, uint16_t),
663 DEFINE_PROP_SIGNED("subsys", E1000EState, subsys, 0,
664 e1000e_prop_subsys, uint16_t),
665 DEFINE_PROP_BOOL("init-vet", E1000EState, init_vet, true),
666 DEFINE_PROP_END_OF_LIST(),
667};
668
669static void e1000e_class_init(ObjectClass *class, void *data)
670{
671 DeviceClass *dc = DEVICE_CLASS(class);
672 PCIDeviceClass *c = PCI_DEVICE_CLASS(class);
673
674 c->realize = e1000e_pci_realize;
675 c->exit = e1000e_pci_uninit;
676 c->vendor_id = PCI_VENDOR_ID_INTEL;
677 c->device_id = E1000_DEV_ID_82574L;
678 c->revision = 0;
679 c->romfile = "efi-e1000e.rom";
680 c->class_id = PCI_CLASS_NETWORK_ETHERNET;
681
682 dc->desc = "Intel 82574L GbE Controller";
683 dc->reset = e1000e_qdev_reset;
684 dc->vmsd = &e1000e_vmstate;
685
686 e1000e_prop_disable_vnet = qdev_prop_uint8;
687 e1000e_prop_disable_vnet.description = "Do not use virtio headers, "
688 "perform SW offloads emulation "
689 "instead";
690
691 e1000e_prop_subsys_ven = qdev_prop_uint16;
692 e1000e_prop_subsys_ven.description = "PCI device Subsystem Vendor ID";
693
694 e1000e_prop_subsys = qdev_prop_uint16;
695 e1000e_prop_subsys.description = "PCI device Subsystem ID";
696
697 device_class_set_props(dc, e1000e_properties);
698 set_bit(DEVICE_CATEGORY_NETWORK, dc->categories);
699}
700
701static void e1000e_instance_init(Object *obj)
702{
703 E1000EState *s = E1000E(obj);
704 device_add_bootindex_property(obj, &s->conf.bootindex,
705 "bootindex", "/ethernet-phy@0",
706 DEVICE(obj));
707}
708
709static const TypeInfo e1000e_info = {
710 .name = TYPE_E1000E,
711 .parent = TYPE_PCI_DEVICE,
712 .instance_size = sizeof(E1000EState),
713 .class_init = e1000e_class_init,
714 .instance_init = e1000e_instance_init,
715 .interfaces = (InterfaceInfo[]) {
716 { INTERFACE_PCIE_DEVICE },
717 { }
718 },
719};
720
721static void e1000e_register_types(void)
722{
723 type_register_static(&e1000e_info);
724}
725
726type_init(e1000e_register_types)
727
