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27#include "qemu/osdep.h"
28#include "hw/i386/pc.h"
29#include "hw/irq.h"
30#include "qapi/error.h"
31#include "qemu/error-report.h"
32#include "qemu/timer.h"
33#include "hw/timer/hpet.h"
34#include "hw/sysbus.h"
35#include "hw/rtc/mc146818rtc.h"
36#include "hw/rtc/mc146818rtc_regs.h"
37#include "migration/vmstate.h"
38#include "hw/timer/i8254.h"
39#include "exec/address-spaces.h"
40#include "qom/object.h"
41
42
43#ifdef HPET_DEBUG
44#define DPRINTF printf
45#else
46#define DPRINTF(...)
47#endif
48
49#define HPET_MSI_SUPPORT 0
50
51OBJECT_DECLARE_SIMPLE_TYPE(HPETState, HPET)
52
53struct HPETState;
54typedef struct HPETTimer {
55 uint8_t tn;
56 QEMUTimer *qemu_timer;
57 struct HPETState *state;
58
59 uint64_t config;
60 uint64_t cmp;
61 uint64_t fsb;
62
63 uint64_t period;
64 uint8_t wrap_flag;
65
66
67} HPETTimer;
68
69struct HPETState {
70
71 SysBusDevice parent_obj;
72
73
74 MemoryRegion iomem;
75 uint64_t hpet_offset;
76 bool hpet_offset_saved;
77 qemu_irq irqs[HPET_NUM_IRQ_ROUTES];
78 uint32_t flags;
79 uint8_t rtc_irq_level;
80 qemu_irq pit_enabled;
81 uint8_t num_timers;
82 uint32_t intcap;
83 HPETTimer timer[HPET_MAX_TIMERS];
84
85
86 uint64_t capability;
87 uint64_t config;
88 uint64_t isr;
89 uint64_t hpet_counter;
90 uint8_t hpet_id;
91};
92
93static uint32_t hpet_in_legacy_mode(HPETState *s)
94{
95 return s->config & HPET_CFG_LEGACY;
96}
97
98static uint32_t timer_int_route(struct HPETTimer *timer)
99{
100 return (timer->config & HPET_TN_INT_ROUTE_MASK) >> HPET_TN_INT_ROUTE_SHIFT;
101}
102
103static uint32_t timer_fsb_route(HPETTimer *t)
104{
105 return t->config & HPET_TN_FSB_ENABLE;
106}
107
108static uint32_t hpet_enabled(HPETState *s)
109{
110 return s->config & HPET_CFG_ENABLE;
111}
112
113static uint32_t timer_is_periodic(HPETTimer *t)
114{
115 return t->config & HPET_TN_PERIODIC;
116}
117
118static uint32_t timer_enabled(HPETTimer *t)
119{
120 return t->config & HPET_TN_ENABLE;
121}
122
123static uint32_t hpet_time_after(uint64_t a, uint64_t b)
124{
125 return ((int32_t)(b - a) < 0);
126}
127
128static uint32_t hpet_time_after64(uint64_t a, uint64_t b)
129{
130 return ((int64_t)(b - a) < 0);
131}
132
133static uint64_t ticks_to_ns(uint64_t value)
134{
135 return value * HPET_CLK_PERIOD;
136}
137
138static uint64_t ns_to_ticks(uint64_t value)
139{
140 return value / HPET_CLK_PERIOD;
141}
142
143static uint64_t hpet_fixup_reg(uint64_t new, uint64_t old, uint64_t mask)
144{
145 new &= mask;
146 new |= old & ~mask;
147 return new;
148}
149
150static int activating_bit(uint64_t old, uint64_t new, uint64_t mask)
151{
152 return (!(old & mask) && (new & mask));
153}
154
155static int deactivating_bit(uint64_t old, uint64_t new, uint64_t mask)
156{
157 return ((old & mask) && !(new & mask));
158}
159
160static uint64_t hpet_get_ticks(HPETState *s)
161{
162 return ns_to_ticks(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + s->hpet_offset);
163}
164
165
166
167
168static inline uint64_t hpet_calculate_diff(HPETTimer *t, uint64_t current)
169{
170
171 if (t->config & HPET_TN_32BIT) {
172 uint32_t diff, cmp;
173
174 cmp = (uint32_t)t->cmp;
175 diff = cmp - (uint32_t)current;
176 diff = (int32_t)diff > 0 ? diff : (uint32_t)1;
177 return (uint64_t)diff;
178 } else {
179 uint64_t diff, cmp;
180
181 cmp = t->cmp;
182 diff = cmp - current;
183 diff = (int64_t)diff > 0 ? diff : (uint64_t)1;
184 return diff;
185 }
186}
187
188static void update_irq(struct HPETTimer *timer, int set)
189{
190 uint64_t mask;
191 HPETState *s;
192 int route;
193
194 if (timer->tn <= 1 && hpet_in_legacy_mode(timer->state)) {
195
196
197
198
199 route = (timer->tn == 0) ? 0 : RTC_ISA_IRQ;
200 } else {
201 route = timer_int_route(timer);
202 }
203 s = timer->state;
204 mask = 1 << timer->tn;
205 if (!set || !timer_enabled(timer) || !hpet_enabled(timer->state)) {
206 s->isr &= ~mask;
207 if (!timer_fsb_route(timer)) {
208 qemu_irq_lower(s->irqs[route]);
209 }
210 } else if (timer_fsb_route(timer)) {
211 address_space_stl_le(&address_space_memory, timer->fsb >> 32,
212 timer->fsb & 0xffffffff, MEMTXATTRS_UNSPECIFIED,
213 NULL);
214 } else if (timer->config & HPET_TN_TYPE_LEVEL) {
215 s->isr |= mask;
216 qemu_irq_raise(s->irqs[route]);
217 } else {
218 s->isr &= ~mask;
219 qemu_irq_pulse(s->irqs[route]);
220 }
221}
222
223static int hpet_pre_save(void *opaque)
224{
225 HPETState *s = opaque;
226
227
228 if (hpet_enabled(s)) {
229 s->hpet_counter = hpet_get_ticks(s);
230 }
231
232 return 0;
233}
234
235static int hpet_pre_load(void *opaque)
236{
237 HPETState *s = opaque;
238
239
240 s->num_timers = HPET_MIN_TIMERS;
241 return 0;
242}
243
244static bool hpet_validate_num_timers(void *opaque, int version_id)
245{
246 HPETState *s = opaque;
247
248 if (s->num_timers < HPET_MIN_TIMERS) {
249 return false;
250 } else if (s->num_timers > HPET_MAX_TIMERS) {
251 return false;
252 }
253 return true;
254}
255
256static int hpet_post_load(void *opaque, int version_id)
257{
258 HPETState *s = opaque;
259
260
261 if (!s->hpet_offset_saved) {
262 s->hpet_offset = ticks_to_ns(s->hpet_counter)
263 - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
264 }
265
266
267 s->capability &= ~HPET_ID_NUM_TIM_MASK;
268 s->capability |= (s->num_timers - 1) << HPET_ID_NUM_TIM_SHIFT;
269 hpet_cfg.hpet[s->hpet_id].event_timer_block_id = (uint32_t)s->capability;
270
271
272 s->flags &= ~(1 << HPET_MSI_SUPPORT);
273 if (s->timer[0].config & HPET_TN_FSB_CAP) {
274 s->flags |= 1 << HPET_MSI_SUPPORT;
275 }
276 return 0;
277}
278
279static bool hpet_offset_needed(void *opaque)
280{
281 HPETState *s = opaque;
282
283 return hpet_enabled(s) && s->hpet_offset_saved;
284}
285
286static bool hpet_rtc_irq_level_needed(void *opaque)
287{
288 HPETState *s = opaque;
289
290 return s->rtc_irq_level != 0;
291}
292
293static const VMStateDescription vmstate_hpet_rtc_irq_level = {
294 .name = "hpet/rtc_irq_level",
295 .version_id = 1,
296 .minimum_version_id = 1,
297 .needed = hpet_rtc_irq_level_needed,
298 .fields = (VMStateField[]) {
299 VMSTATE_UINT8(rtc_irq_level, HPETState),
300 VMSTATE_END_OF_LIST()
301 }
302};
303
304static const VMStateDescription vmstate_hpet_offset = {
305 .name = "hpet/offset",
306 .version_id = 1,
307 .minimum_version_id = 1,
308 .needed = hpet_offset_needed,
309 .fields = (VMStateField[]) {
310 VMSTATE_UINT64(hpet_offset, HPETState),
311 VMSTATE_END_OF_LIST()
312 }
313};
314
315static const VMStateDescription vmstate_hpet_timer = {
316 .name = "hpet_timer",
317 .version_id = 1,
318 .minimum_version_id = 1,
319 .fields = (VMStateField[]) {
320 VMSTATE_UINT8(tn, HPETTimer),
321 VMSTATE_UINT64(config, HPETTimer),
322 VMSTATE_UINT64(cmp, HPETTimer),
323 VMSTATE_UINT64(fsb, HPETTimer),
324 VMSTATE_UINT64(period, HPETTimer),
325 VMSTATE_UINT8(wrap_flag, HPETTimer),
326 VMSTATE_TIMER_PTR(qemu_timer, HPETTimer),
327 VMSTATE_END_OF_LIST()
328 }
329};
330
331static const VMStateDescription vmstate_hpet = {
332 .name = "hpet",
333 .version_id = 2,
334 .minimum_version_id = 1,
335 .pre_save = hpet_pre_save,
336 .pre_load = hpet_pre_load,
337 .post_load = hpet_post_load,
338 .fields = (VMStateField[]) {
339 VMSTATE_UINT64(config, HPETState),
340 VMSTATE_UINT64(isr, HPETState),
341 VMSTATE_UINT64(hpet_counter, HPETState),
342 VMSTATE_UINT8_V(num_timers, HPETState, 2),
343 VMSTATE_VALIDATE("num_timers in range", hpet_validate_num_timers),
344 VMSTATE_STRUCT_VARRAY_UINT8(timer, HPETState, num_timers, 0,
345 vmstate_hpet_timer, HPETTimer),
346 VMSTATE_END_OF_LIST()
347 },
348 .subsections = (const VMStateDescription*[]) {
349 &vmstate_hpet_rtc_irq_level,
350 &vmstate_hpet_offset,
351 NULL
352 }
353};
354
355static void hpet_arm(HPETTimer *t, uint64_t ticks)
356{
357 if (ticks < ns_to_ticks(INT64_MAX / 2)) {
358 timer_mod(t->qemu_timer,
359 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + ticks_to_ns(ticks));
360 } else {
361 timer_del(t->qemu_timer);
362 }
363}
364
365
366
367
368static void hpet_timer(void *opaque)
369{
370 HPETTimer *t = opaque;
371 uint64_t diff;
372
373 uint64_t period = t->period;
374 uint64_t cur_tick = hpet_get_ticks(t->state);
375
376 if (timer_is_periodic(t) && period != 0) {
377 if (t->config & HPET_TN_32BIT) {
378 while (hpet_time_after(cur_tick, t->cmp)) {
379 t->cmp = (uint32_t)(t->cmp + t->period);
380 }
381 } else {
382 while (hpet_time_after64(cur_tick, t->cmp)) {
383 t->cmp += period;
384 }
385 }
386 diff = hpet_calculate_diff(t, cur_tick);
387 hpet_arm(t, diff);
388 } else if (t->config & HPET_TN_32BIT && !timer_is_periodic(t)) {
389 if (t->wrap_flag) {
390 diff = hpet_calculate_diff(t, cur_tick);
391 hpet_arm(t, diff);
392 t->wrap_flag = 0;
393 }
394 }
395 update_irq(t, 1);
396}
397
398static void hpet_set_timer(HPETTimer *t)
399{
400 uint64_t diff;
401 uint32_t wrap_diff;
402 uint64_t cur_tick = hpet_get_ticks(t->state);
403
404
405 t->wrap_flag = 0;
406 diff = hpet_calculate_diff(t, cur_tick);
407
408
409
410
411 if (t->config & HPET_TN_32BIT && !timer_is_periodic(t)) {
412 wrap_diff = 0xffffffff - (uint32_t)cur_tick;
413 if (wrap_diff < (uint32_t)diff) {
414 diff = wrap_diff;
415 t->wrap_flag = 1;
416 }
417 }
418 hpet_arm(t, diff);
419}
420
421static void hpet_del_timer(HPETTimer *t)
422{
423 timer_del(t->qemu_timer);
424 update_irq(t, 0);
425}
426
427static uint64_t hpet_ram_read(void *opaque, hwaddr addr,
428 unsigned size)
429{
430 HPETState *s = opaque;
431 uint64_t cur_tick, index;
432
433 DPRINTF("qemu: Enter hpet_ram_readl at %" PRIx64 "\n", addr);
434 index = addr;
435
436 if (index >= 0x100 && index <= 0x3ff) {
437 uint8_t timer_id = (addr - 0x100) / 0x20;
438 HPETTimer *timer = &s->timer[timer_id];
439
440 if (timer_id > s->num_timers) {
441 DPRINTF("qemu: timer id out of range\n");
442 return 0;
443 }
444
445 switch ((addr - 0x100) % 0x20) {
446 case HPET_TN_CFG:
447 return timer->config;
448 case HPET_TN_CFG + 4:
449 return timer->config >> 32;
450 case HPET_TN_CMP:
451 return timer->cmp;
452 case HPET_TN_CMP + 4:
453 return timer->cmp >> 32;
454 case HPET_TN_ROUTE:
455 return timer->fsb;
456 case HPET_TN_ROUTE + 4:
457 return timer->fsb >> 32;
458 default:
459 DPRINTF("qemu: invalid hpet_ram_readl\n");
460 break;
461 }
462 } else {
463 switch (index) {
464 case HPET_ID:
465 return s->capability;
466 case HPET_PERIOD:
467 return s->capability >> 32;
468 case HPET_CFG:
469 return s->config;
470 case HPET_CFG + 4:
471 DPRINTF("qemu: invalid HPET_CFG + 4 hpet_ram_readl\n");
472 return 0;
473 case HPET_COUNTER:
474 if (hpet_enabled(s)) {
475 cur_tick = hpet_get_ticks(s);
476 } else {
477 cur_tick = s->hpet_counter;
478 }
479 DPRINTF("qemu: reading counter = %" PRIx64 "\n", cur_tick);
480 return cur_tick;
481 case HPET_COUNTER + 4:
482 if (hpet_enabled(s)) {
483 cur_tick = hpet_get_ticks(s);
484 } else {
485 cur_tick = s->hpet_counter;
486 }
487 DPRINTF("qemu: reading counter + 4 = %" PRIx64 "\n", cur_tick);
488 return cur_tick >> 32;
489 case HPET_STATUS:
490 return s->isr;
491 default:
492 DPRINTF("qemu: invalid hpet_ram_readl\n");
493 break;
494 }
495 }
496 return 0;
497}
498
499static void hpet_ram_write(void *opaque, hwaddr addr,
500 uint64_t value, unsigned size)
501{
502 int i;
503 HPETState *s = opaque;
504 uint64_t old_val, new_val, val, index;
505
506 DPRINTF("qemu: Enter hpet_ram_writel at %" PRIx64 " = 0x%" PRIx64 "\n",
507 addr, value);
508 index = addr;
509 old_val = hpet_ram_read(opaque, addr, 4);
510 new_val = value;
511
512
513 if (index >= 0x100 && index <= 0x3ff) {
514 uint8_t timer_id = (addr - 0x100) / 0x20;
515 HPETTimer *timer = &s->timer[timer_id];
516
517 DPRINTF("qemu: hpet_ram_writel timer_id = 0x%x\n", timer_id);
518 if (timer_id > s->num_timers) {
519 DPRINTF("qemu: timer id out of range\n");
520 return;
521 }
522 switch ((addr - 0x100) % 0x20) {
523 case HPET_TN_CFG:
524 DPRINTF("qemu: hpet_ram_writel HPET_TN_CFG\n");
525 if (activating_bit(old_val, new_val, HPET_TN_FSB_ENABLE)) {
526 update_irq(timer, 0);
527 }
528 val = hpet_fixup_reg(new_val, old_val, HPET_TN_CFG_WRITE_MASK);
529 timer->config = (timer->config & 0xffffffff00000000ULL) | val;
530 if (new_val & HPET_TN_32BIT) {
531 timer->cmp = (uint32_t)timer->cmp;
532 timer->period = (uint32_t)timer->period;
533 }
534 if (activating_bit(old_val, new_val, HPET_TN_ENABLE) &&
535 hpet_enabled(s)) {
536 hpet_set_timer(timer);
537 } else if (deactivating_bit(old_val, new_val, HPET_TN_ENABLE)) {
538 hpet_del_timer(timer);
539 }
540 break;
541 case HPET_TN_CFG + 4:
542 DPRINTF("qemu: invalid HPET_TN_CFG+4 write\n");
543 break;
544 case HPET_TN_CMP:
545 DPRINTF("qemu: hpet_ram_writel HPET_TN_CMP\n");
546 if (timer->config & HPET_TN_32BIT) {
547 new_val = (uint32_t)new_val;
548 }
549 if (!timer_is_periodic(timer)
550 || (timer->config & HPET_TN_SETVAL)) {
551 timer->cmp = (timer->cmp & 0xffffffff00000000ULL) | new_val;
552 }
553 if (timer_is_periodic(timer)) {
554
555
556
557
558 new_val &= (timer->config & HPET_TN_32BIT ? ~0u : ~0ull) >> 1;
559 timer->period =
560 (timer->period & 0xffffffff00000000ULL) | new_val;
561 }
562 timer->config &= ~HPET_TN_SETVAL;
563 if (hpet_enabled(s)) {
564 hpet_set_timer(timer);
565 }
566 break;
567 case HPET_TN_CMP + 4:
568 DPRINTF("qemu: hpet_ram_writel HPET_TN_CMP + 4\n");
569 if (!timer_is_periodic(timer)
570 || (timer->config & HPET_TN_SETVAL)) {
571 timer->cmp = (timer->cmp & 0xffffffffULL) | new_val << 32;
572 } else {
573
574
575
576
577 new_val &= (timer->config & HPET_TN_32BIT ? ~0u : ~0ull) >> 1;
578 timer->period =
579 (timer->period & 0xffffffffULL) | new_val << 32;
580 }
581 timer->config &= ~HPET_TN_SETVAL;
582 if (hpet_enabled(s)) {
583 hpet_set_timer(timer);
584 }
585 break;
586 case HPET_TN_ROUTE:
587 timer->fsb = (timer->fsb & 0xffffffff00000000ULL) | new_val;
588 break;
589 case HPET_TN_ROUTE + 4:
590 timer->fsb = (new_val << 32) | (timer->fsb & 0xffffffff);
591 break;
592 default:
593 DPRINTF("qemu: invalid hpet_ram_writel\n");
594 break;
595 }
596 return;
597 } else {
598 switch (index) {
599 case HPET_ID:
600 return;
601 case HPET_CFG:
602 val = hpet_fixup_reg(new_val, old_val, HPET_CFG_WRITE_MASK);
603 s->config = (s->config & 0xffffffff00000000ULL) | val;
604 if (activating_bit(old_val, new_val, HPET_CFG_ENABLE)) {
605
606 s->hpet_offset =
607 ticks_to_ns(s->hpet_counter) - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
608 for (i = 0; i < s->num_timers; i++) {
609 if ((&s->timer[i])->cmp != ~0ULL) {
610 hpet_set_timer(&s->timer[i]);
611 }
612 }
613 } else if (deactivating_bit(old_val, new_val, HPET_CFG_ENABLE)) {
614
615 s->hpet_counter = hpet_get_ticks(s);
616 for (i = 0; i < s->num_timers; i++) {
617 hpet_del_timer(&s->timer[i]);
618 }
619 }
620
621
622 if (activating_bit(old_val, new_val, HPET_CFG_LEGACY)) {
623 qemu_set_irq(s->pit_enabled, 0);
624 qemu_irq_lower(s->irqs[0]);
625 qemu_irq_lower(s->irqs[RTC_ISA_IRQ]);
626 } else if (deactivating_bit(old_val, new_val, HPET_CFG_LEGACY)) {
627 qemu_irq_lower(s->irqs[0]);
628 qemu_set_irq(s->pit_enabled, 1);
629 qemu_set_irq(s->irqs[RTC_ISA_IRQ], s->rtc_irq_level);
630 }
631 break;
632 case HPET_CFG + 4:
633 DPRINTF("qemu: invalid HPET_CFG+4 write\n");
634 break;
635 case HPET_STATUS:
636 val = new_val & s->isr;
637 for (i = 0; i < s->num_timers; i++) {
638 if (val & (1 << i)) {
639 update_irq(&s->timer[i], 0);
640 }
641 }
642 break;
643 case HPET_COUNTER:
644 if (hpet_enabled(s)) {
645 DPRINTF("qemu: Writing counter while HPET enabled!\n");
646 }
647 s->hpet_counter =
648 (s->hpet_counter & 0xffffffff00000000ULL) | value;
649 DPRINTF("qemu: HPET counter written. ctr = 0x%" PRIx64 " -> "
650 "%" PRIx64 "\n", value, s->hpet_counter);
651 break;
652 case HPET_COUNTER + 4:
653 if (hpet_enabled(s)) {
654 DPRINTF("qemu: Writing counter while HPET enabled!\n");
655 }
656 s->hpet_counter =
657 (s->hpet_counter & 0xffffffffULL) | (((uint64_t)value) << 32);
658 DPRINTF("qemu: HPET counter + 4 written. ctr = 0x%" PRIx64 " -> "
659 "%" PRIx64 "\n", value, s->hpet_counter);
660 break;
661 default:
662 DPRINTF("qemu: invalid hpet_ram_writel\n");
663 break;
664 }
665 }
666}
667
668static const MemoryRegionOps hpet_ram_ops = {
669 .read = hpet_ram_read,
670 .write = hpet_ram_write,
671 .valid = {
672 .min_access_size = 4,
673 .max_access_size = 4,
674 },
675 .endianness = DEVICE_NATIVE_ENDIAN,
676};
677
678static void hpet_reset(DeviceState *d)
679{
680 HPETState *s = HPET(d);
681 SysBusDevice *sbd = SYS_BUS_DEVICE(d);
682 int i;
683
684 for (i = 0; i < s->num_timers; i++) {
685 HPETTimer *timer = &s->timer[i];
686
687 hpet_del_timer(timer);
688 timer->cmp = ~0ULL;
689 timer->config = HPET_TN_PERIODIC_CAP | HPET_TN_SIZE_CAP;
690 if (s->flags & (1 << HPET_MSI_SUPPORT)) {
691 timer->config |= HPET_TN_FSB_CAP;
692 }
693
694 timer->config |= (uint64_t)s->intcap << 32;
695 timer->period = 0ULL;
696 timer->wrap_flag = 0;
697 }
698
699 qemu_set_irq(s->pit_enabled, 1);
700 s->hpet_counter = 0ULL;
701 s->hpet_offset = 0ULL;
702 s->config = 0ULL;
703 hpet_cfg.hpet[s->hpet_id].event_timer_block_id = (uint32_t)s->capability;
704 hpet_cfg.hpet[s->hpet_id].address = sbd->mmio[0].addr;
705
706
707 s->rtc_irq_level = 0;
708}
709
710static void hpet_handle_legacy_irq(void *opaque, int n, int level)
711{
712 HPETState *s = HPET(opaque);
713
714 if (n == HPET_LEGACY_PIT_INT) {
715 if (!hpet_in_legacy_mode(s)) {
716 qemu_set_irq(s->irqs[0], level);
717 }
718 } else {
719 s->rtc_irq_level = level;
720 if (!hpet_in_legacy_mode(s)) {
721 qemu_set_irq(s->irqs[RTC_ISA_IRQ], level);
722 }
723 }
724}
725
726static void hpet_init(Object *obj)
727{
728 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
729 HPETState *s = HPET(obj);
730
731
732 memory_region_init_io(&s->iomem, obj, &hpet_ram_ops, s, "hpet", HPET_LEN);
733 sysbus_init_mmio(sbd, &s->iomem);
734}
735
736static void hpet_realize(DeviceState *dev, Error **errp)
737{
738 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
739 HPETState *s = HPET(dev);
740 int i;
741 HPETTimer *timer;
742
743 if (!s->intcap) {
744 warn_report("Hpet's intcap not initialized");
745 }
746 if (hpet_cfg.count == UINT8_MAX) {
747
748 hpet_cfg.count = 0;
749 }
750
751 if (hpet_cfg.count == 8) {
752 error_setg(errp, "Only 8 instances of HPET is allowed");
753 return;
754 }
755
756 s->hpet_id = hpet_cfg.count++;
757
758 for (i = 0; i < HPET_NUM_IRQ_ROUTES; i++) {
759 sysbus_init_irq(sbd, &s->irqs[i]);
760 }
761
762 if (s->num_timers < HPET_MIN_TIMERS) {
763 s->num_timers = HPET_MIN_TIMERS;
764 } else if (s->num_timers > HPET_MAX_TIMERS) {
765 s->num_timers = HPET_MAX_TIMERS;
766 }
767 for (i = 0; i < HPET_MAX_TIMERS; i++) {
768 timer = &s->timer[i];
769 timer->qemu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, hpet_timer, timer);
770 timer->tn = i;
771 timer->state = s;
772 }
773
774
775 s->capability = 0x8086a001ULL;
776 s->capability |= (s->num_timers - 1) << HPET_ID_NUM_TIM_SHIFT;
777 s->capability |= ((uint64_t)(HPET_CLK_PERIOD * FS_PER_NS) << 32);
778
779 qdev_init_gpio_in(dev, hpet_handle_legacy_irq, 2);
780 qdev_init_gpio_out(dev, &s->pit_enabled, 1);
781}
782
783static Property hpet_device_properties[] = {
784 DEFINE_PROP_UINT8("timers", HPETState, num_timers, HPET_MIN_TIMERS),
785 DEFINE_PROP_BIT("msi", HPETState, flags, HPET_MSI_SUPPORT, false),
786 DEFINE_PROP_UINT32(HPET_INTCAP, HPETState, intcap, 0),
787 DEFINE_PROP_BOOL("hpet-offset-saved", HPETState, hpet_offset_saved, true),
788 DEFINE_PROP_END_OF_LIST(),
789};
790
791static void hpet_device_class_init(ObjectClass *klass, void *data)
792{
793 DeviceClass *dc = DEVICE_CLASS(klass);
794
795 dc->realize = hpet_realize;
796 dc->reset = hpet_reset;
797 dc->vmsd = &vmstate_hpet;
798 device_class_set_props(dc, hpet_device_properties);
799}
800
801static const TypeInfo hpet_device_info = {
802 .name = TYPE_HPET,
803 .parent = TYPE_SYS_BUS_DEVICE,
804 .instance_size = sizeof(HPETState),
805 .instance_init = hpet_init,
806 .class_init = hpet_device_class_init,
807};
808
809static void hpet_register_types(void)
810{
811 type_register_static(&hpet_device_info);
812}
813
814type_init(hpet_register_types)
815