LXR qemu/include/hw/rx/rx62n.h

   1/*
   2 * RX62N MCU Object
   3 *
   4 * Datasheet: RX62N Group, RX621 Group User's Manual: Hardware
   5 *            (Rev.1.40 R01UH0033EJ0140)
   6 *
   7 * Copyright (c) 2019 Yoshinori Sato
   8 *
   9 * SPDX-License-Identifier: GPL-2.0-or-later
  10 *
  11 * This program is free software; you can redistribute it and/or modify it
  12 * under the terms and conditions of the GNU General Public License,
  13 * version 2 or later, as published by the Free Software Foundation.
  14 *
  15 * This program is distributed in the hope it will be useful, but WITHOUT
  16 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  17 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  18 * more details.
  19 *
  20 * You should have received a copy of the GNU General Public License along with
  21 * this program.  If not, see <http://www.gnu.org/licenses/>.
  22 */
  23
  24#ifndef HW_RX_RX62N_H
  25#define HW_RX_RX62N_H
  26
  27#include "target/rx/cpu.h"
  28#include "hw/intc/rx_icu.h"
  29#include "hw/timer/renesas_tmr.h"
  30#include "hw/timer/renesas_cmt.h"
  31#include "hw/char/renesas_sci.h"
  32#include "qemu/units.h"
  33#include "qom/object.h"
  34
  35#define TYPE_RX62N_MCU "rx62n-mcu"
  36typedef struct RX62NState RX62NState;
  37DECLARE_INSTANCE_CHECKER(RX62NState, RX62N_MCU,
  38                         TYPE_RX62N_MCU)
  39
  40#define TYPE_R5F562N7_MCU "r5f562n7-mcu"
  41#define TYPE_R5F562N8_MCU "r5f562n8-mcu"
  42
  43#define EXT_CS_BASE         0x01000000
  44#define VECTOR_TABLE_BASE   0xffffff80
  45#define RX62N_CFLASH_BASE   0xfff80000
  46
  47#define RX62N_NR_TMR    2
  48#define RX62N_NR_CMT    2
  49#define RX62N_NR_SCI    6
  50
  51struct RX62NState {
  52    /*< private >*/
  53    DeviceState parent_obj;
  54    /*< public >*/
  55
  56    RXCPU cpu;
  57    RXICUState icu;
  58    RTMRState tmr[RX62N_NR_TMR];
  59    RCMTState cmt[RX62N_NR_CMT];
  60    RSCIState sci[RX62N_NR_SCI];
  61
  62    MemoryRegion *sysmem;
  63    bool kernel;
  64
  65    MemoryRegion iram;
  66    MemoryRegion iomem1;
  67    MemoryRegion d_flash;
  68    MemoryRegion iomem2;
  69    MemoryRegion iomem3;
  70    MemoryRegion c_flash;
  71    qemu_irq irq[NR_IRQS];
  72
  73    /* Input Clock (XTAL) frequency */
  74    uint32_t xtal_freq_hz;
  75    /* Peripheral Module Clock frequency */
  76    uint32_t pclk_freq_hz;
  77};
  78
  79#endif
  80