LXR qemu/tests/tcg/xtensa/test_load

   1#include "macros.inc"
   2
   3test_suite load_store
   4
   5.macro load_ok_test op, type, data, value
   6    .data
   7    .align  4
   81:
   9    \type \data
  10    .previous
  11
  12    reset_ps
  13    set_vector kernel, 0
  14    movi    a3, 1b
  15    addi    a4, a4, 1
  16    mov     a5, a4
  17    \op     a5, a3, 0
  18    movi    a6, \value
  19    assert  eq, a5, a6
  20.endm
  21
  22#if XCHAL_UNALIGNED_LOAD_EXCEPTION
  23.macro load_unaligned_test will_trap, op, type, data, value
  24    .data
  25    .align  4
  26    .byte   0
  271:
  28    \type \data
  29    .previous
  30
  31    reset_ps
  32    .ifeq \will_trap
  33    set_vector kernel, 0
  34    .else
  35    set_vector kernel, 2f
  36    .endif
  37    movi    a3, 1b
  38    addi    a4, a4, 1
  39    mov     a5, a4
  401:
  41    \op     a5, a3, 0
  42    .ifeq \will_trap
  43    movi    a6, \value
  44    assert  eq, a5, a6
  45    .else
  46    test_fail
  472:
  48    rsr     a6, exccause
  49    movi    a7, 9
  50    assert  eq, a6, a7
  51    rsr     a6, epc1
  52    movi    a7, 1b
  53    assert  eq, a6, a7
  54    rsr     a6, excvaddr
  55    assert  eq, a6, a3
  56    assert  eq, a5, a4
  57    .endif
  58    reset_ps
  59.endm
  60#else
  61.macro load_unaligned_test will_trap, op, type, data, value
  62    .data
  63    .align  4
  641:
  65    \type \data
  66    .previous
  67
  68    reset_ps
  69    set_vector kernel, 0
  70    movi    a3, 1b + 1
  71    addi    a4, a4, 1
  72    mov     a5, a4
  73    \op     a5, a3, 0
  74    movi    a6, \value
  75    assert  eq, a5, a6
  76.endm
  77#endif
  78
  79.macro store_ok_test op, type, value
  80    .data
  81    .align  4
  82    .byte   0, 0, 0, 0x55
  831:
  84    \type 0
  852:
  86    .byte   0xaa
  87    .previous
  88
  89    reset_ps
  90    set_vector kernel, 0
  91    movi    a3, 1b
  92    movi    a5, \value
  93    \op     a5, a3, 0
  94    movi    a3, 2b
  95    l8ui    a5, a3, 0
  96    movi    a6, 0xaa
  97    assert  eq, a5, a6
  98    movi    a3, 1b - 1
  99    l8ui    a5, a3, 0
 100    movi    a6, 0x55
 101    assert  eq, a5, a6
 102.endm
 103
 104#if XCHAL_UNALIGNED_STORE_EXCEPTION
 105.macro store_unaligned_test will_trap, op, nop, type, value
 106    .data
 107    .align  4
 108    .byte   0x55
 1091:
 110    \type   0
 1112:
 112    .byte   0xaa
 113    .previous
 114
 115    reset_ps
 116    .ifeq \will_trap
 117    set_vector kernel, 0
 118    .else
 119    set_vector kernel, 4f
 120    .endif
 121    movi    a3, 1b
 122    movi    a5, \value
 1233:
 124    \op     a5, a3, 0
 125    .ifne \will_trap
 126    test_fail
 1274:
 128    rsr     a6, exccause
 129    movi    a7, 9
 130    assert  eq, a6, a7
 131    rsr     a6, epc1
 132    movi    a7, 3b
 133    assert  eq, a6, a7
 134    rsr     a6, excvaddr
 135    assert  eq, a6, a3
 136    l8ui    a5, a3, 0
 137    assert  eqi, a5, 0
 138    .endif
 139    reset_ps
 140    movi    a3, 2b
 141    l8ui    a5, a3, 0
 142    movi    a6, 0xaa
 143    assert  eq, a5, a6
 144    movi    a3, 1b - 1
 145    l8ui    a5, a3, 0
 146    movi    a6, 0x55
 147    assert  eq, a5, a6
 148.endm
 149#else
 150.macro store_unaligned_test will_trap, sop, lop, type, value
 151    .data
 152    .align  4
 153    .byte   0x55
 1541:
 155    \type   0
 156    .previous
 157
 158    reset_ps
 159    set_vector kernel, 0
 160    movi    a3, 1b
 161    movi    a5, \value
 162    \sop    a5, a3, 0
 163    movi    a3, 1b - 1
 164    \lop    a6, a3, 0
 165    assert  eq, a5, a6
 166.endm
 167#endif
 168
 169test load_ok
 170    load_ok_test l16si, .short, 0x00001234, 0x00001234
 171    load_ok_test l16si, .short, 0x000089ab, 0xffff89ab
 172    load_ok_test l16ui, .short, 0x00001234, 0x00001234
 173    load_ok_test l16ui, .short, 0x000089ab, 0x000089ab
 174    load_ok_test l32i,  .word,  0x12345678, 0x12345678
 175#if XCHAL_HAVE_RELEASE_SYNC
 176    load_ok_test l32ai, .word,  0x12345678, 0x12345678
 177#endif
 178test_end
 179
 180#undef WILL_TRAP
 181#if XCHAL_UNALIGNED_LOAD_HW
 182#define WILL_TRAP 0
 183#else
 184#define WILL_TRAP 1
 185#endif
 186
 187test load_unaligned
 188    load_unaligned_test WILL_TRAP, l16si, .short, 0x00001234, 0x00001234
 189    load_unaligned_test WILL_TRAP, l16si, .short, 0x000089ab, 0xffff89ab
 190    load_unaligned_test WILL_TRAP, l16ui, .short, 0x00001234, 0x00001234
 191    load_unaligned_test WILL_TRAP, l16ui, .short, 0x000089ab, 0x000089ab
 192    load_unaligned_test WILL_TRAP, l32i,  .word,  0x12345678, 0x12345678
 193#if XCHAL_HAVE_RELEASE_SYNC
 194    load_unaligned_test 1,         l32ai, .word,  0x12345678, 0x12345678
 195#endif
 196test_end
 197
 198test store_ok
 199    store_ok_test s16i,  .short, 0x00001234
 200    store_ok_test s32i,  .word,  0x12345678
 201#if XCHAL_HAVE_RELEASE_SYNC
 202    store_ok_test s32ri, .word,  0x12345678
 203#endif
 204test_end
 205
 206#undef WILL_TRAP
 207#if XCHAL_UNALIGNED_STORE_HW
 208#define WILL_TRAP 0
 209#else
 210#define WILL_TRAP 1
 211#endif
 212
 213test store_unaligned
 214    store_unaligned_test WILL_TRAP, s16i,  l16ui, .short, 0x00001234
 215    store_unaligned_test WILL_TRAP, s32i,  l32i,  .word,  0x12345678
 216#if XCHAL_HAVE_RELEASE_SYNC
 217    store_unaligned_test 1,         s32ri, l32i,  .word,  0x12345678
 218#endif
 219test_end
 220
 221test_suite_end
 222