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13#include "qemu/osdep.h"
14#include "qemu/units.h"
15#include "qapi/error.h"
16#include "hw/misc/unimp.h"
17#include "hw/arm/aspeed_soc.h"
18#include "hw/char/serial.h"
19#include "qemu/module.h"
20#include "qemu/error-report.h"
21#include "hw/i2c/aspeed_i2c.h"
22#include "net/net.h"
23#include "sysemu/sysemu.h"
24
25#define ASPEED_SOC_IOMEM_SIZE 0x00200000
26
27static const hwaddr aspeed_soc_ast2400_memmap[] = {
28 [ASPEED_DEV_IOMEM] = 0x1E600000,
29 [ASPEED_DEV_FMC] = 0x1E620000,
30 [ASPEED_DEV_SPI1] = 0x1E630000,
31 [ASPEED_DEV_EHCI1] = 0x1E6A1000,
32 [ASPEED_DEV_VIC] = 0x1E6C0000,
33 [ASPEED_DEV_SDMC] = 0x1E6E0000,
34 [ASPEED_DEV_SCU] = 0x1E6E2000,
35 [ASPEED_DEV_HACE] = 0x1E6E3000,
36 [ASPEED_DEV_XDMA] = 0x1E6E7000,
37 [ASPEED_DEV_VIDEO] = 0x1E700000,
38 [ASPEED_DEV_ADC] = 0x1E6E9000,
39 [ASPEED_DEV_SRAM] = 0x1E720000,
40 [ASPEED_DEV_SDHCI] = 0x1E740000,
41 [ASPEED_DEV_GPIO] = 0x1E780000,
42 [ASPEED_DEV_RTC] = 0x1E781000,
43 [ASPEED_DEV_TIMER1] = 0x1E782000,
44 [ASPEED_DEV_WDT] = 0x1E785000,
45 [ASPEED_DEV_PWM] = 0x1E786000,
46 [ASPEED_DEV_LPC] = 0x1E789000,
47 [ASPEED_DEV_IBT] = 0x1E789140,
48 [ASPEED_DEV_I2C] = 0x1E78A000,
49 [ASPEED_DEV_PECI] = 0x1E78B000,
50 [ASPEED_DEV_ETH1] = 0x1E660000,
51 [ASPEED_DEV_ETH2] = 0x1E680000,
52 [ASPEED_DEV_UART1] = 0x1E783000,
53 [ASPEED_DEV_UART2] = 0x1E78D000,
54 [ASPEED_DEV_UART3] = 0x1E78E000,
55 [ASPEED_DEV_UART4] = 0x1E78F000,
56 [ASPEED_DEV_UART5] = 0x1E784000,
57 [ASPEED_DEV_VUART] = 0x1E787000,
58 [ASPEED_DEV_SDRAM] = 0x40000000,
59};
60
61static const hwaddr aspeed_soc_ast2500_memmap[] = {
62 [ASPEED_DEV_IOMEM] = 0x1E600000,
63 [ASPEED_DEV_FMC] = 0x1E620000,
64 [ASPEED_DEV_SPI1] = 0x1E630000,
65 [ASPEED_DEV_SPI2] = 0x1E631000,
66 [ASPEED_DEV_EHCI1] = 0x1E6A1000,
67 [ASPEED_DEV_EHCI2] = 0x1E6A3000,
68 [ASPEED_DEV_VIC] = 0x1E6C0000,
69 [ASPEED_DEV_SDMC] = 0x1E6E0000,
70 [ASPEED_DEV_SCU] = 0x1E6E2000,
71 [ASPEED_DEV_HACE] = 0x1E6E3000,
72 [ASPEED_DEV_XDMA] = 0x1E6E7000,
73 [ASPEED_DEV_ADC] = 0x1E6E9000,
74 [ASPEED_DEV_VIDEO] = 0x1E700000,
75 [ASPEED_DEV_SRAM] = 0x1E720000,
76 [ASPEED_DEV_SDHCI] = 0x1E740000,
77 [ASPEED_DEV_GPIO] = 0x1E780000,
78 [ASPEED_DEV_RTC] = 0x1E781000,
79 [ASPEED_DEV_TIMER1] = 0x1E782000,
80 [ASPEED_DEV_WDT] = 0x1E785000,
81 [ASPEED_DEV_PWM] = 0x1E786000,
82 [ASPEED_DEV_LPC] = 0x1E789000,
83 [ASPEED_DEV_IBT] = 0x1E789140,
84 [ASPEED_DEV_I2C] = 0x1E78A000,
85 [ASPEED_DEV_PECI] = 0x1E78B000,
86 [ASPEED_DEV_ETH1] = 0x1E660000,
87 [ASPEED_DEV_ETH2] = 0x1E680000,
88 [ASPEED_DEV_UART1] = 0x1E783000,
89 [ASPEED_DEV_UART2] = 0x1E78D000,
90 [ASPEED_DEV_UART3] = 0x1E78E000,
91 [ASPEED_DEV_UART4] = 0x1E78F000,
92 [ASPEED_DEV_UART5] = 0x1E784000,
93 [ASPEED_DEV_VUART] = 0x1E787000,
94 [ASPEED_DEV_SDRAM] = 0x80000000,
95};
96
97static const int aspeed_soc_ast2400_irqmap[] = {
98 [ASPEED_DEV_UART1] = 9,
99 [ASPEED_DEV_UART2] = 32,
100 [ASPEED_DEV_UART3] = 33,
101 [ASPEED_DEV_UART4] = 34,
102 [ASPEED_DEV_UART5] = 10,
103 [ASPEED_DEV_VUART] = 8,
104 [ASPEED_DEV_FMC] = 19,
105 [ASPEED_DEV_EHCI1] = 5,
106 [ASPEED_DEV_EHCI2] = 13,
107 [ASPEED_DEV_SDMC] = 0,
108 [ASPEED_DEV_SCU] = 21,
109 [ASPEED_DEV_ADC] = 31,
110 [ASPEED_DEV_GPIO] = 20,
111 [ASPEED_DEV_RTC] = 22,
112 [ASPEED_DEV_TIMER1] = 16,
113 [ASPEED_DEV_TIMER2] = 17,
114 [ASPEED_DEV_TIMER3] = 18,
115 [ASPEED_DEV_TIMER4] = 35,
116 [ASPEED_DEV_TIMER5] = 36,
117 [ASPEED_DEV_TIMER6] = 37,
118 [ASPEED_DEV_TIMER7] = 38,
119 [ASPEED_DEV_TIMER8] = 39,
120 [ASPEED_DEV_WDT] = 27,
121 [ASPEED_DEV_PWM] = 28,
122 [ASPEED_DEV_LPC] = 8,
123 [ASPEED_DEV_I2C] = 12,
124 [ASPEED_DEV_PECI] = 15,
125 [ASPEED_DEV_ETH1] = 2,
126 [ASPEED_DEV_ETH2] = 3,
127 [ASPEED_DEV_XDMA] = 6,
128 [ASPEED_DEV_SDHCI] = 26,
129 [ASPEED_DEV_HACE] = 4,
130};
131
132#define aspeed_soc_ast2500_irqmap aspeed_soc_ast2400_irqmap
133
134static qemu_irq aspeed_soc_ast2400_get_irq(AspeedSoCState *s, int dev)
135{
136 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
137
138 return qdev_get_gpio_in(DEVICE(&s->vic), sc->irqmap[dev]);
139}
140
141static void aspeed_soc_init(Object *obj)
142{
143 AspeedSoCState *s = ASPEED_SOC(obj);
144 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
145 int i;
146 char socname[8];
147 char typename[64];
148
149 if (sscanf(sc->name, "%7s", socname) != 1) {
150 g_assert_not_reached();
151 }
152
153 for (i = 0; i < sc->num_cpus; i++) {
154 object_initialize_child(obj, "cpu[*]", &s->cpu[i], sc->cpu_type);
155 }
156
157 snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname);
158 object_initialize_child(obj, "scu", &s->scu, typename);
159 qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev",
160 sc->silicon_rev);
161 object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu),
162 "hw-strap1");
163 object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu),
164 "hw-strap2");
165 object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu),
166 "hw-prot-key");
167
168 object_initialize_child(obj, "vic", &s->vic, TYPE_ASPEED_VIC);
169
170 object_initialize_child(obj, "rtc", &s->rtc, TYPE_ASPEED_RTC);
171
172 snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname);
173 object_initialize_child(obj, "timerctrl", &s->timerctrl, typename);
174
175 snprintf(typename, sizeof(typename), "aspeed.adc-%s", socname);
176 object_initialize_child(obj, "adc", &s->adc, typename);
177
178 snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname);
179 object_initialize_child(obj, "i2c", &s->i2c, typename);
180
181 object_initialize_child(obj, "peci", &s->peci, TYPE_ASPEED_PECI);
182
183 snprintf(typename, sizeof(typename), "aspeed.fmc-%s", socname);
184 object_initialize_child(obj, "fmc", &s->fmc, typename);
185
186 for (i = 0; i < sc->spis_num; i++) {
187 snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i + 1, socname);
188 object_initialize_child(obj, "spi[*]", &s->spi[i], typename);
189 }
190
191 for (i = 0; i < sc->ehcis_num; i++) {
192 object_initialize_child(obj, "ehci[*]", &s->ehci[i],
193 TYPE_PLATFORM_EHCI);
194 }
195
196 snprintf(typename, sizeof(typename), "aspeed.sdmc-%s", socname);
197 object_initialize_child(obj, "sdmc", &s->sdmc, typename);
198 object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc),
199 "ram-size");
200
201 for (i = 0; i < sc->wdts_num; i++) {
202 snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname);
203 object_initialize_child(obj, "wdt[*]", &s->wdt[i], typename);
204 }
205
206 for (i = 0; i < sc->macs_num; i++) {
207 object_initialize_child(obj, "ftgmac100[*]", &s->ftgmac100[i],
208 TYPE_FTGMAC100);
209 }
210
211 for (i = 0; i < sc->uarts_num; i++) {
212 object_initialize_child(obj, "uart[*]", &s->uart[i], TYPE_SERIAL_MM);
213 }
214
215 snprintf(typename, sizeof(typename), TYPE_ASPEED_XDMA "-%s", socname);
216 object_initialize_child(obj, "xdma", &s->xdma, typename);
217
218 snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname);
219 object_initialize_child(obj, "gpio", &s->gpio, typename);
220
221 object_initialize_child(obj, "sdc", &s->sdhci, TYPE_ASPEED_SDHCI);
222
223 object_property_set_int(OBJECT(&s->sdhci), "num-slots", 2, &error_abort);
224
225
226 for (i = 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) {
227 object_initialize_child(obj, "sdhci[*]", &s->sdhci.slots[i],
228 TYPE_SYSBUS_SDHCI);
229 }
230
231 object_initialize_child(obj, "lpc", &s->lpc, TYPE_ASPEED_LPC);
232
233 snprintf(typename, sizeof(typename), "aspeed.hace-%s", socname);
234 object_initialize_child(obj, "hace", &s->hace, typename);
235
236 object_initialize_child(obj, "iomem", &s->iomem, TYPE_UNIMPLEMENTED_DEVICE);
237 object_initialize_child(obj, "video", &s->video, TYPE_UNIMPLEMENTED_DEVICE);
238}
239
240static void aspeed_soc_realize(DeviceState *dev, Error **errp)
241{
242 int i;
243 AspeedSoCState *s = ASPEED_SOC(dev);
244 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
245 Error *err = NULL;
246 g_autofree char *sram_name = NULL;
247
248
249 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->iomem), "aspeed.io",
250 sc->memmap[ASPEED_DEV_IOMEM],
251 ASPEED_SOC_IOMEM_SIZE);
252
253
254 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->video), "aspeed.video",
255 sc->memmap[ASPEED_DEV_VIDEO], 0x1000);
256
257
258 for (i = 0; i < sc->num_cpus; i++) {
259 object_property_set_link(OBJECT(&s->cpu[i]), "memory",
260 OBJECT(s->memory), &error_abort);
261 if (!qdev_realize(DEVICE(&s->cpu[i]), NULL, errp)) {
262 return;
263 }
264 }
265
266
267 sram_name = g_strdup_printf("aspeed.sram.%d", CPU(&s->cpu[0])->cpu_index);
268 memory_region_init_ram(&s->sram, OBJECT(s), sram_name, sc->sram_size, &err);
269 if (err) {
270 error_propagate(errp, err);
271 return;
272 }
273 memory_region_add_subregion(s->memory,
274 sc->memmap[ASPEED_DEV_SRAM], &s->sram);
275
276
277 if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) {
278 return;
279 }
280 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_DEV_SCU]);
281
282
283 if (!sysbus_realize(SYS_BUS_DEVICE(&s->vic), errp)) {
284 return;
285 }
286 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->vic), 0, sc->memmap[ASPEED_DEV_VIC]);
287 sysbus_connect_irq(SYS_BUS_DEVICE(&s->vic), 0,
288 qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ));
289 sysbus_connect_irq(SYS_BUS_DEVICE(&s->vic), 1,
290 qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ));
291
292
293 if (!sysbus_realize(SYS_BUS_DEVICE(&s->rtc), errp)) {
294 return;
295 }
296 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->rtc), 0, sc->memmap[ASPEED_DEV_RTC]);
297 sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0,
298 aspeed_soc_get_irq(s, ASPEED_DEV_RTC));
299
300
301 object_property_set_link(OBJECT(&s->timerctrl), "scu", OBJECT(&s->scu),
302 &error_abort);
303 if (!sysbus_realize(SYS_BUS_DEVICE(&s->timerctrl), errp)) {
304 return;
305 }
306 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->timerctrl), 0,
307 sc->memmap[ASPEED_DEV_TIMER1]);
308 for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) {
309 qemu_irq irq = aspeed_soc_get_irq(s, ASPEED_DEV_TIMER1 + i);
310 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq);
311 }
312
313
314 if (!sysbus_realize(SYS_BUS_DEVICE(&s->adc), errp)) {
315 return;
316 }
317 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->adc), 0, sc->memmap[ASPEED_DEV_ADC]);
318 sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0,
319 aspeed_soc_get_irq(s, ASPEED_DEV_ADC));
320
321
322 if (!aspeed_soc_uart_realize(s, errp)) {
323 return;
324 }
325
326
327 object_property_set_link(OBJECT(&s->i2c), "dram", OBJECT(s->dram_mr),
328 &error_abort);
329 if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c), errp)) {
330 return;
331 }
332 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_DEV_I2C]);
333 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c), 0,
334 aspeed_soc_get_irq(s, ASPEED_DEV_I2C));
335
336
337 if (!sysbus_realize(SYS_BUS_DEVICE(&s->peci), errp)) {
338 return;
339 }
340 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->peci), 0,
341 sc->memmap[ASPEED_DEV_PECI]);
342 sysbus_connect_irq(SYS_BUS_DEVICE(&s->peci), 0,
343 aspeed_soc_get_irq(s, ASPEED_DEV_PECI));
344
345
346 object_property_set_link(OBJECT(&s->fmc), "dram", OBJECT(s->dram_mr),
347 &error_abort);
348 if (!sysbus_realize(SYS_BUS_DEVICE(&s->fmc), errp)) {
349 return;
350 }
351 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_DEV_FMC]);
352 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 1,
353 ASPEED_SMC_GET_CLASS(&s->fmc)->flash_window_base);
354 sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0,
355 aspeed_soc_get_irq(s, ASPEED_DEV_FMC));
356
357
358 for (i = 0; i < sc->spis_num; i++) {
359 if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) {
360 return;
361 }
362 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 0,
363 sc->memmap[ASPEED_DEV_SPI1 + i]);
364 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 1,
365 ASPEED_SMC_GET_CLASS(&s->spi[i])->flash_window_base);
366 }
367
368
369 for (i = 0; i < sc->ehcis_num; i++) {
370 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ehci[i]), errp)) {
371 return;
372 }
373 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->ehci[i]), 0,
374 sc->memmap[ASPEED_DEV_EHCI1 + i]);
375 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0,
376 aspeed_soc_get_irq(s, ASPEED_DEV_EHCI1 + i));
377 }
378
379
380 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdmc), errp)) {
381 return;
382 }
383 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sdmc), 0,
384 sc->memmap[ASPEED_DEV_SDMC]);
385
386
387 for (i = 0; i < sc->wdts_num; i++) {
388 AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]);
389
390 object_property_set_link(OBJECT(&s->wdt[i]), "scu", OBJECT(&s->scu),
391 &error_abort);
392 if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) {
393 return;
394 }
395 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->wdt[i]), 0,
396 sc->memmap[ASPEED_DEV_WDT] + i * awc->offset);
397 }
398
399
400 if (!aspeed_soc_dram_init(s, errp)) {
401 return;
402 }
403
404
405 for (i = 0; i < sc->macs_num; i++) {
406 object_property_set_bool(OBJECT(&s->ftgmac100[i]), "aspeed", true,
407 &error_abort);
408 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ftgmac100[i]), errp)) {
409 return;
410 }
411 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->ftgmac100[i]), 0,
412 sc->memmap[ASPEED_DEV_ETH1 + i]);
413 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0,
414 aspeed_soc_get_irq(s, ASPEED_DEV_ETH1 + i));
415 }
416
417
418 if (!sysbus_realize(SYS_BUS_DEVICE(&s->xdma), errp)) {
419 return;
420 }
421 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->xdma), 0,
422 sc->memmap[ASPEED_DEV_XDMA]);
423 sysbus_connect_irq(SYS_BUS_DEVICE(&s->xdma), 0,
424 aspeed_soc_get_irq(s, ASPEED_DEV_XDMA));
425
426
427 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) {
428 return;
429 }
430 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->gpio), 0,
431 sc->memmap[ASPEED_DEV_GPIO]);
432 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0,
433 aspeed_soc_get_irq(s, ASPEED_DEV_GPIO));
434
435
436 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), errp)) {
437 return;
438 }
439 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sdhci), 0,
440 sc->memmap[ASPEED_DEV_SDHCI]);
441 sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0,
442 aspeed_soc_get_irq(s, ASPEED_DEV_SDHCI));
443
444
445 if (!sysbus_realize(SYS_BUS_DEVICE(&s->lpc), errp)) {
446 return;
447 }
448 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->lpc), 0, sc->memmap[ASPEED_DEV_LPC]);
449
450
451 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 0,
452 aspeed_soc_get_irq(s, ASPEED_DEV_LPC));
453
454
455
456
457
458
459
460
461
462
463 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_1,
464 qdev_get_gpio_in(DEVICE(&s->lpc), aspeed_lpc_kcs_1));
465
466 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_2,
467 qdev_get_gpio_in(DEVICE(&s->lpc), aspeed_lpc_kcs_2));
468
469 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_3,
470 qdev_get_gpio_in(DEVICE(&s->lpc), aspeed_lpc_kcs_3));
471
472 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_4,
473 qdev_get_gpio_in(DEVICE(&s->lpc), aspeed_lpc_kcs_4));
474
475
476 object_property_set_link(OBJECT(&s->hace), "dram", OBJECT(s->dram_mr),
477 &error_abort);
478 if (!sysbus_realize(SYS_BUS_DEVICE(&s->hace), errp)) {
479 return;
480 }
481 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->hace), 0,
482 sc->memmap[ASPEED_DEV_HACE]);
483 sysbus_connect_irq(SYS_BUS_DEVICE(&s->hace), 0,
484 aspeed_soc_get_irq(s, ASPEED_DEV_HACE));
485}
486static Property aspeed_soc_properties[] = {
487 DEFINE_PROP_LINK("memory", AspeedSoCState, memory, TYPE_MEMORY_REGION,
488 MemoryRegion *),
489 DEFINE_PROP_LINK("dram", AspeedSoCState, dram_mr, TYPE_MEMORY_REGION,
490 MemoryRegion *),
491 DEFINE_PROP_END_OF_LIST(),
492};
493
494static void aspeed_soc_class_init(ObjectClass *oc, void *data)
495{
496 DeviceClass *dc = DEVICE_CLASS(oc);
497
498 dc->realize = aspeed_soc_realize;
499
500 dc->user_creatable = false;
501 device_class_set_props(dc, aspeed_soc_properties);
502}
503
504static const TypeInfo aspeed_soc_type_info = {
505 .name = TYPE_ASPEED_SOC,
506 .parent = TYPE_DEVICE,
507 .instance_size = sizeof(AspeedSoCState),
508 .class_size = sizeof(AspeedSoCClass),
509 .class_init = aspeed_soc_class_init,
510 .abstract = true,
511};
512
513static void aspeed_soc_ast2400_class_init(ObjectClass *oc, void *data)
514{
515 AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc);
516
517 sc->name = "ast2400-a1";
518 sc->cpu_type = ARM_CPU_TYPE_NAME("arm926");
519 sc->silicon_rev = AST2400_A1_SILICON_REV;
520 sc->sram_size = 0x8000;
521 sc->spis_num = 1;
522 sc->ehcis_num = 1;
523 sc->wdts_num = 2;
524 sc->macs_num = 2;
525 sc->uarts_num = 5;
526 sc->irqmap = aspeed_soc_ast2400_irqmap;
527 sc->memmap = aspeed_soc_ast2400_memmap;
528 sc->num_cpus = 1;
529 sc->get_irq = aspeed_soc_ast2400_get_irq;
530}
531
532static const TypeInfo aspeed_soc_ast2400_type_info = {
533 .name = "ast2400-a1",
534 .parent = TYPE_ASPEED_SOC,
535 .instance_init = aspeed_soc_init,
536 .instance_size = sizeof(AspeedSoCState),
537 .class_init = aspeed_soc_ast2400_class_init,
538};
539
540static void aspeed_soc_ast2500_class_init(ObjectClass *oc, void *data)
541{
542 AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc);
543
544 sc->name = "ast2500-a1";
545 sc->cpu_type = ARM_CPU_TYPE_NAME("arm1176");
546 sc->silicon_rev = AST2500_A1_SILICON_REV;
547 sc->sram_size = 0x9000;
548 sc->spis_num = 2;
549 sc->ehcis_num = 2;
550 sc->wdts_num = 3;
551 sc->macs_num = 2;
552 sc->uarts_num = 5;
553 sc->irqmap = aspeed_soc_ast2500_irqmap;
554 sc->memmap = aspeed_soc_ast2500_memmap;
555 sc->num_cpus = 1;
556 sc->get_irq = aspeed_soc_ast2400_get_irq;
557}
558
559static const TypeInfo aspeed_soc_ast2500_type_info = {
560 .name = "ast2500-a1",
561 .parent = TYPE_ASPEED_SOC,
562 .instance_init = aspeed_soc_init,
563 .instance_size = sizeof(AspeedSoCState),
564 .class_init = aspeed_soc_ast2500_class_init,
565};
566static void aspeed_soc_register_types(void)
567{
568 type_register_static(&aspeed_soc_type_info);
569 type_register_static(&aspeed_soc_ast2400_type_info);
570 type_register_static(&aspeed_soc_ast2500_type_info);
571};
572
573type_init(aspeed_soc_register_types);
574
575qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev)
576{
577 return ASPEED_SOC_GET_CLASS(s)->get_irq(s, dev);
578}
579
580bool aspeed_soc_uart_realize(AspeedSoCState *s, Error **errp)
581{
582 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
583 SerialMM *smm;
584
585 for (int i = 0, uart = ASPEED_DEV_UART1; i < sc->uarts_num; i++, uart++) {
586 smm = &s->uart[i];
587
588
589 qdev_prop_set_uint8(DEVICE(smm), "regshift", 2);
590 qdev_prop_set_uint32(DEVICE(smm), "baudbase", 38400);
591 qdev_set_legacy_instance_id(DEVICE(smm), sc->memmap[uart], 2);
592 qdev_prop_set_uint8(DEVICE(smm), "endianness", DEVICE_LITTLE_ENDIAN);
593 if (!sysbus_realize(SYS_BUS_DEVICE(smm), errp)) {
594 return false;
595 }
596
597 sysbus_connect_irq(SYS_BUS_DEVICE(smm), 0, aspeed_soc_get_irq(s, uart));
598 aspeed_mmio_map(s, SYS_BUS_DEVICE(smm), 0, sc->memmap[uart]);
599 }
600
601 return true;
602}
603
604void aspeed_soc_uart_set_chr(AspeedSoCState *s, int dev, Chardev *chr)
605{
606 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
607 int i = dev - ASPEED_DEV_UART1;
608
609 g_assert(0 <= i && i < ARRAY_SIZE(s->uart) && i < sc->uarts_num);
610 qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", chr);
611}
612
613
614
615
616
617bool aspeed_soc_dram_init(AspeedSoCState *s, Error **errp)
618{
619 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
620 ram_addr_t ram_size, max_ram_size;
621
622 ram_size = object_property_get_uint(OBJECT(&s->sdmc), "ram-size",
623 &error_abort);
624 max_ram_size = object_property_get_uint(OBJECT(&s->sdmc), "max-ram-size",
625 &error_abort);
626
627 memory_region_init(&s->dram_container, OBJECT(s), "ram-container",
628 max_ram_size);
629 memory_region_add_subregion(&s->dram_container, 0, s->dram_mr);
630
631
632
633
634
635
636 if (ram_size < max_ram_size) {
637 DeviceState *dev = qdev_new(TYPE_UNIMPLEMENTED_DEVICE);
638
639 qdev_prop_set_string(dev, "name", "ram-empty");
640 qdev_prop_set_uint64(dev, "size", max_ram_size - ram_size);
641 if (!sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), errp)) {
642 return false;
643 }
644
645 memory_region_add_subregion_overlap(&s->dram_container, ram_size,
646 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0), -1000);
647 }
648
649 memory_region_add_subregion(s->memory,
650 sc->memmap[ASPEED_DEV_SDRAM], &s->dram_container);
651 return true;
652}
653
654void aspeed_mmio_map(AspeedSoCState *s, SysBusDevice *dev, int n, hwaddr addr)
655{
656 memory_region_add_subregion(s->memory, addr,
657 sysbus_mmio_get_region(dev, n));
658}
659
660void aspeed_mmio_map_unimplemented(AspeedSoCState *s, SysBusDevice *dev,
661 const char *name, hwaddr addr, uint64_t size)
662{
663 qdev_prop_set_string(DEVICE(dev), "name", name);
664 qdev_prop_set_uint64(DEVICE(dev), "size", size);
665 sysbus_realize(dev, &error_abort);
666
667 memory_region_add_subregion_overlap(s->memory, addr,
668 sysbus_mmio_get_region(dev, 0), -1000);
669}
670
