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19#ifndef HW_ARM_SMMU_COMMON_H
20#define HW_ARM_SMMU_COMMON_H
21
22#include "hw/sysbus.h"
23#include "hw/pci/pci.h"
24#include "qom/object.h"
25
26#define SMMU_PCI_BUS_MAX 256
27#define SMMU_PCI_DEVFN_MAX 256
28#define SMMU_PCI_DEVFN(sid) (sid & 0xFF)
29
30#define SMMU_MAX_VA_BITS 48
31
32
33
34
35typedef enum {
36 SMMU_PTW_ERR_NONE,
37 SMMU_PTW_ERR_WALK_EABT,
38 SMMU_PTW_ERR_TRANSLATION,
39 SMMU_PTW_ERR_ADDR_SIZE,
40 SMMU_PTW_ERR_ACCESS,
41 SMMU_PTW_ERR_PERMISSION,
42} SMMUPTWEventType;
43
44typedef struct SMMUPTWEventInfo {
45 SMMUPTWEventType type;
46 dma_addr_t addr;
47} SMMUPTWEventInfo;
48
49typedef struct SMMUTransTableInfo {
50 bool disabled;
51 uint64_t ttb;
52 uint8_t tsz;
53 uint8_t granule_sz;
54 bool had;
55} SMMUTransTableInfo;
56
57typedef struct SMMUTLBEntry {
58 IOMMUTLBEntry entry;
59 uint8_t level;
60 uint8_t granule;
61} SMMUTLBEntry;
62
63
64
65
66
67
68typedef struct SMMUTransCfg {
69 int stage;
70 bool aa64;
71 bool disabled;
72 bool bypassed;
73 bool aborted;
74 bool record_faults;
75 uint64_t ttb;
76 uint8_t oas;
77 uint8_t tbi;
78 uint16_t asid;
79 SMMUTransTableInfo tt[2];
80 uint32_t iotlb_hits;
81 uint32_t iotlb_misses;
82} SMMUTransCfg;
83
84typedef struct SMMUDevice {
85 void *smmu;
86 PCIBus *bus;
87 int devfn;
88 IOMMUMemoryRegion iommu;
89 AddressSpace as;
90 uint32_t cfg_cache_hits;
91 uint32_t cfg_cache_misses;
92 QLIST_ENTRY(SMMUDevice) next;
93} SMMUDevice;
94
95typedef struct SMMUPciBus {
96 PCIBus *bus;
97 SMMUDevice *pbdev[];
98} SMMUPciBus;
99
100typedef struct SMMUIOTLBKey {
101 uint64_t iova;
102 uint16_t asid;
103 uint8_t tg;
104 uint8_t level;
105} SMMUIOTLBKey;
106
107struct SMMUState {
108
109 SysBusDevice dev;
110 const char *mrtypename;
111 MemoryRegion iomem;
112
113 GHashTable *smmu_pcibus_by_busptr;
114 GHashTable *configs;
115 GHashTable *iotlb;
116 SMMUPciBus *smmu_pcibus_by_bus_num[SMMU_PCI_BUS_MAX];
117 PCIBus *pci_bus;
118 QLIST_HEAD(, SMMUDevice) devices_with_notifiers;
119 uint8_t bus_num;
120 PCIBus *primary_bus;
121};
122
123struct SMMUBaseClass {
124
125 SysBusDeviceClass parent_class;
126
127
128
129 DeviceRealize parent_realize;
130
131};
132
133#define TYPE_ARM_SMMU "arm-smmu"
134OBJECT_DECLARE_TYPE(SMMUState, SMMUBaseClass, ARM_SMMU)
135
136
137SMMUPciBus *smmu_find_smmu_pcibus(SMMUState *s, uint8_t bus_num);
138
139
140static inline uint16_t smmu_get_sid(SMMUDevice *sdev)
141{
142 return PCI_BUILD_BDF(pci_bus_num(sdev->bus), sdev->devfn);
143}
144
145
146
147
148
149int smmu_ptw(SMMUTransCfg *cfg, dma_addr_t iova, IOMMUAccessFlags perm,
150 SMMUTLBEntry *tlbe, SMMUPTWEventInfo *info);
151
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154
155
156SMMUTransTableInfo *select_tt(SMMUTransCfg *cfg, dma_addr_t iova);
157
158
159IOMMUMemoryRegion *smmu_iommu_mr(SMMUState *s, uint32_t sid);
160
161#define SMMU_IOTLB_MAX_SIZE 256
162
163SMMUTLBEntry *smmu_iotlb_lookup(SMMUState *bs, SMMUTransCfg *cfg,
164 SMMUTransTableInfo *tt, hwaddr iova);
165void smmu_iotlb_insert(SMMUState *bs, SMMUTransCfg *cfg, SMMUTLBEntry *entry);
166SMMUIOTLBKey smmu_get_iotlb_key(uint16_t asid, uint64_t iova,
167 uint8_t tg, uint8_t level);
168void smmu_iotlb_inv_all(SMMUState *s);
169void smmu_iotlb_inv_asid(SMMUState *s, uint16_t asid);
170void smmu_iotlb_inv_iova(SMMUState *s, int asid, dma_addr_t iova,
171 uint8_t tg, uint64_t num_pages, uint8_t ttl);
172
173
174void smmu_inv_notifiers_all(SMMUState *s);
175
176
177void smmu_inv_notifiers_mr(IOMMUMemoryRegion *mr);
178
179#endif
180