LXR qemu/target/arm/translate-a32.h

   1/*
   2 *  AArch32 translation, common definitions.
   3 *
   4 * Copyright (c) 2021 Linaro, Ltd.
   5 *
   6 * This library is free software; you can redistribute it and/or
   7 * modify it under the terms of the GNU Lesser General Public
   8 * License as published by the Free Software Foundation; either
   9 * version 2.1 of the License, or (at your option) any later version.
  10 *
  11 * This library is distributed in the hope that it will be useful,
  12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14 * Lesser General Public License for more details.
  15 *
  16 * You should have received a copy of the GNU Lesser General Public
  17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18 */
  19
  20#ifndef TARGET_ARM_TRANSLATE_A32_H
  21#define TARGET_ARM_TRANSLATE_A32_H
  22
  23/* Prototypes for autogenerated disassembler functions */
  24bool disas_m_nocp(DisasContext *dc, uint32_t insn);
  25bool disas_mve(DisasContext *dc, uint32_t insn);
  26bool disas_vfp(DisasContext *s, uint32_t insn);
  27bool disas_vfp_uncond(DisasContext *s, uint32_t insn);
  28bool disas_neon_dp(DisasContext *s, uint32_t insn);
  29bool disas_neon_ls(DisasContext *s, uint32_t insn);
  30bool disas_neon_shared(DisasContext *s, uint32_t insn);
  31
  32void load_reg_var(DisasContext *s, TCGv_i32 var, int reg);
  33void arm_gen_condlabel(DisasContext *s);
  34bool vfp_access_check(DisasContext *s);
  35bool vfp_access_check_m(DisasContext *s, bool skip_context_update);
  36void read_neon_element32(TCGv_i32 dest, int reg, int ele, MemOp memop);
  37void read_neon_element64(TCGv_i64 dest, int reg, int ele, MemOp memop);
  38void write_neon_element32(TCGv_i32 src, int reg, int ele, MemOp memop);
  39void write_neon_element64(TCGv_i64 src, int reg, int ele, MemOp memop);
  40TCGv_i32 add_reg_for_lit(DisasContext *s, int reg, int ofs);
  41void gen_set_cpsr(TCGv_i32 var, uint32_t mask);
  42void gen_set_condexec(DisasContext *s);
  43void gen_update_pc(DisasContext *s, target_long diff);
  44void gen_lookup_tb(DisasContext *s);
  45long vfp_reg_offset(bool dp, unsigned reg);
  46long neon_full_reg_offset(unsigned reg);
  47long neon_element_offset(int reg, int element, MemOp memop);
  48void gen_rev16(TCGv_i32 dest, TCGv_i32 var);
  49void clear_eci_state(DisasContext *s);
  50bool mve_eci_check(DisasContext *s);
  51void mve_update_eci(DisasContext *s);
  52void mve_update_and_store_eci(DisasContext *s);
  53bool mve_skip_vmov(DisasContext *s, int vn, int index, int size);
  54
  55static inline TCGv_i32 load_cpu_offset(int offset)
  56{
  57    TCGv_i32 tmp = tcg_temp_new_i32();
  58    tcg_gen_ld_i32(tmp, cpu_env, offset);
  59    return tmp;
  60}
  61
  62#define load_cpu_field(name) load_cpu_offset(offsetof(CPUARMState, name))
  63
  64/* Load from the low half of a 64-bit field to a TCGv_i32 */
  65#define load_cpu_field_low32(name)                                      \
  66    ({                                                                  \
  67        QEMU_BUILD_BUG_ON(sizeof_field(CPUARMState, name) != 8);        \
  68        load_cpu_offset(offsetoflow32(CPUARMState, name));              \
  69    })
  70
  71void store_cpu_offset(TCGv_i32 var, int offset, int size);
  72
  73#define store_cpu_field(var, name)                              \
  74    store_cpu_offset(var, offsetof(CPUARMState, name),          \
  75                     sizeof_field(CPUARMState, name))
  76
  77#define store_cpu_field_constant(val, name) \
  78    store_cpu_field(tcg_constant_i32(val), name)
  79
  80/* Create a new temporary and set it to the value of a CPU register.  */
  81static inline TCGv_i32 load_reg(DisasContext *s, int reg)
  82{
  83    TCGv_i32 tmp = tcg_temp_new_i32();
  84    load_reg_var(s, tmp, reg);
  85    return tmp;
  86}
  87
  88void store_reg(DisasContext *s, int reg, TCGv_i32 var);
  89
  90void gen_aa32_ld_internal_i32(DisasContext *s, TCGv_i32 val,
  91                              TCGv_i32 a32, int index, MemOp opc);
  92void gen_aa32_st_internal_i32(DisasContext *s, TCGv_i32 val,
  93                              TCGv_i32 a32, int index, MemOp opc);
  94void gen_aa32_ld_internal_i64(DisasContext *s, TCGv_i64 val,
  95                              TCGv_i32 a32, int index, MemOp opc);
  96void gen_aa32_st_internal_i64(DisasContext *s, TCGv_i64 val,
  97                              TCGv_i32 a32, int index, MemOp opc);
  98void gen_aa32_ld_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32,
  99                     int index, MemOp opc);
 100void gen_aa32_st_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32,
 101                     int index, MemOp opc);
 102void gen_aa32_ld_i64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32,
 103                     int index, MemOp opc);
 104void gen_aa32_st_i64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32,
 105                     int index, MemOp opc);
 106
 107#define DO_GEN_LD(SUFF, OPC)                                            \
 108    static inline void gen_aa32_ld##SUFF(DisasContext *s, TCGv_i32 val, \
 109                                         TCGv_i32 a32, int index)       \
 110    {                                                                   \
 111        gen_aa32_ld_i32(s, val, a32, index, OPC);                       \
 112    }
 113
 114#define DO_GEN_ST(SUFF, OPC)                                            \
 115    static inline void gen_aa32_st##SUFF(DisasContext *s, TCGv_i32 val, \
 116                                         TCGv_i32 a32, int index)       \
 117    {                                                                   \
 118        gen_aa32_st_i32(s, val, a32, index, OPC);                       \
 119    }
 120
 121static inline void gen_aa32_ld64(DisasContext *s, TCGv_i64 val,
 122                                 TCGv_i32 a32, int index)
 123{
 124    gen_aa32_ld_i64(s, val, a32, index, MO_UQ);
 125}
 126
 127static inline void gen_aa32_st64(DisasContext *s, TCGv_i64 val,
 128                                 TCGv_i32 a32, int index)
 129{
 130    gen_aa32_st_i64(s, val, a32, index, MO_UQ);
 131}
 132
 133DO_GEN_LD(8u, MO_UB)
 134DO_GEN_LD(16u, MO_UW)
 135DO_GEN_LD(32u, MO_UL)
 136DO_GEN_ST(8, MO_UB)
 137DO_GEN_ST(16, MO_UW)
 138DO_GEN_ST(32, MO_UL)
 139
 140#undef DO_GEN_LD
 141#undef DO_GEN_ST
 142
 143#if defined(CONFIG_USER_ONLY)
 144#define IS_USER(s) 1
 145#else
 146#define IS_USER(s) (s->user)
 147#endif
 148
 149/* Set NZCV flags from the high 4 bits of var.  */
 150#define gen_set_nzcv(var) gen_set_cpsr(var, CPSR_NZCV)
 151
 152/* Swap low and high halfwords.  */
 153static inline void gen_swap_half(TCGv_i32 dest, TCGv_i32 var)
 154{
 155    tcg_gen_rotri_i32(dest, var, 16);
 156}
 157
 158#endif
 159