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20#include "qemu/osdep.h"
21#include "qemu/qemu-print.h"
22#include "qemu/ctype.h"
23#include "qemu/log.h"
24#include "cpu.h"
25#include "pmu.h"
26#include "internals.h"
27#include "time_helper.h"
28#include "exec/exec-all.h"
29#include "qapi/error.h"
30#include "qemu/error-report.h"
31#include "hw/qdev-properties.h"
32#include "migration/vmstate.h"
33#include "fpu/softfloat-helpers.h"
34#include "sysemu/kvm.h"
35#include "kvm_riscv.h"
36
37
38
39#define RISCV_CPU_MARCHID ((QEMU_VERSION_MAJOR << 16) | \
40 (QEMU_VERSION_MINOR << 8) | \
41 (QEMU_VERSION_MICRO))
42#define RISCV_CPU_MIMPID RISCV_CPU_MARCHID
43
44static const char riscv_single_letter_exts[] = "IEMAFDQCPVH";
45
46struct isa_ext_data {
47 const char *name;
48 bool multi_letter;
49 int min_version;
50 int ext_enable_offset;
51};
52
53#define ISA_EXT_DATA_ENTRY(_name, _m_letter, _min_ver, _prop) \
54{#_name, _m_letter, _min_ver, offsetof(struct RISCVCPUConfig, _prop)}
55
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72
73static const struct isa_ext_data isa_edata_arr[] = {
74 ISA_EXT_DATA_ENTRY(h, false, PRIV_VERSION_1_12_0, ext_h),
75 ISA_EXT_DATA_ENTRY(v, false, PRIV_VERSION_1_12_0, ext_v),
76 ISA_EXT_DATA_ENTRY(zicsr, true, PRIV_VERSION_1_10_0, ext_icsr),
77 ISA_EXT_DATA_ENTRY(zifencei, true, PRIV_VERSION_1_10_0, ext_ifencei),
78 ISA_EXT_DATA_ENTRY(zihintpause, true, PRIV_VERSION_1_10_0, ext_zihintpause),
79 ISA_EXT_DATA_ENTRY(zfh, true, PRIV_VERSION_1_12_0, ext_zfh),
80 ISA_EXT_DATA_ENTRY(zfhmin, true, PRIV_VERSION_1_12_0, ext_zfhmin),
81 ISA_EXT_DATA_ENTRY(zfinx, true, PRIV_VERSION_1_12_0, ext_zfinx),
82 ISA_EXT_DATA_ENTRY(zdinx, true, PRIV_VERSION_1_12_0, ext_zdinx),
83 ISA_EXT_DATA_ENTRY(zba, true, PRIV_VERSION_1_12_0, ext_zba),
84 ISA_EXT_DATA_ENTRY(zbb, true, PRIV_VERSION_1_12_0, ext_zbb),
85 ISA_EXT_DATA_ENTRY(zbc, true, PRIV_VERSION_1_12_0, ext_zbc),
86 ISA_EXT_DATA_ENTRY(zbkb, true, PRIV_VERSION_1_12_0, ext_zbkb),
87 ISA_EXT_DATA_ENTRY(zbkc, true, PRIV_VERSION_1_12_0, ext_zbkc),
88 ISA_EXT_DATA_ENTRY(zbkx, true, PRIV_VERSION_1_12_0, ext_zbkx),
89 ISA_EXT_DATA_ENTRY(zbs, true, PRIV_VERSION_1_12_0, ext_zbs),
90 ISA_EXT_DATA_ENTRY(zk, true, PRIV_VERSION_1_12_0, ext_zk),
91 ISA_EXT_DATA_ENTRY(zkn, true, PRIV_VERSION_1_12_0, ext_zkn),
92 ISA_EXT_DATA_ENTRY(zknd, true, PRIV_VERSION_1_12_0, ext_zknd),
93 ISA_EXT_DATA_ENTRY(zkne, true, PRIV_VERSION_1_12_0, ext_zkne),
94 ISA_EXT_DATA_ENTRY(zknh, true, PRIV_VERSION_1_12_0, ext_zknh),
95 ISA_EXT_DATA_ENTRY(zkr, true, PRIV_VERSION_1_12_0, ext_zkr),
96 ISA_EXT_DATA_ENTRY(zks, true, PRIV_VERSION_1_12_0, ext_zks),
97 ISA_EXT_DATA_ENTRY(zksed, true, PRIV_VERSION_1_12_0, ext_zksed),
98 ISA_EXT_DATA_ENTRY(zksh, true, PRIV_VERSION_1_12_0, ext_zksh),
99 ISA_EXT_DATA_ENTRY(zkt, true, PRIV_VERSION_1_12_0, ext_zkt),
100 ISA_EXT_DATA_ENTRY(zve32f, true, PRIV_VERSION_1_12_0, ext_zve32f),
101 ISA_EXT_DATA_ENTRY(zve64f, true, PRIV_VERSION_1_12_0, ext_zve64f),
102 ISA_EXT_DATA_ENTRY(zhinx, true, PRIV_VERSION_1_12_0, ext_zhinx),
103 ISA_EXT_DATA_ENTRY(zhinxmin, true, PRIV_VERSION_1_12_0, ext_zhinxmin),
104 ISA_EXT_DATA_ENTRY(smaia, true, PRIV_VERSION_1_12_0, ext_smaia),
105 ISA_EXT_DATA_ENTRY(ssaia, true, PRIV_VERSION_1_12_0, ext_ssaia),
106 ISA_EXT_DATA_ENTRY(sscofpmf, true, PRIV_VERSION_1_12_0, ext_sscofpmf),
107 ISA_EXT_DATA_ENTRY(sstc, true, PRIV_VERSION_1_12_0, ext_sstc),
108 ISA_EXT_DATA_ENTRY(svinval, true, PRIV_VERSION_1_12_0, ext_svinval),
109 ISA_EXT_DATA_ENTRY(svnapot, true, PRIV_VERSION_1_12_0, ext_svnapot),
110 ISA_EXT_DATA_ENTRY(svpbmt, true, PRIV_VERSION_1_12_0, ext_svpbmt),
111 ISA_EXT_DATA_ENTRY(xventanacondops, true, PRIV_VERSION_1_12_0, ext_XVentanaCondOps),
112};
113
114static bool isa_ext_is_enabled(RISCVCPU *cpu,
115 const struct isa_ext_data *edata)
116{
117 bool *ext_enabled = (void *)&cpu->cfg + edata->ext_enable_offset;
118
119 return *ext_enabled;
120}
121
122static void isa_ext_update_enabled(RISCVCPU *cpu,
123 const struct isa_ext_data *edata, bool en)
124{
125 bool *ext_enabled = (void *)&cpu->cfg + edata->ext_enable_offset;
126
127 *ext_enabled = en;
128}
129
130const char * const riscv_int_regnames[] = {
131 "x0/zero", "x1/ra", "x2/sp", "x3/gp", "x4/tp", "x5/t0", "x6/t1",
132 "x7/t2", "x8/s0", "x9/s1", "x10/a0", "x11/a1", "x12/a2", "x13/a3",
133 "x14/a4", "x15/a5", "x16/a6", "x17/a7", "x18/s2", "x19/s3", "x20/s4",
134 "x21/s5", "x22/s6", "x23/s7", "x24/s8", "x25/s9", "x26/s10", "x27/s11",
135 "x28/t3", "x29/t4", "x30/t5", "x31/t6"
136};
137
138const char * const riscv_int_regnamesh[] = {
139 "x0h/zeroh", "x1h/rah", "x2h/sph", "x3h/gph", "x4h/tph", "x5h/t0h",
140 "x6h/t1h", "x7h/t2h", "x8h/s0h", "x9h/s1h", "x10h/a0h", "x11h/a1h",
141 "x12h/a2h", "x13h/a3h", "x14h/a4h", "x15h/a5h", "x16h/a6h", "x17h/a7h",
142 "x18h/s2h", "x19h/s3h", "x20h/s4h", "x21h/s5h", "x22h/s6h", "x23h/s7h",
143 "x24h/s8h", "x25h/s9h", "x26h/s10h", "x27h/s11h", "x28h/t3h", "x29h/t4h",
144 "x30h/t5h", "x31h/t6h"
145};
146
147const char * const riscv_fpr_regnames[] = {
148 "f0/ft0", "f1/ft1", "f2/ft2", "f3/ft3", "f4/ft4", "f5/ft5",
149 "f6/ft6", "f7/ft7", "f8/fs0", "f9/fs1", "f10/fa0", "f11/fa1",
150 "f12/fa2", "f13/fa3", "f14/fa4", "f15/fa5", "f16/fa6", "f17/fa7",
151 "f18/fs2", "f19/fs3", "f20/fs4", "f21/fs5", "f22/fs6", "f23/fs7",
152 "f24/fs8", "f25/fs9", "f26/fs10", "f27/fs11", "f28/ft8", "f29/ft9",
153 "f30/ft10", "f31/ft11"
154};
155
156static const char * const riscv_excp_names[] = {
157 "misaligned_fetch",
158 "fault_fetch",
159 "illegal_instruction",
160 "breakpoint",
161 "misaligned_load",
162 "fault_load",
163 "misaligned_store",
164 "fault_store",
165 "user_ecall",
166 "supervisor_ecall",
167 "hypervisor_ecall",
168 "machine_ecall",
169 "exec_page_fault",
170 "load_page_fault",
171 "reserved",
172 "store_page_fault",
173 "reserved",
174 "reserved",
175 "reserved",
176 "reserved",
177 "guest_exec_page_fault",
178 "guest_load_page_fault",
179 "reserved",
180 "guest_store_page_fault",
181};
182
183static const char * const riscv_intr_names[] = {
184 "u_software",
185 "s_software",
186 "vs_software",
187 "m_software",
188 "u_timer",
189 "s_timer",
190 "vs_timer",
191 "m_timer",
192 "u_external",
193 "s_external",
194 "vs_external",
195 "m_external",
196 "reserved",
197 "reserved",
198 "reserved",
199 "reserved"
200};
201
202static void register_cpu_props(DeviceState *dev);
203
204const char *riscv_cpu_get_trap_name(target_ulong cause, bool async)
205{
206 if (async) {
207 return (cause < ARRAY_SIZE(riscv_intr_names)) ?
208 riscv_intr_names[cause] : "(unknown)";
209 } else {
210 return (cause < ARRAY_SIZE(riscv_excp_names)) ?
211 riscv_excp_names[cause] : "(unknown)";
212 }
213}
214
215static void set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext)
216{
217 env->misa_mxl_max = env->misa_mxl = mxl;
218 env->misa_ext_mask = env->misa_ext = ext;
219}
220
221static void set_priv_version(CPURISCVState *env, int priv_ver)
222{
223 env->priv_ver = priv_ver;
224}
225
226static void set_vext_version(CPURISCVState *env, int vext_ver)
227{
228 env->vext_ver = vext_ver;
229}
230
231static void riscv_any_cpu_init(Object *obj)
232{
233 CPURISCVState *env = &RISCV_CPU(obj)->env;
234#if defined(TARGET_RISCV32)
235 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVU);
236#elif defined(TARGET_RISCV64)
237 set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU);
238#endif
239 set_priv_version(env, PRIV_VERSION_1_12_0);
240 register_cpu_props(DEVICE(obj));
241}
242
243#if defined(TARGET_RISCV64)
244static void rv64_base_cpu_init(Object *obj)
245{
246 CPURISCVState *env = &RISCV_CPU(obj)->env;
247
248 set_misa(env, MXL_RV64, 0);
249 register_cpu_props(DEVICE(obj));
250
251 set_priv_version(env, PRIV_VERSION_1_12_0);
252}
253
254static void rv64_sifive_u_cpu_init(Object *obj)
255{
256 CPURISCVState *env = &RISCV_CPU(obj)->env;
257 set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
258 set_priv_version(env, PRIV_VERSION_1_10_0);
259}
260
261static void rv64_sifive_e_cpu_init(Object *obj)
262{
263 CPURISCVState *env = &RISCV_CPU(obj)->env;
264 RISCVCPU *cpu = RISCV_CPU(obj);
265
266 set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU);
267 set_priv_version(env, PRIV_VERSION_1_10_0);
268 cpu->cfg.mmu = false;
269}
270
271static void rv128_base_cpu_init(Object *obj)
272{
273 if (qemu_tcg_mttcg_enabled()) {
274
275 error_report("128-bit RISC-V currently does not work with Multi "
276 "Threaded TCG. Please use: -accel tcg,thread=single");
277 exit(EXIT_FAILURE);
278 }
279 CPURISCVState *env = &RISCV_CPU(obj)->env;
280
281 set_misa(env, MXL_RV128, 0);
282 register_cpu_props(DEVICE(obj));
283
284 set_priv_version(env, PRIV_VERSION_1_12_0);
285}
286#else
287static void rv32_base_cpu_init(Object *obj)
288{
289 CPURISCVState *env = &RISCV_CPU(obj)->env;
290
291 set_misa(env, MXL_RV32, 0);
292 register_cpu_props(DEVICE(obj));
293
294 set_priv_version(env, PRIV_VERSION_1_12_0);
295}
296
297static void rv32_sifive_u_cpu_init(Object *obj)
298{
299 CPURISCVState *env = &RISCV_CPU(obj)->env;
300 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
301 set_priv_version(env, PRIV_VERSION_1_10_0);
302}
303
304static void rv32_sifive_e_cpu_init(Object *obj)
305{
306 CPURISCVState *env = &RISCV_CPU(obj)->env;
307 RISCVCPU *cpu = RISCV_CPU(obj);
308
309 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU);
310 set_priv_version(env, PRIV_VERSION_1_10_0);
311 cpu->cfg.mmu = false;
312}
313
314static void rv32_ibex_cpu_init(Object *obj)
315{
316 CPURISCVState *env = &RISCV_CPU(obj)->env;
317 RISCVCPU *cpu = RISCV_CPU(obj);
318
319 set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU);
320 set_priv_version(env, PRIV_VERSION_1_11_0);
321 cpu->cfg.mmu = false;
322 cpu->cfg.epmp = true;
323}
324
325static void rv32_imafcu_nommu_cpu_init(Object *obj)
326{
327 CPURISCVState *env = &RISCV_CPU(obj)->env;
328 RISCVCPU *cpu = RISCV_CPU(obj);
329
330 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU);
331 set_priv_version(env, PRIV_VERSION_1_10_0);
332 cpu->cfg.mmu = false;
333}
334#endif
335
336#if defined(CONFIG_KVM)
337static void riscv_host_cpu_init(Object *obj)
338{
339 CPURISCVState *env = &RISCV_CPU(obj)->env;
340#if defined(TARGET_RISCV32)
341 set_misa(env, MXL_RV32, 0);
342#elif defined(TARGET_RISCV64)
343 set_misa(env, MXL_RV64, 0);
344#endif
345 register_cpu_props(DEVICE(obj));
346}
347#endif
348
349static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model)
350{
351 ObjectClass *oc;
352 char *typename;
353 char **cpuname;
354
355 cpuname = g_strsplit(cpu_model, ",", 1);
356 typename = g_strdup_printf(RISCV_CPU_TYPE_NAME("%s"), cpuname[0]);
357 oc = object_class_by_name(typename);
358 g_strfreev(cpuname);
359 g_free(typename);
360 if (!oc || !object_class_dynamic_cast(oc, TYPE_RISCV_CPU) ||
361 object_class_is_abstract(oc)) {
362 return NULL;
363 }
364 return oc;
365}
366
367static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
368{
369 RISCVCPU *cpu = RISCV_CPU(cs);
370 CPURISCVState *env = &cpu->env;
371 int i;
372
373#if !defined(CONFIG_USER_ONLY)
374 if (riscv_has_ext(env, RVH)) {
375 qemu_fprintf(f, " %s %d\n", "V = ", riscv_cpu_virt_enabled(env));
376 }
377#endif
378 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "pc ", env->pc);
379#ifndef CONFIG_USER_ONLY
380 {
381 static const int dump_csrs[] = {
382 CSR_MHARTID,
383 CSR_MSTATUS,
384 CSR_MSTATUSH,
385 CSR_HSTATUS,
386 CSR_VSSTATUS,
387 CSR_MIP,
388 CSR_MIE,
389 CSR_MIDELEG,
390 CSR_HIDELEG,
391 CSR_MEDELEG,
392 CSR_HEDELEG,
393 CSR_MTVEC,
394 CSR_STVEC,
395 CSR_VSTVEC,
396 CSR_MEPC,
397 CSR_SEPC,
398 CSR_VSEPC,
399 CSR_MCAUSE,
400 CSR_SCAUSE,
401 CSR_VSCAUSE,
402 CSR_MTVAL,
403 CSR_STVAL,
404 CSR_HTVAL,
405 CSR_MTVAL2,
406 CSR_MSCRATCH,
407 CSR_SSCRATCH,
408 CSR_SATP,
409 CSR_MMTE,
410 CSR_UPMBASE,
411 CSR_UPMMASK,
412 CSR_SPMBASE,
413 CSR_SPMMASK,
414 CSR_MPMBASE,
415 CSR_MPMMASK,
416 };
417
418 for (int i = 0; i < ARRAY_SIZE(dump_csrs); ++i) {
419 int csrno = dump_csrs[i];
420 target_ulong val = 0;
421 RISCVException res = riscv_csrrw_debug(env, csrno, &val, 0, 0);
422
423
424
425
426
427 if (res == RISCV_EXCP_NONE) {
428 qemu_fprintf(f, " %-8s " TARGET_FMT_lx "\n",
429 csr_ops[csrno].name, val);
430 }
431 }
432 }
433#endif
434
435 for (i = 0; i < 32; i++) {
436 qemu_fprintf(f, " %-8s " TARGET_FMT_lx,
437 riscv_int_regnames[i], env->gpr[i]);
438 if ((i & 3) == 3) {
439 qemu_fprintf(f, "\n");
440 }
441 }
442 if (flags & CPU_DUMP_FPU) {
443 for (i = 0; i < 32; i++) {
444 qemu_fprintf(f, " %-8s %016" PRIx64,
445 riscv_fpr_regnames[i], env->fpr[i]);
446 if ((i & 3) == 3) {
447 qemu_fprintf(f, "\n");
448 }
449 }
450 }
451}
452
453static void riscv_cpu_set_pc(CPUState *cs, vaddr value)
454{
455 RISCVCPU *cpu = RISCV_CPU(cs);
456 CPURISCVState *env = &cpu->env;
457
458 if (env->xl == MXL_RV32) {
459 env->pc = (int32_t)value;
460 } else {
461 env->pc = value;
462 }
463}
464
465static vaddr riscv_cpu_get_pc(CPUState *cs)
466{
467 RISCVCPU *cpu = RISCV_CPU(cs);
468 CPURISCVState *env = &cpu->env;
469
470
471 if (env->xl == MXL_RV32) {
472 return env->pc & UINT32_MAX;
473 }
474 return env->pc;
475}
476
477static void riscv_cpu_synchronize_from_tb(CPUState *cs,
478 const TranslationBlock *tb)
479{
480 RISCVCPU *cpu = RISCV_CPU(cs);
481 CPURISCVState *env = &cpu->env;
482 RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL);
483
484 if (xl == MXL_RV32) {
485 env->pc = (int32_t)tb_pc(tb);
486 } else {
487 env->pc = tb_pc(tb);
488 }
489}
490
491static bool riscv_cpu_has_work(CPUState *cs)
492{
493#ifndef CONFIG_USER_ONLY
494 RISCVCPU *cpu = RISCV_CPU(cs);
495 CPURISCVState *env = &cpu->env;
496
497
498
499
500 return riscv_cpu_all_pending(env) != 0;
501#else
502 return true;
503#endif
504}
505
506static void riscv_restore_state_to_opc(CPUState *cs,
507 const TranslationBlock *tb,
508 const uint64_t *data)
509{
510 RISCVCPU *cpu = RISCV_CPU(cs);
511 CPURISCVState *env = &cpu->env;
512 RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL);
513
514 if (xl == MXL_RV32) {
515 env->pc = (int32_t)data[0];
516 } else {
517 env->pc = data[0];
518 }
519 env->bins = data[1];
520}
521
522static void riscv_cpu_reset(DeviceState *dev)
523{
524#ifndef CONFIG_USER_ONLY
525 uint8_t iprio;
526 int i, irq, rdzero;
527#endif
528 CPUState *cs = CPU(dev);
529 RISCVCPU *cpu = RISCV_CPU(cs);
530 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu);
531 CPURISCVState *env = &cpu->env;
532
533 mcc->parent_reset(dev);
534#ifndef CONFIG_USER_ONLY
535 env->misa_mxl = env->misa_mxl_max;
536 env->priv = PRV_M;
537 env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV);
538 if (env->misa_mxl > MXL_RV32) {
539
540
541
542
543 env->mstatus = set_field(env->mstatus, MSTATUS64_SXL, env->misa_mxl);
544 env->mstatus = set_field(env->mstatus, MSTATUS64_UXL, env->misa_mxl);
545 if (riscv_has_ext(env, RVH)) {
546 env->vsstatus = set_field(env->vsstatus,
547 MSTATUS64_SXL, env->misa_mxl);
548 env->vsstatus = set_field(env->vsstatus,
549 MSTATUS64_UXL, env->misa_mxl);
550 env->mstatus_hs = set_field(env->mstatus_hs,
551 MSTATUS64_SXL, env->misa_mxl);
552 env->mstatus_hs = set_field(env->mstatus_hs,
553 MSTATUS64_UXL, env->misa_mxl);
554 }
555 }
556 env->mcause = 0;
557 env->miclaim = MIP_SGEIP;
558 env->pc = env->resetvec;
559 env->bins = 0;
560 env->two_stage_lookup = false;
561
562
563 for (i = 0; i < ARRAY_SIZE(env->miprio); i++) {
564 iprio = riscv_cpu_default_priority(i);
565 env->miprio[i] = (i == IRQ_M_EXT) ? 0 : iprio;
566 env->siprio[i] = (i == IRQ_S_EXT) ? 0 : iprio;
567 env->hviprio[i] = 0;
568 }
569 i = 0;
570 while (!riscv_cpu_hviprio_index2irq(i, &irq, &rdzero)) {
571 if (!rdzero) {
572 env->hviprio[irq] = env->miprio[irq];
573 }
574 i++;
575 }
576
577 env->mmte |= (PM_EXT_INITIAL | MMTE_M_PM_CURRENT);
578#endif
579 env->xl = riscv_cpu_mxl(env);
580 riscv_cpu_update_mask(env);
581 cs->exception_index = RISCV_EXCP_NONE;
582 env->load_res = -1;
583 set_default_nan_mode(1, &env->fp_status);
584
585#ifndef CONFIG_USER_ONLY
586 if (riscv_feature(env, RISCV_FEATURE_DEBUG)) {
587 riscv_trigger_init(env);
588 }
589
590 if (kvm_enabled()) {
591 kvm_riscv_reset_vcpu(cpu);
592 }
593#endif
594}
595
596static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info)
597{
598 RISCVCPU *cpu = RISCV_CPU(s);
599
600 switch (riscv_cpu_mxl(&cpu->env)) {
601 case MXL_RV32:
602 info->print_insn = print_insn_riscv32;
603 break;
604 case MXL_RV64:
605 info->print_insn = print_insn_riscv64;
606 break;
607 case MXL_RV128:
608 info->print_insn = print_insn_riscv128;
609 break;
610 default:
611 g_assert_not_reached();
612 }
613}
614
615static void riscv_cpu_realize(DeviceState *dev, Error **errp)
616{
617 CPUState *cs = CPU(dev);
618 RISCVCPU *cpu = RISCV_CPU(dev);
619 CPURISCVState *env = &cpu->env;
620 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev);
621 CPUClass *cc = CPU_CLASS(mcc);
622 int i, priv_version = -1;
623 Error *local_err = NULL;
624
625 cpu_exec_realizefn(cs, &local_err);
626 if (local_err != NULL) {
627 error_propagate(errp, local_err);
628 return;
629 }
630
631 if (cpu->cfg.priv_spec) {
632 if (!g_strcmp0(cpu->cfg.priv_spec, "v1.12.0")) {
633 priv_version = PRIV_VERSION_1_12_0;
634 } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) {
635 priv_version = PRIV_VERSION_1_11_0;
636 } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) {
637 priv_version = PRIV_VERSION_1_10_0;
638 } else {
639 error_setg(errp,
640 "Unsupported privilege spec version '%s'",
641 cpu->cfg.priv_spec);
642 return;
643 }
644 }
645
646 if (priv_version >= PRIV_VERSION_1_10_0) {
647 set_priv_version(env, priv_version);
648 }
649
650
651 for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) {
652 if (isa_ext_is_enabled(cpu, &isa_edata_arr[i]) &&
653 (env->priv_ver < isa_edata_arr[i].min_version)) {
654 isa_ext_update_enabled(cpu, &isa_edata_arr[i], false);
655#ifndef CONFIG_USER_ONLY
656 warn_report("disabling %s extension for hart 0x%lx because "
657 "privilege spec version does not match",
658 isa_edata_arr[i].name, (unsigned long)env->mhartid);
659#else
660 warn_report("disabling %s extension because "
661 "privilege spec version does not match",
662 isa_edata_arr[i].name);
663#endif
664 }
665 }
666
667 if (cpu->cfg.mmu) {
668 riscv_set_feature(env, RISCV_FEATURE_MMU);
669 }
670
671 if (cpu->cfg.pmp) {
672 riscv_set_feature(env, RISCV_FEATURE_PMP);
673
674
675
676
677
678 if (cpu->cfg.epmp) {
679 riscv_set_feature(env, RISCV_FEATURE_EPMP);
680 }
681 }
682
683 if (cpu->cfg.debug) {
684 riscv_set_feature(env, RISCV_FEATURE_DEBUG);
685 }
686
687
688#ifndef CONFIG_USER_ONLY
689 if (cpu->cfg.ext_sstc) {
690 riscv_timer_init(cpu);
691 }
692#endif
693
694
695 switch (env->misa_mxl_max) {
696#ifdef TARGET_RISCV64
697 case MXL_RV64:
698 case MXL_RV128:
699 cc->gdb_core_xml_file = "riscv-64bit-cpu.xml";
700 break;
701#endif
702 case MXL_RV32:
703 cc->gdb_core_xml_file = "riscv-32bit-cpu.xml";
704 break;
705 default:
706 g_assert_not_reached();
707 }
708 assert(env->misa_mxl_max == env->misa_mxl);
709
710
711 if (env->misa_ext == 0) {
712 uint32_t ext = 0;
713
714
715 if (cpu->cfg.ext_g && !(cpu->cfg.ext_i && cpu->cfg.ext_m &&
716 cpu->cfg.ext_a && cpu->cfg.ext_f &&
717 cpu->cfg.ext_d &&
718 cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) {
719 warn_report("Setting G will also set IMAFD_Zicsr_Zifencei");
720 cpu->cfg.ext_i = true;
721 cpu->cfg.ext_m = true;
722 cpu->cfg.ext_a = true;
723 cpu->cfg.ext_f = true;
724 cpu->cfg.ext_d = true;
725 cpu->cfg.ext_icsr = true;
726 cpu->cfg.ext_ifencei = true;
727 }
728
729 if (cpu->cfg.ext_i && cpu->cfg.ext_e) {
730 error_setg(errp,
731 "I and E extensions are incompatible");
732 return;
733 }
734
735 if (!cpu->cfg.ext_i && !cpu->cfg.ext_e) {
736 error_setg(errp,
737 "Either I or E extension must be set");
738 return;
739 }
740
741 if (cpu->cfg.ext_s && !cpu->cfg.ext_u) {
742 error_setg(errp,
743 "Setting S extension without U extension is illegal");
744 return;
745 }
746
747 if (cpu->cfg.ext_h && !cpu->cfg.ext_i) {
748 error_setg(errp,
749 "H depends on an I base integer ISA with 32 x registers");
750 return;
751 }
752
753 if (cpu->cfg.ext_h && !cpu->cfg.ext_s) {
754 error_setg(errp, "H extension implicitly requires S-mode");
755 return;
756 }
757
758 if (cpu->cfg.ext_f && !cpu->cfg.ext_icsr) {
759 error_setg(errp, "F extension requires Zicsr");
760 return;
761 }
762
763 if ((cpu->cfg.ext_zfh || cpu->cfg.ext_zfhmin) && !cpu->cfg.ext_f) {
764 error_setg(errp, "Zfh/Zfhmin extensions require F extension");
765 return;
766 }
767
768 if (cpu->cfg.ext_d && !cpu->cfg.ext_f) {
769 error_setg(errp, "D extension requires F extension");
770 return;
771 }
772
773 if (cpu->cfg.ext_v && !cpu->cfg.ext_d) {
774 error_setg(errp, "V extension requires D extension");
775 return;
776 }
777
778 if ((cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f) && !cpu->cfg.ext_f) {
779 error_setg(errp, "Zve32f/Zve64f extensions require F extension");
780 return;
781 }
782
783
784 if (cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinx ||
785 cpu->cfg.ext_zhinxmin) {
786 cpu->cfg.ext_zfinx = true;
787 }
788
789 if (cpu->cfg.ext_zfinx) {
790 if (!cpu->cfg.ext_icsr) {
791 error_setg(errp, "Zfinx extension requires Zicsr");
792 return;
793 }
794 if (cpu->cfg.ext_f) {
795 error_setg(errp,
796 "Zfinx cannot be supported together with F extension");
797 return;
798 }
799 }
800
801 if (cpu->cfg.ext_zk) {
802 cpu->cfg.ext_zkn = true;
803 cpu->cfg.ext_zkr = true;
804 cpu->cfg.ext_zkt = true;
805 }
806
807 if (cpu->cfg.ext_zkn) {
808 cpu->cfg.ext_zbkb = true;
809 cpu->cfg.ext_zbkc = true;
810 cpu->cfg.ext_zbkx = true;
811 cpu->cfg.ext_zkne = true;
812 cpu->cfg.ext_zknd = true;
813 cpu->cfg.ext_zknh = true;
814 }
815
816 if (cpu->cfg.ext_zks) {
817 cpu->cfg.ext_zbkb = true;
818 cpu->cfg.ext_zbkc = true;
819 cpu->cfg.ext_zbkx = true;
820 cpu->cfg.ext_zksed = true;
821 cpu->cfg.ext_zksh = true;
822 }
823
824 if (cpu->cfg.ext_i) {
825 ext |= RVI;
826 }
827 if (cpu->cfg.ext_e) {
828 ext |= RVE;
829 }
830 if (cpu->cfg.ext_m) {
831 ext |= RVM;
832 }
833 if (cpu->cfg.ext_a) {
834 ext |= RVA;
835 }
836 if (cpu->cfg.ext_f) {
837 ext |= RVF;
838 }
839 if (cpu->cfg.ext_d) {
840 ext |= RVD;
841 }
842 if (cpu->cfg.ext_c) {
843 ext |= RVC;
844 }
845 if (cpu->cfg.ext_s) {
846 ext |= RVS;
847 }
848 if (cpu->cfg.ext_u) {
849 ext |= RVU;
850 }
851 if (cpu->cfg.ext_h) {
852 ext |= RVH;
853 }
854 if (cpu->cfg.ext_v) {
855 int vext_version = VEXT_VERSION_1_00_0;
856 ext |= RVV;
857 if (!is_power_of_2(cpu->cfg.vlen)) {
858 error_setg(errp,
859 "Vector extension VLEN must be power of 2");
860 return;
861 }
862 if (cpu->cfg.vlen > RV_VLEN_MAX || cpu->cfg.vlen < 128) {
863 error_setg(errp,
864 "Vector extension implementation only supports VLEN "
865 "in the range [128, %d]", RV_VLEN_MAX);
866 return;
867 }
868 if (!is_power_of_2(cpu->cfg.elen)) {
869 error_setg(errp,
870 "Vector extension ELEN must be power of 2");
871 return;
872 }
873 if (cpu->cfg.elen > 64 || cpu->cfg.vlen < 8) {
874 error_setg(errp,
875 "Vector extension implementation only supports ELEN "
876 "in the range [8, 64]");
877 return;
878 }
879 if (cpu->cfg.vext_spec) {
880 if (!g_strcmp0(cpu->cfg.vext_spec, "v1.0")) {
881 vext_version = VEXT_VERSION_1_00_0;
882 } else {
883 error_setg(errp,
884 "Unsupported vector spec version '%s'",
885 cpu->cfg.vext_spec);
886 return;
887 }
888 } else {
889 qemu_log("vector version is not specified, "
890 "use the default value v1.0\n");
891 }
892 set_vext_version(env, vext_version);
893 }
894 if (cpu->cfg.ext_j) {
895 ext |= RVJ;
896 }
897
898 set_misa(env, env->misa_mxl, ext);
899 }
900
901#ifndef CONFIG_USER_ONLY
902 if (cpu->cfg.pmu_num) {
903 if (!riscv_pmu_init(cpu, cpu->cfg.pmu_num) && cpu->cfg.ext_sscofpmf) {
904 cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
905 riscv_pmu_timer_cb, cpu);
906 }
907 }
908#endif
909
910 riscv_cpu_register_gdb_regs_for_features(cs);
911
912 qemu_init_vcpu(cs);
913 cpu_reset(cs);
914
915 mcc->parent_realize(dev, errp);
916}
917
918#ifndef CONFIG_USER_ONLY
919static void riscv_cpu_set_irq(void *opaque, int irq, int level)
920{
921 RISCVCPU *cpu = RISCV_CPU(opaque);
922 CPURISCVState *env = &cpu->env;
923
924 if (irq < IRQ_LOCAL_MAX) {
925 switch (irq) {
926 case IRQ_U_SOFT:
927 case IRQ_S_SOFT:
928 case IRQ_VS_SOFT:
929 case IRQ_M_SOFT:
930 case IRQ_U_TIMER:
931 case IRQ_S_TIMER:
932 case IRQ_VS_TIMER:
933 case IRQ_M_TIMER:
934 case IRQ_U_EXT:
935 case IRQ_VS_EXT:
936 case IRQ_M_EXT:
937 if (kvm_enabled()) {
938 kvm_riscv_set_irq(cpu, irq, level);
939 } else {
940 riscv_cpu_update_mip(cpu, 1 << irq, BOOL_TO_MASK(level));
941 }
942 break;
943 case IRQ_S_EXT:
944 if (kvm_enabled()) {
945 kvm_riscv_set_irq(cpu, irq, level);
946 } else {
947 env->external_seip = level;
948 riscv_cpu_update_mip(cpu, 1 << irq,
949 BOOL_TO_MASK(level | env->software_seip));
950 }
951 break;
952 default:
953 g_assert_not_reached();
954 }
955 } else if (irq < (IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX)) {
956
957 if (!riscv_has_ext(env, RVH)) {
958 g_assert_not_reached();
959 }
960
961
962 irq = irq - IRQ_LOCAL_MAX + 1;
963 if (env->geilen < irq) {
964 g_assert_not_reached();
965 }
966
967
968 env->hgeip &= ~((target_ulong)1 << irq);
969 if (level) {
970 env->hgeip |= (target_ulong)1 << irq;
971 }
972
973
974 riscv_cpu_update_mip(cpu, MIP_SGEIP,
975 BOOL_TO_MASK(!!(env->hgeie & env->hgeip)));
976 } else {
977 g_assert_not_reached();
978 }
979}
980#endif
981
982static void riscv_cpu_init(Object *obj)
983{
984 RISCVCPU *cpu = RISCV_CPU(obj);
985
986 cpu->cfg.ext_ifencei = true;
987 cpu->cfg.ext_icsr = true;
988 cpu->cfg.mmu = true;
989 cpu->cfg.pmp = true;
990
991 cpu_set_cpustate_pointers(cpu);
992
993#ifndef CONFIG_USER_ONLY
994 qdev_init_gpio_in(DEVICE(cpu), riscv_cpu_set_irq,
995 IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX);
996#endif
997}
998
999static Property riscv_cpu_extensions[] = {
1000
1001 DEFINE_PROP_BOOL("i", RISCVCPU, cfg.ext_i, true),
1002 DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false),
1003 DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false),
1004 DEFINE_PROP_BOOL("m", RISCVCPU, cfg.ext_m, true),
1005 DEFINE_PROP_BOOL("a", RISCVCPU, cfg.ext_a, true),
1006 DEFINE_PROP_BOOL("f", RISCVCPU, cfg.ext_f, true),
1007 DEFINE_PROP_BOOL("d", RISCVCPU, cfg.ext_d, true),
1008 DEFINE_PROP_BOOL("c", RISCVCPU, cfg.ext_c, true),
1009 DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true),
1010 DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
1011 DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false),
1012 DEFINE_PROP_BOOL("h", RISCVCPU, cfg.ext_h, true),
1013 DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16),
1014 DEFINE_PROP_BOOL("sscofpmf", RISCVCPU, cfg.ext_sscofpmf, false),
1015 DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
1016 DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
1017 DEFINE_PROP_BOOL("Zihintpause", RISCVCPU, cfg.ext_zihintpause, true),
1018 DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false),
1019 DEFINE_PROP_BOOL("Zfhmin", RISCVCPU, cfg.ext_zfhmin, false),
1020 DEFINE_PROP_BOOL("Zve32f", RISCVCPU, cfg.ext_zve32f, false),
1021 DEFINE_PROP_BOOL("Zve64f", RISCVCPU, cfg.ext_zve64f, false),
1022 DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
1023 DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
1024 DEFINE_PROP_BOOL("sstc", RISCVCPU, cfg.ext_sstc, true),
1025
1026 DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
1027 DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec),
1028 DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128),
1029 DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
1030
1031 DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false),
1032 DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false),
1033 DEFINE_PROP_BOOL("svpbmt", RISCVCPU, cfg.ext_svpbmt, false),
1034
1035 DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true),
1036 DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true),
1037 DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true),
1038 DEFINE_PROP_BOOL("zbkb", RISCVCPU, cfg.ext_zbkb, false),
1039 DEFINE_PROP_BOOL("zbkc", RISCVCPU, cfg.ext_zbkc, false),
1040 DEFINE_PROP_BOOL("zbkx", RISCVCPU, cfg.ext_zbkx, false),
1041 DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, true),
1042 DEFINE_PROP_BOOL("zk", RISCVCPU, cfg.ext_zk, false),
1043 DEFINE_PROP_BOOL("zkn", RISCVCPU, cfg.ext_zkn, false),
1044 DEFINE_PROP_BOOL("zknd", RISCVCPU, cfg.ext_zknd, false),
1045 DEFINE_PROP_BOOL("zkne", RISCVCPU, cfg.ext_zkne, false),
1046 DEFINE_PROP_BOOL("zknh", RISCVCPU, cfg.ext_zknh, false),
1047 DEFINE_PROP_BOOL("zkr", RISCVCPU, cfg.ext_zkr, false),
1048 DEFINE_PROP_BOOL("zks", RISCVCPU, cfg.ext_zks, false),
1049 DEFINE_PROP_BOOL("zksed", RISCVCPU, cfg.ext_zksed, false),
1050 DEFINE_PROP_BOOL("zksh", RISCVCPU, cfg.ext_zksh, false),
1051 DEFINE_PROP_BOOL("zkt", RISCVCPU, cfg.ext_zkt, false),
1052
1053 DEFINE_PROP_BOOL("zdinx", RISCVCPU, cfg.ext_zdinx, false),
1054 DEFINE_PROP_BOOL("zfinx", RISCVCPU, cfg.ext_zfinx, false),
1055 DEFINE_PROP_BOOL("zhinx", RISCVCPU, cfg.ext_zhinx, false),
1056 DEFINE_PROP_BOOL("zhinxmin", RISCVCPU, cfg.ext_zhinxmin, false),
1057
1058 DEFINE_PROP_BOOL("zmmul", RISCVCPU, cfg.ext_zmmul, false),
1059
1060
1061 DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps, false),
1062
1063
1064 DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false),
1065
1066 DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false),
1067 DEFINE_PROP_BOOL("x-smaia", RISCVCPU, cfg.ext_smaia, false),
1068 DEFINE_PROP_BOOL("x-ssaia", RISCVCPU, cfg.ext_ssaia, false),
1069
1070 DEFINE_PROP_END_OF_LIST(),
1071};
1072
1073static void register_cpu_props(DeviceState *dev)
1074{
1075 Property *prop;
1076
1077 for (prop = riscv_cpu_extensions; prop && prop->name; prop++) {
1078 qdev_property_add_static(dev, prop);
1079 }
1080}
1081
1082static Property riscv_cpu_properties[] = {
1083 DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true),
1084
1085 DEFINE_PROP_UINT32("mvendorid", RISCVCPU, cfg.mvendorid, 0),
1086 DEFINE_PROP_UINT64("marchid", RISCVCPU, cfg.marchid, RISCV_CPU_MARCHID),
1087 DEFINE_PROP_UINT64("mimpid", RISCVCPU, cfg.mimpid, RISCV_CPU_MIMPID),
1088
1089#ifndef CONFIG_USER_ONLY
1090 DEFINE_PROP_UINT64("resetvec", RISCVCPU, env.resetvec, DEFAULT_RSTVEC),
1091#endif
1092
1093 DEFINE_PROP_BOOL("short-isa-string", RISCVCPU, cfg.short_isa_string, false),
1094
1095 DEFINE_PROP_BOOL("rvv_ta_all_1s", RISCVCPU, cfg.rvv_ta_all_1s, false),
1096 DEFINE_PROP_BOOL("rvv_ma_all_1s", RISCVCPU, cfg.rvv_ma_all_1s, false),
1097 DEFINE_PROP_END_OF_LIST(),
1098};
1099
1100static gchar *riscv_gdb_arch_name(CPUState *cs)
1101{
1102 RISCVCPU *cpu = RISCV_CPU(cs);
1103 CPURISCVState *env = &cpu->env;
1104
1105 switch (riscv_cpu_mxl(env)) {
1106 case MXL_RV32:
1107 return g_strdup("riscv:rv32");
1108 case MXL_RV64:
1109 case MXL_RV128:
1110 return g_strdup("riscv:rv64");
1111 default:
1112 g_assert_not_reached();
1113 }
1114}
1115
1116static const char *riscv_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname)
1117{
1118 RISCVCPU *cpu = RISCV_CPU(cs);
1119
1120 if (strcmp(xmlname, "riscv-csr.xml") == 0) {
1121 return cpu->dyn_csr_xml;
1122 } else if (strcmp(xmlname, "riscv-vector.xml") == 0) {
1123 return cpu->dyn_vreg_xml;
1124 }
1125
1126 return NULL;
1127}
1128
1129#ifndef CONFIG_USER_ONLY
1130#include "hw/core/sysemu-cpu-ops.h"
1131
1132static const struct SysemuCPUOps riscv_sysemu_ops = {
1133 .get_phys_page_debug = riscv_cpu_get_phys_page_debug,
1134 .write_elf64_note = riscv_cpu_write_elf64_note,
1135 .write_elf32_note = riscv_cpu_write_elf32_note,
1136 .legacy_vmsd = &vmstate_riscv_cpu,
1137};
1138#endif
1139
1140#include "hw/core/tcg-cpu-ops.h"
1141
1142static const struct TCGCPUOps riscv_tcg_ops = {
1143 .initialize = riscv_translate_init,
1144 .synchronize_from_tb = riscv_cpu_synchronize_from_tb,
1145 .restore_state_to_opc = riscv_restore_state_to_opc,
1146
1147#ifndef CONFIG_USER_ONLY
1148 .tlb_fill = riscv_cpu_tlb_fill,
1149 .cpu_exec_interrupt = riscv_cpu_exec_interrupt,
1150 .do_interrupt = riscv_cpu_do_interrupt,
1151 .do_transaction_failed = riscv_cpu_do_transaction_failed,
1152 .do_unaligned_access = riscv_cpu_do_unaligned_access,
1153 .debug_excp_handler = riscv_cpu_debug_excp_handler,
1154 .debug_check_breakpoint = riscv_cpu_debug_check_breakpoint,
1155 .debug_check_watchpoint = riscv_cpu_debug_check_watchpoint,
1156#endif
1157};
1158
1159static void riscv_cpu_class_init(ObjectClass *c, void *data)
1160{
1161 RISCVCPUClass *mcc = RISCV_CPU_CLASS(c);
1162 CPUClass *cc = CPU_CLASS(c);
1163 DeviceClass *dc = DEVICE_CLASS(c);
1164
1165 device_class_set_parent_realize(dc, riscv_cpu_realize,
1166 &mcc->parent_realize);
1167
1168 device_class_set_parent_reset(dc, riscv_cpu_reset, &mcc->parent_reset);
1169
1170 cc->class_by_name = riscv_cpu_class_by_name;
1171 cc->has_work = riscv_cpu_has_work;
1172 cc->dump_state = riscv_cpu_dump_state;
1173 cc->set_pc = riscv_cpu_set_pc;
1174 cc->get_pc = riscv_cpu_get_pc;
1175 cc->gdb_read_register = riscv_cpu_gdb_read_register;
1176 cc->gdb_write_register = riscv_cpu_gdb_write_register;
1177 cc->gdb_num_core_regs = 33;
1178 cc->gdb_stop_before_watchpoint = true;
1179 cc->disas_set_info = riscv_cpu_disas_set_info;
1180#ifndef CONFIG_USER_ONLY
1181 cc->sysemu_ops = &riscv_sysemu_ops;
1182#endif
1183 cc->gdb_arch_name = riscv_gdb_arch_name;
1184 cc->gdb_get_dynamic_xml = riscv_gdb_get_dynamic_xml;
1185 cc->tcg_ops = &riscv_tcg_ops;
1186
1187 device_class_set_props(dc, riscv_cpu_properties);
1188}
1189
1190static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str, int max_str_len)
1191{
1192 char *old = *isa_str;
1193 char *new = *isa_str;
1194 int i;
1195
1196 for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) {
1197 if (isa_edata_arr[i].multi_letter &&
1198 isa_ext_is_enabled(cpu, &isa_edata_arr[i])) {
1199 new = g_strconcat(old, "_", isa_edata_arr[i].name, NULL);
1200 g_free(old);
1201 old = new;
1202 }
1203 }
1204
1205 *isa_str = new;
1206}
1207
1208char *riscv_isa_string(RISCVCPU *cpu)
1209{
1210 int i;
1211 const size_t maxlen = sizeof("rv128") + sizeof(riscv_single_letter_exts);
1212 char *isa_str = g_new(char, maxlen);
1213 char *p = isa_str + snprintf(isa_str, maxlen, "rv%d", TARGET_LONG_BITS);
1214 for (i = 0; i < sizeof(riscv_single_letter_exts) - 1; i++) {
1215 if (cpu->env.misa_ext & RV(riscv_single_letter_exts[i])) {
1216 *p++ = qemu_tolower(riscv_single_letter_exts[i]);
1217 }
1218 }
1219 *p = '\0';
1220 if (!cpu->cfg.short_isa_string) {
1221 riscv_isa_string_ext(cpu, &isa_str, maxlen);
1222 }
1223 return isa_str;
1224}
1225
1226static gint riscv_cpu_list_compare(gconstpointer a, gconstpointer b)
1227{
1228 ObjectClass *class_a = (ObjectClass *)a;
1229 ObjectClass *class_b = (ObjectClass *)b;
1230 const char *name_a, *name_b;
1231
1232 name_a = object_class_get_name(class_a);
1233 name_b = object_class_get_name(class_b);
1234 return strcmp(name_a, name_b);
1235}
1236
1237static void riscv_cpu_list_entry(gpointer data, gpointer user_data)
1238{
1239 const char *typename = object_class_get_name(OBJECT_CLASS(data));
1240 int len = strlen(typename) - strlen(RISCV_CPU_TYPE_SUFFIX);
1241
1242 qemu_printf("%.*s\n", len, typename);
1243}
1244
1245void riscv_cpu_list(void)
1246{
1247 GSList *list;
1248
1249 list = object_class_get_list(TYPE_RISCV_CPU, false);
1250 list = g_slist_sort(list, riscv_cpu_list_compare);
1251 g_slist_foreach(list, riscv_cpu_list_entry, NULL);
1252 g_slist_free(list);
1253}
1254
1255#define DEFINE_CPU(type_name, initfn) \
1256 { \
1257 .name = type_name, \
1258 .parent = TYPE_RISCV_CPU, \
1259 .instance_init = initfn \
1260 }
1261
1262static const TypeInfo riscv_cpu_type_infos[] = {
1263 {
1264 .name = TYPE_RISCV_CPU,
1265 .parent = TYPE_CPU,
1266 .instance_size = sizeof(RISCVCPU),
1267 .instance_align = __alignof__(RISCVCPU),
1268 .instance_init = riscv_cpu_init,
1269 .abstract = true,
1270 .class_size = sizeof(RISCVCPUClass),
1271 .class_init = riscv_cpu_class_init,
1272 },
1273 DEFINE_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init),
1274#if defined(CONFIG_KVM)
1275 DEFINE_CPU(TYPE_RISCV_CPU_HOST, riscv_host_cpu_init),
1276#endif
1277#if defined(TARGET_RISCV32)
1278 DEFINE_CPU(TYPE_RISCV_CPU_BASE32, rv32_base_cpu_init),
1279 DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32_ibex_cpu_init),
1280 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32_sifive_e_cpu_init),
1281 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32_imafcu_nommu_cpu_init),
1282 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32_sifive_u_cpu_init),
1283#elif defined(TARGET_RISCV64)
1284 DEFINE_CPU(TYPE_RISCV_CPU_BASE64, rv64_base_cpu_init),
1285 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64_sifive_e_cpu_init),
1286 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64_sifive_u_cpu_init),
1287 DEFINE_CPU(TYPE_RISCV_CPU_SHAKTI_C, rv64_sifive_u_cpu_init),
1288 DEFINE_CPU(TYPE_RISCV_CPU_BASE128, rv128_base_cpu_init),
1289#endif
1290};
1291
1292DEFINE_TYPES(riscv_cpu_type_infos)
1293
