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27#include "qemu/osdep.h"
28#include "hw/sysbus.h"
29#include "migration/vmstate.h"
30#include "hw/register.h"
31#include "qemu/bitops.h"
32#include "qemu/log.h"
33#include "qemu/module.h"
34#include "hw/intc/xlnx-pmu-iomod-intc.h"
35#include "hw/irq.h"
36#include "hw/qdev-properties.h"
37
38#ifndef XLNX_PMU_IO_INTC_ERR_DEBUG
39#define XLNX_PMU_IO_INTC_ERR_DEBUG 0
40#endif
41
42#define DB_PRINT_L(lvl, fmt, args...) do {\
43 if (XLNX_PMU_IO_INTC_ERR_DEBUG >= lvl) {\
44 qemu_log(TYPE_XLNX_PMU_IO_INTC ": %s:" fmt, __func__, ## args);\
45 } \
46} while (0)
47
48#define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args)
49
50REG32(IRQ_MODE, 0xc)
51REG32(GPO0, 0x10)
52 FIELD(GPO0, MAGIC_WORD_1, 24, 8)
53 FIELD(GPO0, MAGIC_WORD_2, 16, 8)
54 FIELD(GPO0, FT_INJECT_FAILURE, 13, 3)
55 FIELD(GPO0, DISABLE_RST_FTSM, 12, 1)
56 FIELD(GPO0, RST_FTSM, 11, 1)
57 FIELD(GPO0, CLR_FTSTS, 10, 1)
58 FIELD(GPO0, RST_ON_SLEEP, 9, 1)
59 FIELD(GPO0, DISABLE_TRACE_COMP, 8, 1)
60 FIELD(GPO0, PIT3_PRESCALE, 7, 1)
61 FIELD(GPO0, PIT2_PRESCALE, 5, 2)
62 FIELD(GPO0, PIT1_PRESCALE, 3, 2)
63 FIELD(GPO0, PIT0_PRESCALE, 1, 2)
64 FIELD(GPO0, DEBUG_REMAP, 0, 1)
65REG32(GPO1, 0x14)
66 FIELD(GPO1, MIO_5, 5, 1)
67 FIELD(GPO1, MIO_4, 4, 1)
68 FIELD(GPO1, MIO_3, 3, 1)
69 FIELD(GPO1, MIO_2, 2, 1)
70 FIELD(GPO1, MIO_1, 1, 1)
71 FIELD(GPO1, MIO_0, 0, 1)
72REG32(GPO2, 0x18)
73 FIELD(GPO2, DAP_RPU_WAKE_ACK, 9, 1)
74 FIELD(GPO2, DAP_FP_WAKE_ACK, 8, 1)
75 FIELD(GPO2, PS_STATUS, 7, 1)
76 FIELD(GPO2, PCAP_EN, 6, 1)
77REG32(GPO3, 0x1c)
78 FIELD(GPO3, PL_GPO_31, 31, 1)
79 FIELD(GPO3, PL_GPO_30, 30, 1)
80 FIELD(GPO3, PL_GPO_29, 29, 1)
81 FIELD(GPO3, PL_GPO_28, 28, 1)
82 FIELD(GPO3, PL_GPO_27, 27, 1)
83 FIELD(GPO3, PL_GPO_26, 26, 1)
84 FIELD(GPO3, PL_GPO_25, 25, 1)
85 FIELD(GPO3, PL_GPO_24, 24, 1)
86 FIELD(GPO3, PL_GPO_23, 23, 1)
87 FIELD(GPO3, PL_GPO_22, 22, 1)
88 FIELD(GPO3, PL_GPO_21, 21, 1)
89 FIELD(GPO3, PL_GPO_20, 20, 1)
90 FIELD(GPO3, PL_GPO_19, 19, 1)
91 FIELD(GPO3, PL_GPO_18, 18, 1)
92 FIELD(GPO3, PL_GPO_17, 17, 1)
93 FIELD(GPO3, PL_GPO_16, 16, 1)
94 FIELD(GPO3, PL_GPO_15, 15, 1)
95 FIELD(GPO3, PL_GPO_14, 14, 1)
96 FIELD(GPO3, PL_GPO_13, 13, 1)
97 FIELD(GPO3, PL_GPO_12, 12, 1)
98 FIELD(GPO3, PL_GPO_11, 11, 1)
99 FIELD(GPO3, PL_GPO_10, 10, 1)
100 FIELD(GPO3, PL_GPO_9, 9, 1)
101 FIELD(GPO3, PL_GPO_8, 8, 1)
102 FIELD(GPO3, PL_GPO_7, 7, 1)
103 FIELD(GPO3, PL_GPO_6, 6, 1)
104 FIELD(GPO3, PL_GPO_5, 5, 1)
105 FIELD(GPO3, PL_GPO_4, 4, 1)
106 FIELD(GPO3, PL_GPO_3, 3, 1)
107 FIELD(GPO3, PL_GPO_2, 2, 1)
108 FIELD(GPO3, PL_GPO_1, 1, 1)
109 FIELD(GPO3, PL_GPO_0, 0, 1)
110REG32(GPI0, 0x20)
111 FIELD(GPI0, RFT_ECC_FATAL_ERR, 31, 1)
112 FIELD(GPI0, RFT_VOTER_ERR, 30, 1)
113 FIELD(GPI0, RFT_COMPARE_ERR_23, 29, 1)
114 FIELD(GPI0, RFT_COMPARE_ERR_13, 28, 1)
115 FIELD(GPI0, RFT_COMPARE_ERR_12, 27, 1)
116 FIELD(GPI0, RFT_LS_MISMATCH_23_B, 26, 1)
117 FIELD(GPI0, RFT_LS_MISMATCH_13_B, 25, 1)
118 FIELD(GPI0, RFT_LS_MISMATCH_12_B, 24, 1)
119 FIELD(GPI0, RFT_MISMATCH_STATE, 23, 1)
120 FIELD(GPI0, RFT_MISMATCH_CPU, 22, 1)
121 FIELD(GPI0, RFT_SLEEP_RESET, 19, 1)
122 FIELD(GPI0, RFT_LS_MISMATCH_23_A, 18, 1)
123 FIELD(GPI0, RFT_LS_MISMATCH_13_A, 17, 1)
124 FIELD(GPI0, RFT_LS_MISMATCH_12_A, 16, 1)
125 FIELD(GPI0, NFT_ECC_FATAL_ERR, 15, 1)
126 FIELD(GPI0, NFT_VOTER_ERR, 14, 1)
127 FIELD(GPI0, NFT_COMPARE_ERR_23, 13, 1)
128 FIELD(GPI0, NFT_COMPARE_ERR_13, 12, 1)
129 FIELD(GPI0, NFT_COMPARE_ERR_12, 11, 1)
130 FIELD(GPI0, NFT_LS_MISMATCH_23_B, 10, 1)
131 FIELD(GPI0, NFT_LS_MISMATCH_13_B, 9, 1)
132 FIELD(GPI0, NFT_LS_MISMATCH_12_B, 8, 1)
133 FIELD(GPI0, NFT_MISMATCH_STATE, 7, 1)
134 FIELD(GPI0, NFT_MISMATCH_CPU, 6, 1)
135 FIELD(GPI0, NFT_SLEEP_RESET, 3, 1)
136 FIELD(GPI0, NFT_LS_MISMATCH_23_A, 2, 1)
137 FIELD(GPI0, NFT_LS_MISMATCH_13_A, 1, 1)
138 FIELD(GPI0, NFT_LS_MISMATCH_12_A, 0, 1)
139REG32(GPI1, 0x24)
140 FIELD(GPI1, APB_AIB_ERROR, 31, 1)
141 FIELD(GPI1, AXI_AIB_ERROR, 30, 1)
142 FIELD(GPI1, ERROR_2, 29, 1)
143 FIELD(GPI1, ERROR_1, 28, 1)
144 FIELD(GPI1, ACPU_3_DBG_PWRUP, 23, 1)
145 FIELD(GPI1, ACPU_2_DBG_PWRUP, 22, 1)
146 FIELD(GPI1, ACPU_1_DBG_PWRUP, 21, 1)
147 FIELD(GPI1, ACPU_0_DBG_PWRUP, 20, 1)
148 FIELD(GPI1, FPD_WAKE_GIC_PROXY, 16, 1)
149 FIELD(GPI1, MIO_WAKE_5, 15, 1)
150 FIELD(GPI1, MIO_WAKE_4, 14, 1)
151 FIELD(GPI1, MIO_WAKE_3, 13, 1)
152 FIELD(GPI1, MIO_WAKE_2, 12, 1)
153 FIELD(GPI1, MIO_WAKE_1, 11, 1)
154 FIELD(GPI1, MIO_WAKE_0, 10, 1)
155 FIELD(GPI1, DAP_RPU_WAKE, 9, 1)
156 FIELD(GPI1, DAP_FPD_WAKE, 8, 1)
157 FIELD(GPI1, USB_1_WAKE, 7, 1)
158 FIELD(GPI1, USB_0_WAKE, 6, 1)
159 FIELD(GPI1, R5_1_WAKE, 5, 1)
160 FIELD(GPI1, R5_0_WAKE, 4, 1)
161 FIELD(GPI1, ACPU_3_WAKE, 3, 1)
162 FIELD(GPI1, ACPU_2_WAKE, 2, 1)
163 FIELD(GPI1, ACPU_1_WAKE, 1, 1)
164 FIELD(GPI1, ACPU_0_WAKE, 0, 1)
165REG32(GPI2, 0x28)
166 FIELD(GPI2, VCC_INT_FP_DISCONNECT, 31, 1)
167 FIELD(GPI2, VCC_INT_DISCONNECT, 30, 1)
168 FIELD(GPI2, VCC_AUX_DISCONNECT, 29, 1)
169 FIELD(GPI2, DBG_ACPU3_RST_REQ, 23, 1)
170 FIELD(GPI2, DBG_ACPU2_RST_REQ, 22, 1)
171 FIELD(GPI2, DBG_ACPU1_RST_REQ, 21, 1)
172 FIELD(GPI2, DBG_ACPU0_RST_REQ, 20, 1)
173 FIELD(GPI2, CP_ACPU3_RST_REQ, 19, 1)
174 FIELD(GPI2, CP_ACPU2_RST_REQ, 18, 1)
175 FIELD(GPI2, CP_ACPU1_RST_REQ, 17, 1)
176 FIELD(GPI2, CP_ACPU0_RST_REQ, 16, 1)
177 FIELD(GPI2, DBG_RCPU1_RST_REQ, 9, 1)
178 FIELD(GPI2, DBG_RCPU0_RST_REQ, 8, 1)
179 FIELD(GPI2, R5_1_SLEEP, 5, 1)
180 FIELD(GPI2, R5_0_SLEEP, 4, 1)
181 FIELD(GPI2, ACPU_3_SLEEP, 3, 1)
182 FIELD(GPI2, ACPU_2_SLEEP, 2, 1)
183 FIELD(GPI2, ACPU_1_SLEEP, 1, 1)
184 FIELD(GPI2, ACPU_0_SLEEP, 0, 1)
185REG32(GPI3, 0x2c)
186 FIELD(GPI3, PL_GPI_31, 31, 1)
187 FIELD(GPI3, PL_GPI_30, 30, 1)
188 FIELD(GPI3, PL_GPI_29, 29, 1)
189 FIELD(GPI3, PL_GPI_28, 28, 1)
190 FIELD(GPI3, PL_GPI_27, 27, 1)
191 FIELD(GPI3, PL_GPI_26, 26, 1)
192 FIELD(GPI3, PL_GPI_25, 25, 1)
193 FIELD(GPI3, PL_GPI_24, 24, 1)
194 FIELD(GPI3, PL_GPI_23, 23, 1)
195 FIELD(GPI3, PL_GPI_22, 22, 1)
196 FIELD(GPI3, PL_GPI_21, 21, 1)
197 FIELD(GPI3, PL_GPI_20, 20, 1)
198 FIELD(GPI3, PL_GPI_19, 19, 1)
199 FIELD(GPI3, PL_GPI_18, 18, 1)
200 FIELD(GPI3, PL_GPI_17, 17, 1)
201 FIELD(GPI3, PL_GPI_16, 16, 1)
202 FIELD(GPI3, PL_GPI_15, 15, 1)
203 FIELD(GPI3, PL_GPI_14, 14, 1)
204 FIELD(GPI3, PL_GPI_13, 13, 1)
205 FIELD(GPI3, PL_GPI_12, 12, 1)
206 FIELD(GPI3, PL_GPI_11, 11, 1)
207 FIELD(GPI3, PL_GPI_10, 10, 1)
208 FIELD(GPI3, PL_GPI_9, 9, 1)
209 FIELD(GPI3, PL_GPI_8, 8, 1)
210 FIELD(GPI3, PL_GPI_7, 7, 1)
211 FIELD(GPI3, PL_GPI_6, 6, 1)
212 FIELD(GPI3, PL_GPI_5, 5, 1)
213 FIELD(GPI3, PL_GPI_4, 4, 1)
214 FIELD(GPI3, PL_GPI_3, 3, 1)
215 FIELD(GPI3, PL_GPI_2, 2, 1)
216 FIELD(GPI3, PL_GPI_1, 1, 1)
217 FIELD(GPI3, PL_GPI_0, 0, 1)
218REG32(IRQ_STATUS, 0x30)
219 FIELD(IRQ_STATUS, CSU_PMU_SEC_LOCK, 31, 1)
220 FIELD(IRQ_STATUS, INV_ADDR, 29, 1)
221 FIELD(IRQ_STATUS, PWR_DN_REQ, 28, 1)
222 FIELD(IRQ_STATUS, PWR_UP_REQ, 27, 1)
223 FIELD(IRQ_STATUS, SW_RST_REQ, 26, 1)
224 FIELD(IRQ_STATUS, HW_RST_REQ, 25, 1)
225 FIELD(IRQ_STATUS, ISO_REQ, 24, 1)
226 FIELD(IRQ_STATUS, FW_REQ, 23, 1)
227 FIELD(IRQ_STATUS, IPI3, 22, 1)
228 FIELD(IRQ_STATUS, IPI2, 21, 1)
229 FIELD(IRQ_STATUS, IPI1, 20, 1)
230 FIELD(IRQ_STATUS, IPI0, 19, 1)
231 FIELD(IRQ_STATUS, RTC_ALARM, 18, 1)
232 FIELD(IRQ_STATUS, RTC_EVERY_SECOND, 17, 1)
233 FIELD(IRQ_STATUS, CORRECTABLE_ECC, 16, 1)
234 FIELD(IRQ_STATUS, GPI3, 14, 1)
235 FIELD(IRQ_STATUS, GPI2, 13, 1)
236 FIELD(IRQ_STATUS, GPI1, 12, 1)
237 FIELD(IRQ_STATUS, GPI0, 11, 1)
238 FIELD(IRQ_STATUS, PIT3, 6, 1)
239 FIELD(IRQ_STATUS, PIT2, 5, 1)
240 FIELD(IRQ_STATUS, PIT1, 4, 1)
241 FIELD(IRQ_STATUS, PIT0, 3, 1)
242REG32(IRQ_PENDING, 0x34)
243 FIELD(IRQ_PENDING, CSU_PMU_SEC_LOCK, 31, 1)
244 FIELD(IRQ_PENDING, INV_ADDR, 29, 1)
245 FIELD(IRQ_PENDING, PWR_DN_REQ, 28, 1)
246 FIELD(IRQ_PENDING, PWR_UP_REQ, 27, 1)
247 FIELD(IRQ_PENDING, SW_RST_REQ, 26, 1)
248 FIELD(IRQ_PENDING, HW_RST_REQ, 25, 1)
249 FIELD(IRQ_PENDING, ISO_REQ, 24, 1)
250 FIELD(IRQ_PENDING, FW_REQ, 23, 1)
251 FIELD(IRQ_PENDING, IPI3, 22, 1)
252 FIELD(IRQ_PENDING, IPI2, 21, 1)
253 FIELD(IRQ_PENDING, IPI1, 20, 1)
254 FIELD(IRQ_PENDING, IPI0, 19, 1)
255 FIELD(IRQ_PENDING, RTC_ALARM, 18, 1)
256 FIELD(IRQ_PENDING, RTC_EVERY_SECOND, 17, 1)
257 FIELD(IRQ_PENDING, CORRECTABLE_ECC, 16, 1)
258 FIELD(IRQ_PENDING, GPI3, 14, 1)
259 FIELD(IRQ_PENDING, GPI2, 13, 1)
260 FIELD(IRQ_PENDING, GPI1, 12, 1)
261 FIELD(IRQ_PENDING, GPI0, 11, 1)
262 FIELD(IRQ_PENDING, PIT3, 6, 1)
263 FIELD(IRQ_PENDING, PIT2, 5, 1)
264 FIELD(IRQ_PENDING, PIT1, 4, 1)
265 FIELD(IRQ_PENDING, PIT0, 3, 1)
266REG32(IRQ_ENABLE, 0x38)
267 FIELD(IRQ_ENABLE, CSU_PMU_SEC_LOCK, 31, 1)
268 FIELD(IRQ_ENABLE, INV_ADDR, 29, 1)
269 FIELD(IRQ_ENABLE, PWR_DN_REQ, 28, 1)
270 FIELD(IRQ_ENABLE, PWR_UP_REQ, 27, 1)
271 FIELD(IRQ_ENABLE, SW_RST_REQ, 26, 1)
272 FIELD(IRQ_ENABLE, HW_RST_REQ, 25, 1)
273 FIELD(IRQ_ENABLE, ISO_REQ, 24, 1)
274 FIELD(IRQ_ENABLE, FW_REQ, 23, 1)
275 FIELD(IRQ_ENABLE, IPI3, 22, 1)
276 FIELD(IRQ_ENABLE, IPI2, 21, 1)
277 FIELD(IRQ_ENABLE, IPI1, 20, 1)
278 FIELD(IRQ_ENABLE, IPI0, 19, 1)
279 FIELD(IRQ_ENABLE, RTC_ALARM, 18, 1)
280 FIELD(IRQ_ENABLE, RTC_EVERY_SECOND, 17, 1)
281 FIELD(IRQ_ENABLE, CORRECTABLE_ECC, 16, 1)
282 FIELD(IRQ_ENABLE, GPI3, 14, 1)
283 FIELD(IRQ_ENABLE, GPI2, 13, 1)
284 FIELD(IRQ_ENABLE, GPI1, 12, 1)
285 FIELD(IRQ_ENABLE, GPI0, 11, 1)
286 FIELD(IRQ_ENABLE, PIT3, 6, 1)
287 FIELD(IRQ_ENABLE, PIT2, 5, 1)
288 FIELD(IRQ_ENABLE, PIT1, 4, 1)
289 FIELD(IRQ_ENABLE, PIT0, 3, 1)
290REG32(IRQ_ACK, 0x3c)
291 FIELD(IRQ_ACK, CSU_PMU_SEC_LOCK, 31, 1)
292 FIELD(IRQ_ACK, INV_ADDR, 29, 1)
293 FIELD(IRQ_ACK, PWR_DN_REQ, 28, 1)
294 FIELD(IRQ_ACK, PWR_UP_REQ, 27, 1)
295 FIELD(IRQ_ACK, SW_RST_REQ, 26, 1)
296 FIELD(IRQ_ACK, HW_RST_REQ, 25, 1)
297 FIELD(IRQ_ACK, ISO_REQ, 24, 1)
298 FIELD(IRQ_ACK, FW_REQ, 23, 1)
299 FIELD(IRQ_ACK, IPI3, 22, 1)
300 FIELD(IRQ_ACK, IPI2, 21, 1)
301 FIELD(IRQ_ACK, IPI1, 20, 1)
302 FIELD(IRQ_ACK, IPI0, 19, 1)
303 FIELD(IRQ_ACK, RTC_ALARM, 18, 1)
304 FIELD(IRQ_ACK, RTC_EVERY_SECOND, 17, 1)
305 FIELD(IRQ_ACK, CORRECTABLE_ECC, 16, 1)
306 FIELD(IRQ_ACK, GPI3, 14, 1)
307 FIELD(IRQ_ACK, GPI2, 13, 1)
308 FIELD(IRQ_ACK, GPI1, 12, 1)
309 FIELD(IRQ_ACK, GPI0, 11, 1)
310 FIELD(IRQ_ACK, PIT3, 6, 1)
311 FIELD(IRQ_ACK, PIT2, 5, 1)
312 FIELD(IRQ_ACK, PIT1, 4, 1)
313 FIELD(IRQ_ACK, PIT0, 3, 1)
314REG32(PIT0_PRELOAD, 0x40)
315REG32(PIT0_COUNTER, 0x44)
316REG32(PIT0_CONTROL, 0x48)
317 FIELD(PIT0_CONTROL, PRELOAD, 1, 1)
318 FIELD(PIT0_CONTROL, EN, 0, 1)
319REG32(PIT1_PRELOAD, 0x50)
320REG32(PIT1_COUNTER, 0x54)
321REG32(PIT1_CONTROL, 0x58)
322 FIELD(PIT1_CONTROL, PRELOAD, 1, 1)
323 FIELD(PIT1_CONTROL, EN, 0, 1)
324REG32(PIT2_PRELOAD, 0x60)
325REG32(PIT2_COUNTER, 0x64)
326REG32(PIT2_CONTROL, 0x68)
327 FIELD(PIT2_CONTROL, PRELOAD, 1, 1)
328 FIELD(PIT2_CONTROL, EN, 0, 1)
329REG32(PIT3_PRELOAD, 0x70)
330REG32(PIT3_COUNTER, 0x74)
331REG32(PIT3_CONTROL, 0x78)
332 FIELD(PIT3_CONTROL, PRELOAD, 1, 1)
333 FIELD(PIT3_CONTROL, EN, 0, 1)
334
335static void xlnx_pmu_io_irq_update(XlnxPMUIOIntc *s)
336{
337 bool irq_out;
338
339 s->regs[R_IRQ_PENDING] = s->regs[R_IRQ_STATUS] & s->regs[R_IRQ_ENABLE];
340 irq_out = !!s->regs[R_IRQ_PENDING];
341
342 DB_PRINT("Setting IRQ output = %d\n", irq_out);
343
344 qemu_set_irq(s->parent_irq, irq_out);
345}
346
347static void xlnx_pmu_io_irq_enable_postw(RegisterInfo *reg, uint64_t val64)
348{
349 XlnxPMUIOIntc *s = XLNX_PMU_IO_INTC(reg->opaque);
350
351 xlnx_pmu_io_irq_update(s);
352}
353
354static void xlnx_pmu_io_irq_ack_postw(RegisterInfo *reg, uint64_t val64)
355{
356 XlnxPMUIOIntc *s = XLNX_PMU_IO_INTC(reg->opaque);
357 uint32_t val = val64;
358
359
360 val &= s->regs[R_IRQ_STATUS];
361 s->regs[R_IRQ_STATUS] ^= val;
362
363
364 s->regs[R_IRQ_STATUS] |= s->irq_raw & ~s->cfg.level_edge;
365
366 xlnx_pmu_io_irq_update(s);
367}
368
369static const RegisterAccessInfo xlnx_pmu_io_intc_regs_info[] = {
370 { .name = "IRQ_MODE", .addr = A_IRQ_MODE,
371 .rsvd = 0xffffffff,
372 },{ .name = "GPO0", .addr = A_GPO0,
373 },{ .name = "GPO1", .addr = A_GPO1,
374 .rsvd = 0xffffffc0,
375 },{ .name = "GPO2", .addr = A_GPO2,
376 .rsvd = 0xfffffc3f,
377 },{ .name = "GPO3", .addr = A_GPO3,
378 },{ .name = "GPI0", .addr = A_GPI0,
379 .rsvd = 0x300030,
380 .ro = 0xffcfffcf,
381 },{ .name = "GPI1", .addr = A_GPI1,
382 .rsvd = 0xf0e0000,
383 .ro = 0xf0f1ffff,
384 },{ .name = "GPI2", .addr = A_GPI2,
385 .rsvd = 0x1f00fcc0,
386 .ro = 0xe0ff033f,
387 },{ .name = "GPI3", .addr = A_GPI3,
388 .ro = 0xffffffff,
389 },{ .name = "IRQ_STATUS", .addr = A_IRQ_STATUS,
390 .rsvd = 0x40008787,
391 .ro = 0xbfff7878,
392 },{ .name = "IRQ_PENDING", .addr = A_IRQ_PENDING,
393 .rsvd = 0x40008787,
394 .ro = 0xdfff7ff8,
395 },{ .name = "IRQ_ENABLE", .addr = A_IRQ_ENABLE,
396 .rsvd = 0x40008787,
397 .ro = 0x7800,
398 .post_write = xlnx_pmu_io_irq_enable_postw,
399 },{ .name = "IRQ_ACK", .addr = A_IRQ_ACK,
400 .rsvd = 0x40008787,
401 .post_write = xlnx_pmu_io_irq_ack_postw,
402 },{ .name = "PIT0_PRELOAD", .addr = A_PIT0_PRELOAD,
403 .ro = 0xffffffff,
404 },{ .name = "PIT0_COUNTER", .addr = A_PIT0_COUNTER,
405 .ro = 0xffffffff,
406 },{ .name = "PIT0_CONTROL", .addr = A_PIT0_CONTROL,
407 .rsvd = 0xfffffffc,
408 },{ .name = "PIT1_PRELOAD", .addr = A_PIT1_PRELOAD,
409 .ro = 0xffffffff,
410 },{ .name = "PIT1_COUNTER", .addr = A_PIT1_COUNTER,
411 .ro = 0xffffffff,
412 },{ .name = "PIT1_CONTROL", .addr = A_PIT1_CONTROL,
413 .rsvd = 0xfffffffc,
414 },{ .name = "PIT2_PRELOAD", .addr = A_PIT2_PRELOAD,
415 .ro = 0xffffffff,
416 },{ .name = "PIT2_COUNTER", .addr = A_PIT2_COUNTER,
417 .ro = 0xffffffff,
418 },{ .name = "PIT2_CONTROL", .addr = A_PIT2_CONTROL,
419 .rsvd = 0xfffffffc,
420 },{ .name = "PIT3_PRELOAD", .addr = A_PIT3_PRELOAD,
421 .ro = 0xffffffff,
422 },{ .name = "PIT3_COUNTER", .addr = A_PIT3_COUNTER,
423 .ro = 0xffffffff,
424 },{ .name = "PIT3_CONTROL", .addr = A_PIT3_CONTROL,
425 .rsvd = 0xfffffffc,
426 }
427};
428
429static void irq_handler(void *opaque, int irq, int level)
430{
431 XlnxPMUIOIntc *s = XLNX_PMU_IO_INTC(opaque);
432 uint32_t mask = 1 << irq;
433 uint32_t prev = s->irq_raw;
434 uint32_t temp;
435
436 s->irq_raw &= ~mask;
437 s->irq_raw |= (!!level) << irq;
438
439
440 s->irq_raw ^= (~s->cfg.positive);
441 s->irq_raw &= mask;
442
443 if (s->cfg.level_edge & mask) {
444
445 temp = (prev ^ s->irq_raw) & s->irq_raw;
446 } else {
447
448 temp = s->irq_raw;
449 }
450 s->regs[R_IRQ_STATUS] |= temp;
451
452 xlnx_pmu_io_irq_update(s);
453}
454
455static void xlnx_pmu_io_intc_reset(DeviceState *dev)
456{
457 XlnxPMUIOIntc *s = XLNX_PMU_IO_INTC(dev);
458 unsigned int i;
459
460 for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) {
461 register_reset(&s->regs_info[i]);
462 }
463
464 xlnx_pmu_io_irq_update(s);
465}
466
467static const MemoryRegionOps xlnx_pmu_io_intc_ops = {
468 .read = register_read_memory,
469 .write = register_write_memory,
470 .endianness = DEVICE_LITTLE_ENDIAN,
471 .valid = {
472 .min_access_size = 4,
473 .max_access_size = 4,
474 },
475};
476
477static Property xlnx_pmu_io_intc_properties[] = {
478 DEFINE_PROP_UINT32("intc-intr-size", XlnxPMUIOIntc, cfg.intr_size, 0),
479 DEFINE_PROP_UINT32("intc-level-edge", XlnxPMUIOIntc, cfg.level_edge, 0),
480 DEFINE_PROP_UINT32("intc-positive", XlnxPMUIOIntc, cfg.positive, 0),
481 DEFINE_PROP_END_OF_LIST(),
482};
483
484static void xlnx_pmu_io_intc_realize(DeviceState *dev, Error **errp)
485{
486 XlnxPMUIOIntc *s = XLNX_PMU_IO_INTC(dev);
487
488
489 s->cfg.level_edge <<= 16;
490 s->cfg.level_edge |= 0xffff;
491
492
493 s->cfg.positive <<= 16;
494 s->cfg.positive |= 0xffff;
495
496
497 assert(s->cfg.intr_size <= 16);
498
499 qdev_init_gpio_in(dev, irq_handler, 16 + s->cfg.intr_size);
500}
501
502static void xlnx_pmu_io_intc_init(Object *obj)
503{
504 XlnxPMUIOIntc *s = XLNX_PMU_IO_INTC(obj);
505 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
506 RegisterInfoArray *reg_array;
507
508 memory_region_init(&s->iomem, obj, TYPE_XLNX_PMU_IO_INTC,
509 XLNXPMUIOINTC_R_MAX * 4);
510 reg_array =
511 register_init_block32(DEVICE(obj), xlnx_pmu_io_intc_regs_info,
512 ARRAY_SIZE(xlnx_pmu_io_intc_regs_info),
513 s->regs_info, s->regs,
514 &xlnx_pmu_io_intc_ops,
515 XLNX_PMU_IO_INTC_ERR_DEBUG,
516 XLNXPMUIOINTC_R_MAX * 4);
517 memory_region_add_subregion(&s->iomem,
518 0x0,
519 ®_array->mem);
520 sysbus_init_mmio(sbd, &s->iomem);
521
522 sysbus_init_irq(sbd, &s->parent_irq);
523}
524
525static const VMStateDescription vmstate_xlnx_pmu_io_intc = {
526 .name = TYPE_XLNX_PMU_IO_INTC,
527 .version_id = 1,
528 .minimum_version_id = 1,
529 .fields = (VMStateField[]) {
530 VMSTATE_UINT32_ARRAY(regs, XlnxPMUIOIntc, XLNXPMUIOINTC_R_MAX),
531 VMSTATE_END_OF_LIST(),
532 }
533};
534
535static void xlnx_pmu_io_intc_class_init(ObjectClass *klass, void *data)
536{
537 DeviceClass *dc = DEVICE_CLASS(klass);
538
539 dc->reset = xlnx_pmu_io_intc_reset;
540 dc->realize = xlnx_pmu_io_intc_realize;
541 dc->vmsd = &vmstate_xlnx_pmu_io_intc;
542 device_class_set_props(dc, xlnx_pmu_io_intc_properties);
543}
544
545static const TypeInfo xlnx_pmu_io_intc_info = {
546 .name = TYPE_XLNX_PMU_IO_INTC,
547 .parent = TYPE_SYS_BUS_DEVICE,
548 .instance_size = sizeof(XlnxPMUIOIntc),
549 .class_init = xlnx_pmu_io_intc_class_init,
550 .instance_init = xlnx_pmu_io_intc_init,
551};
552
553static void xlnx_pmu_io_intc_register_types(void)
554{
555 type_register_static(&xlnx_pmu_io_intc_info);
556}
557
558type_init(xlnx_pmu_io_intc_register_types)
559
