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32#include "qemu/osdep.h"
33#include "qapi/error.h"
34#include "hw/irq.h"
35#include "hw/pci-host/gpex.h"
36#include "hw/qdev-properties.h"
37#include "migration/vmstate.h"
38#include "qemu/module.h"
39
40
41
42
43
44static void gpex_set_irq(void *opaque, int irq_num, int level)
45{
46 GPEXHost *s = opaque;
47
48 qemu_set_irq(s->irq[irq_num], level);
49}
50
51int gpex_set_irq_num(GPEXHost *s, int index, int gsi)
52{
53 if (index >= GPEX_NUM_IRQS) {
54 return -EINVAL;
55 }
56
57 s->irq_num[index] = gsi;
58 return 0;
59}
60
61static PCIINTxRoute gpex_route_intx_pin_to_irq(void *opaque, int pin)
62{
63 PCIINTxRoute route;
64 GPEXHost *s = opaque;
65 int gsi = s->irq_num[pin];
66
67 route.irq = gsi;
68 if (gsi < 0) {
69 route.mode = PCI_INTX_DISABLED;
70 } else {
71 route.mode = PCI_INTX_ENABLED;
72 }
73
74 return route;
75}
76
77static void gpex_host_realize(DeviceState *dev, Error **errp)
78{
79 PCIHostState *pci = PCI_HOST_BRIDGE(dev);
80 GPEXHost *s = GPEX_HOST(dev);
81 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
82 PCIExpressHost *pex = PCIE_HOST_BRIDGE(dev);
83 int i;
84
85 pcie_host_mmcfg_init(pex, PCIE_MMCFG_SIZE_MAX);
86 sysbus_init_mmio(sbd, &pex->mmio);
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110
111 memory_region_init(&s->io_mmio, OBJECT(s), "gpex_mmio", UINT64_MAX);
112 memory_region_init(&s->io_ioport, OBJECT(s), "gpex_ioport", 64 * 1024);
113
114 if (s->allow_unmapped_accesses) {
115 memory_region_init_io(&s->io_mmio_window, OBJECT(s),
116 &unassigned_io_ops, OBJECT(s),
117 "gpex_mmio_window", UINT64_MAX);
118 memory_region_init_io(&s->io_ioport_window, OBJECT(s),
119 &unassigned_io_ops, OBJECT(s),
120 "gpex_ioport_window", 64 * 1024);
121
122 memory_region_add_subregion(&s->io_mmio_window, 0, &s->io_mmio);
123 memory_region_add_subregion(&s->io_ioport_window, 0, &s->io_ioport);
124 sysbus_init_mmio(sbd, &s->io_mmio_window);
125 sysbus_init_mmio(sbd, &s->io_ioport_window);
126 } else {
127 sysbus_init_mmio(sbd, &s->io_mmio);
128 sysbus_init_mmio(sbd, &s->io_ioport);
129 }
130
131 for (i = 0; i < GPEX_NUM_IRQS; i++) {
132 sysbus_init_irq(sbd, &s->irq[i]);
133 s->irq_num[i] = -1;
134 }
135
136 pci->bus = pci_register_root_bus(dev, "pcie.0", gpex_set_irq,
137 pci_swizzle_map_irq_fn, s, &s->io_mmio,
138 &s->io_ioport, 0, 4, TYPE_PCIE_BUS);
139
140 pci_bus_set_route_irq_fn(pci->bus, gpex_route_intx_pin_to_irq);
141 qdev_realize(DEVICE(&s->gpex_root), BUS(pci->bus), &error_fatal);
142}
143
144static const char *gpex_host_root_bus_path(PCIHostState *host_bridge,
145 PCIBus *rootbus)
146{
147 return "0000:00";
148}
149
150static Property gpex_host_properties[] = {
151
152
153
154
155 DEFINE_PROP_BOOL("allow-unmapped-accesses", GPEXHost,
156 allow_unmapped_accesses, true),
157 DEFINE_PROP_END_OF_LIST(),
158};
159
160static void gpex_host_class_init(ObjectClass *klass, void *data)
161{
162 DeviceClass *dc = DEVICE_CLASS(klass);
163 PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass);
164
165 hc->root_bus_path = gpex_host_root_bus_path;
166 dc->realize = gpex_host_realize;
167 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
168 dc->fw_name = "pci";
169 device_class_set_props(dc, gpex_host_properties);
170}
171
172static void gpex_host_initfn(Object *obj)
173{
174 GPEXHost *s = GPEX_HOST(obj);
175 GPEXRootState *root = &s->gpex_root;
176
177 object_initialize_child(obj, "gpex_root", root, TYPE_GPEX_ROOT_DEVICE);
178 qdev_prop_set_int32(DEVICE(root), "addr", PCI_DEVFN(0, 0));
179 qdev_prop_set_bit(DEVICE(root), "multifunction", false);
180}
181
182static const TypeInfo gpex_host_info = {
183 .name = TYPE_GPEX_HOST,
184 .parent = TYPE_PCIE_HOST_BRIDGE,
185 .instance_size = sizeof(GPEXHost),
186 .instance_init = gpex_host_initfn,
187 .class_init = gpex_host_class_init,
188};
189
190
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192
193
194static const VMStateDescription vmstate_gpex_root = {
195 .name = "gpex_root",
196 .version_id = 1,
197 .minimum_version_id = 1,
198 .fields = (VMStateField[]) {
199 VMSTATE_PCI_DEVICE(parent_obj, GPEXRootState),
200 VMSTATE_END_OF_LIST()
201 }
202};
203
204static void gpex_root_class_init(ObjectClass *klass, void *data)
205{
206 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
207 DeviceClass *dc = DEVICE_CLASS(klass);
208
209 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
210 dc->desc = "QEMU generic PCIe host bridge";
211 dc->vmsd = &vmstate_gpex_root;
212 k->vendor_id = PCI_VENDOR_ID_REDHAT;
213 k->device_id = PCI_DEVICE_ID_REDHAT_PCIE_HOST;
214 k->revision = 0;
215 k->class_id = PCI_CLASS_BRIDGE_HOST;
216
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220 dc->user_creatable = false;
221}
222
223static const TypeInfo gpex_root_info = {
224 .name = TYPE_GPEX_ROOT_DEVICE,
225 .parent = TYPE_PCI_DEVICE,
226 .instance_size = sizeof(GPEXRootState),
227 .class_init = gpex_root_class_init,
228 .interfaces = (InterfaceInfo[]) {
229 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
230 { },
231 },
232};
233
234static void gpex_register(void)
235{
236 type_register_static(&gpex_root_info);
237 type_register_static(&gpex_host_info);
238}
239
240type_init(gpex_register)
241