1#ifndef BLOCK_NVME_H
2#define BLOCK_NVME_H
3
4typedef struct QEMU_PACKED NvmeBar {
5 uint64_t cap;
6 uint32_t vs;
7 uint32_t intms;
8 uint32_t intmc;
9 uint32_t cc;
10 uint8_t rsvd24[4];
11 uint32_t csts;
12 uint32_t nssr;
13 uint32_t aqa;
14 uint64_t asq;
15 uint64_t acq;
16 uint32_t cmbloc;
17 uint32_t cmbsz;
18 uint32_t bpinfo;
19 uint32_t bprsel;
20 uint64_t bpmbl;
21 uint64_t cmbmsc;
22 uint32_t cmbsts;
23 uint8_t rsvd92[3492];
24 uint32_t pmrcap;
25 uint32_t pmrctl;
26 uint32_t pmrsts;
27 uint32_t pmrebs;
28 uint32_t pmrswtp;
29 uint32_t pmrmscl;
30 uint32_t pmrmscu;
31 uint8_t css[484];
32} NvmeBar;
33
34enum NvmeBarRegs {
35 NVME_REG_CAP = offsetof(NvmeBar, cap),
36 NVME_REG_VS = offsetof(NvmeBar, vs),
37 NVME_REG_INTMS = offsetof(NvmeBar, intms),
38 NVME_REG_INTMC = offsetof(NvmeBar, intmc),
39 NVME_REG_CC = offsetof(NvmeBar, cc),
40 NVME_REG_CSTS = offsetof(NvmeBar, csts),
41 NVME_REG_NSSR = offsetof(NvmeBar, nssr),
42 NVME_REG_AQA = offsetof(NvmeBar, aqa),
43 NVME_REG_ASQ = offsetof(NvmeBar, asq),
44 NVME_REG_ACQ = offsetof(NvmeBar, acq),
45 NVME_REG_CMBLOC = offsetof(NvmeBar, cmbloc),
46 NVME_REG_CMBSZ = offsetof(NvmeBar, cmbsz),
47 NVME_REG_BPINFO = offsetof(NvmeBar, bpinfo),
48 NVME_REG_BPRSEL = offsetof(NvmeBar, bprsel),
49 NVME_REG_BPMBL = offsetof(NvmeBar, bpmbl),
50 NVME_REG_CMBMSC = offsetof(NvmeBar, cmbmsc),
51 NVME_REG_CMBSTS = offsetof(NvmeBar, cmbsts),
52 NVME_REG_PMRCAP = offsetof(NvmeBar, pmrcap),
53 NVME_REG_PMRCTL = offsetof(NvmeBar, pmrctl),
54 NVME_REG_PMRSTS = offsetof(NvmeBar, pmrsts),
55 NVME_REG_PMREBS = offsetof(NvmeBar, pmrebs),
56 NVME_REG_PMRSWTP = offsetof(NvmeBar, pmrswtp),
57 NVME_REG_PMRMSCL = offsetof(NvmeBar, pmrmscl),
58 NVME_REG_PMRMSCU = offsetof(NvmeBar, pmrmscu),
59};
60
61enum NvmeCapShift {
62 CAP_MQES_SHIFT = 0,
63 CAP_CQR_SHIFT = 16,
64 CAP_AMS_SHIFT = 17,
65 CAP_TO_SHIFT = 24,
66 CAP_DSTRD_SHIFT = 32,
67 CAP_NSSRS_SHIFT = 36,
68 CAP_CSS_SHIFT = 37,
69 CAP_MPSMIN_SHIFT = 48,
70 CAP_MPSMAX_SHIFT = 52,
71 CAP_PMRS_SHIFT = 56,
72 CAP_CMBS_SHIFT = 57,
73};
74
75enum NvmeCapMask {
76 CAP_MQES_MASK = 0xffff,
77 CAP_CQR_MASK = 0x1,
78 CAP_AMS_MASK = 0x3,
79 CAP_TO_MASK = 0xff,
80 CAP_DSTRD_MASK = 0xf,
81 CAP_NSSRS_MASK = 0x1,
82 CAP_CSS_MASK = 0xff,
83 CAP_MPSMIN_MASK = 0xf,
84 CAP_MPSMAX_MASK = 0xf,
85 CAP_PMRS_MASK = 0x1,
86 CAP_CMBS_MASK = 0x1,
87};
88
89#define NVME_CAP_MQES(cap) (((cap) >> CAP_MQES_SHIFT) & CAP_MQES_MASK)
90#define NVME_CAP_CQR(cap) (((cap) >> CAP_CQR_SHIFT) & CAP_CQR_MASK)
91#define NVME_CAP_AMS(cap) (((cap) >> CAP_AMS_SHIFT) & CAP_AMS_MASK)
92#define NVME_CAP_TO(cap) (((cap) >> CAP_TO_SHIFT) & CAP_TO_MASK)
93#define NVME_CAP_DSTRD(cap) (((cap) >> CAP_DSTRD_SHIFT) & CAP_DSTRD_MASK)
94#define NVME_CAP_NSSRS(cap) (((cap) >> CAP_NSSRS_SHIFT) & CAP_NSSRS_MASK)
95#define NVME_CAP_CSS(cap) (((cap) >> CAP_CSS_SHIFT) & CAP_CSS_MASK)
96#define NVME_CAP_MPSMIN(cap)(((cap) >> CAP_MPSMIN_SHIFT) & CAP_MPSMIN_MASK)
97#define NVME_CAP_MPSMAX(cap)(((cap) >> CAP_MPSMAX_SHIFT) & CAP_MPSMAX_MASK)
98#define NVME_CAP_PMRS(cap) (((cap) >> CAP_PMRS_SHIFT) & CAP_PMRS_MASK)
99#define NVME_CAP_CMBS(cap) (((cap) >> CAP_CMBS_SHIFT) & CAP_CMBS_MASK)
100
101#define NVME_CAP_SET_MQES(cap, val) \
102 ((cap) |= (uint64_t)((val) & CAP_MQES_MASK) << CAP_MQES_SHIFT)
103#define NVME_CAP_SET_CQR(cap, val) \
104 ((cap) |= (uint64_t)((val) & CAP_CQR_MASK) << CAP_CQR_SHIFT)
105#define NVME_CAP_SET_AMS(cap, val) \
106 ((cap) |= (uint64_t)((val) & CAP_AMS_MASK) << CAP_AMS_SHIFT)
107#define NVME_CAP_SET_TO(cap, val) \
108 ((cap) |= (uint64_t)((val) & CAP_TO_MASK) << CAP_TO_SHIFT)
109#define NVME_CAP_SET_DSTRD(cap, val) \
110 ((cap) |= (uint64_t)((val) & CAP_DSTRD_MASK) << CAP_DSTRD_SHIFT)
111#define NVME_CAP_SET_NSSRS(cap, val) \
112 ((cap) |= (uint64_t)((val) & CAP_NSSRS_MASK) << CAP_NSSRS_SHIFT)
113#define NVME_CAP_SET_CSS(cap, val) \
114 ((cap) |= (uint64_t)((val) & CAP_CSS_MASK) << CAP_CSS_SHIFT)
115#define NVME_CAP_SET_MPSMIN(cap, val) \
116 ((cap) |= (uint64_t)((val) & CAP_MPSMIN_MASK) << CAP_MPSMIN_SHIFT)
117#define NVME_CAP_SET_MPSMAX(cap, val) \
118 ((cap) |= (uint64_t)((val) & CAP_MPSMAX_MASK) << CAP_MPSMAX_SHIFT)
119#define NVME_CAP_SET_PMRS(cap, val) \
120 ((cap) |= (uint64_t)((val) & CAP_PMRS_MASK) << CAP_PMRS_SHIFT)
121#define NVME_CAP_SET_CMBS(cap, val) \
122 ((cap) |= (uint64_t)((val) & CAP_CMBS_MASK) << CAP_CMBS_SHIFT)
123
124enum NvmeCapCss {
125 NVME_CAP_CSS_NVM = 1 << 0,
126 NVME_CAP_CSS_CSI_SUPP = 1 << 6,
127 NVME_CAP_CSS_ADMIN_ONLY = 1 << 7,
128};
129
130enum NvmeCcShift {
131 CC_EN_SHIFT = 0,
132 CC_CSS_SHIFT = 4,
133 CC_MPS_SHIFT = 7,
134 CC_AMS_SHIFT = 11,
135 CC_SHN_SHIFT = 14,
136 CC_IOSQES_SHIFT = 16,
137 CC_IOCQES_SHIFT = 20,
138};
139
140enum NvmeCcMask {
141 CC_EN_MASK = 0x1,
142 CC_CSS_MASK = 0x7,
143 CC_MPS_MASK = 0xf,
144 CC_AMS_MASK = 0x7,
145 CC_SHN_MASK = 0x3,
146 CC_IOSQES_MASK = 0xf,
147 CC_IOCQES_MASK = 0xf,
148};
149
150#define NVME_CC_EN(cc) ((cc >> CC_EN_SHIFT) & CC_EN_MASK)
151#define NVME_CC_CSS(cc) ((cc >> CC_CSS_SHIFT) & CC_CSS_MASK)
152#define NVME_CC_MPS(cc) ((cc >> CC_MPS_SHIFT) & CC_MPS_MASK)
153#define NVME_CC_AMS(cc) ((cc >> CC_AMS_SHIFT) & CC_AMS_MASK)
154#define NVME_CC_SHN(cc) ((cc >> CC_SHN_SHIFT) & CC_SHN_MASK)
155#define NVME_CC_IOSQES(cc) ((cc >> CC_IOSQES_SHIFT) & CC_IOSQES_MASK)
156#define NVME_CC_IOCQES(cc) ((cc >> CC_IOCQES_SHIFT) & CC_IOCQES_MASK)
157
158enum NvmeCcCss {
159 NVME_CC_CSS_NVM = 0x0,
160 NVME_CC_CSS_CSI = 0x6,
161 NVME_CC_CSS_ADMIN_ONLY = 0x7,
162};
163
164#define NVME_SET_CC_EN(cc, val) \
165 (cc |= (uint32_t)((val) & CC_EN_MASK) << CC_EN_SHIFT)
166#define NVME_SET_CC_CSS(cc, val) \
167 (cc |= (uint32_t)((val) & CC_CSS_MASK) << CC_CSS_SHIFT)
168#define NVME_SET_CC_MPS(cc, val) \
169 (cc |= (uint32_t)((val) & CC_MPS_MASK) << CC_MPS_SHIFT)
170#define NVME_SET_CC_AMS(cc, val) \
171 (cc |= (uint32_t)((val) & CC_AMS_MASK) << CC_AMS_SHIFT)
172#define NVME_SET_CC_SHN(cc, val) \
173 (cc |= (uint32_t)((val) & CC_SHN_MASK) << CC_SHN_SHIFT)
174#define NVME_SET_CC_IOSQES(cc, val) \
175 (cc |= (uint32_t)((val) & CC_IOSQES_MASK) << CC_IOSQES_SHIFT)
176#define NVME_SET_CC_IOCQES(cc, val) \
177 (cc |= (uint32_t)((val) & CC_IOCQES_MASK) << CC_IOCQES_SHIFT)
178
179enum NvmeCstsShift {
180 CSTS_RDY_SHIFT = 0,
181 CSTS_CFS_SHIFT = 1,
182 CSTS_SHST_SHIFT = 2,
183 CSTS_NSSRO_SHIFT = 4,
184};
185
186enum NvmeCstsMask {
187 CSTS_RDY_MASK = 0x1,
188 CSTS_CFS_MASK = 0x1,
189 CSTS_SHST_MASK = 0x3,
190 CSTS_NSSRO_MASK = 0x1,
191};
192
193enum NvmeCsts {
194 NVME_CSTS_READY = 1 << CSTS_RDY_SHIFT,
195 NVME_CSTS_FAILED = 1 << CSTS_CFS_SHIFT,
196 NVME_CSTS_SHST_NORMAL = 0 << CSTS_SHST_SHIFT,
197 NVME_CSTS_SHST_PROGRESS = 1 << CSTS_SHST_SHIFT,
198 NVME_CSTS_SHST_COMPLETE = 2 << CSTS_SHST_SHIFT,
199 NVME_CSTS_NSSRO = 1 << CSTS_NSSRO_SHIFT,
200};
201
202#define NVME_CSTS_RDY(csts) ((csts >> CSTS_RDY_SHIFT) & CSTS_RDY_MASK)
203#define NVME_CSTS_CFS(csts) ((csts >> CSTS_CFS_SHIFT) & CSTS_CFS_MASK)
204#define NVME_CSTS_SHST(csts) ((csts >> CSTS_SHST_SHIFT) & CSTS_SHST_MASK)
205#define NVME_CSTS_NSSRO(csts) ((csts >> CSTS_NSSRO_SHIFT) & CSTS_NSSRO_MASK)
206
207enum NvmeAqaShift {
208 AQA_ASQS_SHIFT = 0,
209 AQA_ACQS_SHIFT = 16,
210};
211
212enum NvmeAqaMask {
213 AQA_ASQS_MASK = 0xfff,
214 AQA_ACQS_MASK = 0xfff,
215};
216
217#define NVME_AQA_ASQS(aqa) ((aqa >> AQA_ASQS_SHIFT) & AQA_ASQS_MASK)
218#define NVME_AQA_ACQS(aqa) ((aqa >> AQA_ACQS_SHIFT) & AQA_ACQS_MASK)
219
220enum NvmeCmblocShift {
221 CMBLOC_BIR_SHIFT = 0,
222 CMBLOC_CQMMS_SHIFT = 3,
223 CMBLOC_CQPDS_SHIFT = 4,
224 CMBLOC_CDPMLS_SHIFT = 5,
225 CMBLOC_CDPCILS_SHIFT = 6,
226 CMBLOC_CDMMMS_SHIFT = 7,
227 CMBLOC_CQDA_SHIFT = 8,
228 CMBLOC_OFST_SHIFT = 12,
229};
230
231enum NvmeCmblocMask {
232 CMBLOC_BIR_MASK = 0x7,
233 CMBLOC_CQMMS_MASK = 0x1,
234 CMBLOC_CQPDS_MASK = 0x1,
235 CMBLOC_CDPMLS_MASK = 0x1,
236 CMBLOC_CDPCILS_MASK = 0x1,
237 CMBLOC_CDMMMS_MASK = 0x1,
238 CMBLOC_CQDA_MASK = 0x1,
239 CMBLOC_OFST_MASK = 0xfffff,
240};
241
242#define NVME_CMBLOC_BIR(cmbloc) \
243 ((cmbloc >> CMBLOC_BIR_SHIFT) & CMBLOC_BIR_MASK)
244#define NVME_CMBLOC_CQMMS(cmbloc) \
245 ((cmbloc >> CMBLOC_CQMMS_SHIFT) & CMBLOC_CQMMS_MASK)
246#define NVME_CMBLOC_CQPDS(cmbloc) \
247 ((cmbloc >> CMBLOC_CQPDS_SHIFT) & CMBLOC_CQPDS_MASK)
248#define NVME_CMBLOC_CDPMLS(cmbloc) \
249 ((cmbloc >> CMBLOC_CDPMLS_SHIFT) & CMBLOC_CDPMLS_MASK)
250#define NVME_CMBLOC_CDPCILS(cmbloc) \
251 ((cmbloc >> CMBLOC_CDPCILS_SHIFT) & CMBLOC_CDPCILS_MASK)
252#define NVME_CMBLOC_CDMMMS(cmbloc) \
253 ((cmbloc >> CMBLOC_CDMMMS_SHIFT) & CMBLOC_CDMMMS_MASK)
254#define NVME_CMBLOC_CQDA(cmbloc) \
255 ((cmbloc >> CMBLOC_CQDA_SHIFT) & CMBLOC_CQDA_MASK)
256#define NVME_CMBLOC_OFST(cmbloc) \
257 ((cmbloc >> CMBLOC_OFST_SHIFT) & CMBLOC_OFST_MASK)
258
259#define NVME_CMBLOC_SET_BIR(cmbloc, val) \
260 (cmbloc |= (uint64_t)(val & CMBLOC_BIR_MASK) << CMBLOC_BIR_SHIFT)
261#define NVME_CMBLOC_SET_CQMMS(cmbloc, val) \
262 (cmbloc |= (uint64_t)(val & CMBLOC_CQMMS_MASK) << CMBLOC_CQMMS_SHIFT)
263#define NVME_CMBLOC_SET_CQPDS(cmbloc, val) \
264 (cmbloc |= (uint64_t)(val & CMBLOC_CQPDS_MASK) << CMBLOC_CQPDS_SHIFT)
265#define NVME_CMBLOC_SET_CDPMLS(cmbloc, val) \
266 (cmbloc |= (uint64_t)(val & CMBLOC_CDPMLS_MASK) << CMBLOC_CDPMLS_SHIFT)
267#define NVME_CMBLOC_SET_CDPCILS(cmbloc, val) \
268 (cmbloc |= (uint64_t)(val & CMBLOC_CDPCILS_MASK) << CMBLOC_CDPCILS_SHIFT)
269#define NVME_CMBLOC_SET_CDMMMS(cmbloc, val) \
270 (cmbloc |= (uint64_t)(val & CMBLOC_CDMMMS_MASK) << CMBLOC_CDMMMS_SHIFT)
271#define NVME_CMBLOC_SET_CQDA(cmbloc, val) \
272 (cmbloc |= (uint64_t)(val & CMBLOC_CQDA_MASK) << CMBLOC_CQDA_SHIFT)
273#define NVME_CMBLOC_SET_OFST(cmbloc, val) \
274 (cmbloc |= (uint64_t)(val & CMBLOC_OFST_MASK) << CMBLOC_OFST_SHIFT)
275
276#define NVME_CMBMSMC_SET_CRE (cmbmsc, val) \
277 (cmbmsc |= (uint64_t)(val & CMBLOC_OFST_MASK) << CMBMSC_CRE_SHIFT)
278
279enum NvmeCmbszShift {
280 CMBSZ_SQS_SHIFT = 0,
281 CMBSZ_CQS_SHIFT = 1,
282 CMBSZ_LISTS_SHIFT = 2,
283 CMBSZ_RDS_SHIFT = 3,
284 CMBSZ_WDS_SHIFT = 4,
285 CMBSZ_SZU_SHIFT = 8,
286 CMBSZ_SZ_SHIFT = 12,
287};
288
289enum NvmeCmbszMask {
290 CMBSZ_SQS_MASK = 0x1,
291 CMBSZ_CQS_MASK = 0x1,
292 CMBSZ_LISTS_MASK = 0x1,
293 CMBSZ_RDS_MASK = 0x1,
294 CMBSZ_WDS_MASK = 0x1,
295 CMBSZ_SZU_MASK = 0xf,
296 CMBSZ_SZ_MASK = 0xfffff,
297};
298
299#define NVME_CMBSZ_SQS(cmbsz) ((cmbsz >> CMBSZ_SQS_SHIFT) & CMBSZ_SQS_MASK)
300#define NVME_CMBSZ_CQS(cmbsz) ((cmbsz >> CMBSZ_CQS_SHIFT) & CMBSZ_CQS_MASK)
301#define NVME_CMBSZ_LISTS(cmbsz)((cmbsz >> CMBSZ_LISTS_SHIFT) & CMBSZ_LISTS_MASK)
302#define NVME_CMBSZ_RDS(cmbsz) ((cmbsz >> CMBSZ_RDS_SHIFT) & CMBSZ_RDS_MASK)
303#define NVME_CMBSZ_WDS(cmbsz) ((cmbsz >> CMBSZ_WDS_SHIFT) & CMBSZ_WDS_MASK)
304#define NVME_CMBSZ_SZU(cmbsz) ((cmbsz >> CMBSZ_SZU_SHIFT) & CMBSZ_SZU_MASK)
305#define NVME_CMBSZ_SZ(cmbsz) ((cmbsz >> CMBSZ_SZ_SHIFT) & CMBSZ_SZ_MASK)
306
307#define NVME_CMBSZ_SET_SQS(cmbsz, val) \
308 (cmbsz |= (uint64_t)(val & CMBSZ_SQS_MASK) << CMBSZ_SQS_SHIFT)
309#define NVME_CMBSZ_SET_CQS(cmbsz, val) \
310 (cmbsz |= (uint64_t)(val & CMBSZ_CQS_MASK) << CMBSZ_CQS_SHIFT)
311#define NVME_CMBSZ_SET_LISTS(cmbsz, val) \
312 (cmbsz |= (uint64_t)(val & CMBSZ_LISTS_MASK) << CMBSZ_LISTS_SHIFT)
313#define NVME_CMBSZ_SET_RDS(cmbsz, val) \
314 (cmbsz |= (uint64_t)(val & CMBSZ_RDS_MASK) << CMBSZ_RDS_SHIFT)
315#define NVME_CMBSZ_SET_WDS(cmbsz, val) \
316 (cmbsz |= (uint64_t)(val & CMBSZ_WDS_MASK) << CMBSZ_WDS_SHIFT)
317#define NVME_CMBSZ_SET_SZU(cmbsz, val) \
318 (cmbsz |= (uint64_t)(val & CMBSZ_SZU_MASK) << CMBSZ_SZU_SHIFT)
319#define NVME_CMBSZ_SET_SZ(cmbsz, val) \
320 (cmbsz |= (uint64_t)(val & CMBSZ_SZ_MASK) << CMBSZ_SZ_SHIFT)
321
322#define NVME_CMBSZ_GETSIZE(cmbsz) \
323 (NVME_CMBSZ_SZ(cmbsz) * (1 << (12 + 4 * NVME_CMBSZ_SZU(cmbsz))))
324
325enum NvmeCmbmscShift {
326 CMBMSC_CRE_SHIFT = 0,
327 CMBMSC_CMSE_SHIFT = 1,
328 CMBMSC_CBA_SHIFT = 12,
329};
330
331enum NvmeCmbmscMask {
332 CMBMSC_CRE_MASK = 0x1,
333 CMBMSC_CMSE_MASK = 0x1,
334 CMBMSC_CBA_MASK = ((1ULL << 52) - 1),
335};
336
337#define NVME_CMBMSC_CRE(cmbmsc) \
338 ((cmbmsc >> CMBMSC_CRE_SHIFT) & CMBMSC_CRE_MASK)
339#define NVME_CMBMSC_CMSE(cmbmsc) \
340 ((cmbmsc >> CMBMSC_CMSE_SHIFT) & CMBMSC_CMSE_MASK)
341#define NVME_CMBMSC_CBA(cmbmsc) \
342 ((cmbmsc >> CMBMSC_CBA_SHIFT) & CMBMSC_CBA_MASK)
343
344
345#define NVME_CMBMSC_SET_CRE(cmbmsc, val) \
346 (cmbmsc |= (uint64_t)(val & CMBMSC_CRE_MASK) << CMBMSC_CRE_SHIFT)
347#define NVME_CMBMSC_SET_CMSE(cmbmsc, val) \
348 (cmbmsc |= (uint64_t)(val & CMBMSC_CMSE_MASK) << CMBMSC_CMSE_SHIFT)
349#define NVME_CMBMSC_SET_CBA(cmbmsc, val) \
350 (cmbmsc |= (uint64_t)(val & CMBMSC_CBA_MASK) << CMBMSC_CBA_SHIFT)
351
352enum NvmeCmbstsShift {
353 CMBSTS_CBAI_SHIFT = 0,
354};
355enum NvmeCmbstsMask {
356 CMBSTS_CBAI_MASK = 0x1,
357};
358
359#define NVME_CMBSTS_CBAI(cmbsts) \
360 ((cmbsts >> CMBSTS_CBAI_SHIFT) & CMBSTS_CBAI_MASK)
361
362#define NVME_CMBSTS_SET_CBAI(cmbsts, val) \
363 (cmbsts |= (uint64_t)(val & CMBSTS_CBAI_MASK) << CMBSTS_CBAI_SHIFT)
364
365enum NvmePmrcapShift {
366 PMRCAP_RDS_SHIFT = 3,
367 PMRCAP_WDS_SHIFT = 4,
368 PMRCAP_BIR_SHIFT = 5,
369 PMRCAP_PMRTU_SHIFT = 8,
370 PMRCAP_PMRWBM_SHIFT = 10,
371 PMRCAP_PMRTO_SHIFT = 16,
372 PMRCAP_CMSS_SHIFT = 24,
373};
374
375enum NvmePmrcapMask {
376 PMRCAP_RDS_MASK = 0x1,
377 PMRCAP_WDS_MASK = 0x1,
378 PMRCAP_BIR_MASK = 0x7,
379 PMRCAP_PMRTU_MASK = 0x3,
380 PMRCAP_PMRWBM_MASK = 0xf,
381 PMRCAP_PMRTO_MASK = 0xff,
382 PMRCAP_CMSS_MASK = 0x1,
383};
384
385#define NVME_PMRCAP_RDS(pmrcap) \
386 ((pmrcap >> PMRCAP_RDS_SHIFT) & PMRCAP_RDS_MASK)
387#define NVME_PMRCAP_WDS(pmrcap) \
388 ((pmrcap >> PMRCAP_WDS_SHIFT) & PMRCAP_WDS_MASK)
389#define NVME_PMRCAP_BIR(pmrcap) \
390 ((pmrcap >> PMRCAP_BIR_SHIFT) & PMRCAP_BIR_MASK)
391#define NVME_PMRCAP_PMRTU(pmrcap) \
392 ((pmrcap >> PMRCAP_PMRTU_SHIFT) & PMRCAP_PMRTU_MASK)
393#define NVME_PMRCAP_PMRWBM(pmrcap) \
394 ((pmrcap >> PMRCAP_PMRWBM_SHIFT) & PMRCAP_PMRWBM_MASK)
395#define NVME_PMRCAP_PMRTO(pmrcap) \
396 ((pmrcap >> PMRCAP_PMRTO_SHIFT) & PMRCAP_PMRTO_MASK)
397#define NVME_PMRCAP_CMSS(pmrcap) \
398 ((pmrcap >> PMRCAP_CMSS_SHIFT) & PMRCAP_CMSS_MASK)
399
400#define NVME_PMRCAP_SET_RDS(pmrcap, val) \
401 (pmrcap |= (uint64_t)(val & PMRCAP_RDS_MASK) << PMRCAP_RDS_SHIFT)
402#define NVME_PMRCAP_SET_WDS(pmrcap, val) \
403 (pmrcap |= (uint64_t)(val & PMRCAP_WDS_MASK) << PMRCAP_WDS_SHIFT)
404#define NVME_PMRCAP_SET_BIR(pmrcap, val) \
405 (pmrcap |= (uint64_t)(val & PMRCAP_BIR_MASK) << PMRCAP_BIR_SHIFT)
406#define NVME_PMRCAP_SET_PMRTU(pmrcap, val) \
407 (pmrcap |= (uint64_t)(val & PMRCAP_PMRTU_MASK) << PMRCAP_PMRTU_SHIFT)
408#define NVME_PMRCAP_SET_PMRWBM(pmrcap, val) \
409 (pmrcap |= (uint64_t)(val & PMRCAP_PMRWBM_MASK) << PMRCAP_PMRWBM_SHIFT)
410#define NVME_PMRCAP_SET_PMRTO(pmrcap, val) \
411 (pmrcap |= (uint64_t)(val & PMRCAP_PMRTO_MASK) << PMRCAP_PMRTO_SHIFT)
412#define NVME_PMRCAP_SET_CMSS(pmrcap, val) \
413 (pmrcap |= (uint64_t)(val & PMRCAP_CMSS_MASK) << PMRCAP_CMSS_SHIFT)
414
415enum NvmePmrctlShift {
416 PMRCTL_EN_SHIFT = 0,
417};
418
419enum NvmePmrctlMask {
420 PMRCTL_EN_MASK = 0x1,
421};
422
423#define NVME_PMRCTL_EN(pmrctl) ((pmrctl >> PMRCTL_EN_SHIFT) & PMRCTL_EN_MASK)
424
425#define NVME_PMRCTL_SET_EN(pmrctl, val) \
426 (pmrctl |= (uint64_t)(val & PMRCTL_EN_MASK) << PMRCTL_EN_SHIFT)
427
428enum NvmePmrstsShift {
429 PMRSTS_ERR_SHIFT = 0,
430 PMRSTS_NRDY_SHIFT = 8,
431 PMRSTS_HSTS_SHIFT = 9,
432 PMRSTS_CBAI_SHIFT = 12,
433};
434
435enum NvmePmrstsMask {
436 PMRSTS_ERR_MASK = 0xff,
437 PMRSTS_NRDY_MASK = 0x1,
438 PMRSTS_HSTS_MASK = 0x7,
439 PMRSTS_CBAI_MASK = 0x1,
440};
441
442#define NVME_PMRSTS_ERR(pmrsts) \
443 ((pmrsts >> PMRSTS_ERR_SHIFT) & PMRSTS_ERR_MASK)
444#define NVME_PMRSTS_NRDY(pmrsts) \
445 ((pmrsts >> PMRSTS_NRDY_SHIFT) & PMRSTS_NRDY_MASK)
446#define NVME_PMRSTS_HSTS(pmrsts) \
447 ((pmrsts >> PMRSTS_HSTS_SHIFT) & PMRSTS_HSTS_MASK)
448#define NVME_PMRSTS_CBAI(pmrsts) \
449 ((pmrsts >> PMRSTS_CBAI_SHIFT) & PMRSTS_CBAI_MASK)
450
451#define NVME_PMRSTS_SET_ERR(pmrsts, val) \
452 (pmrsts |= (uint64_t)(val & PMRSTS_ERR_MASK) << PMRSTS_ERR_SHIFT)
453#define NVME_PMRSTS_SET_NRDY(pmrsts, val) \
454 (pmrsts |= (uint64_t)(val & PMRSTS_NRDY_MASK) << PMRSTS_NRDY_SHIFT)
455#define NVME_PMRSTS_SET_HSTS(pmrsts, val) \
456 (pmrsts |= (uint64_t)(val & PMRSTS_HSTS_MASK) << PMRSTS_HSTS_SHIFT)
457#define NVME_PMRSTS_SET_CBAI(pmrsts, val) \
458 (pmrsts |= (uint64_t)(val & PMRSTS_CBAI_MASK) << PMRSTS_CBAI_SHIFT)
459
460enum NvmePmrebsShift {
461 PMREBS_PMRSZU_SHIFT = 0,
462 PMREBS_RBB_SHIFT = 4,
463 PMREBS_PMRWBZ_SHIFT = 8,
464};
465
466enum NvmePmrebsMask {
467 PMREBS_PMRSZU_MASK = 0xf,
468 PMREBS_RBB_MASK = 0x1,
469 PMREBS_PMRWBZ_MASK = 0xffffff,
470};
471
472#define NVME_PMREBS_PMRSZU(pmrebs) \
473 ((pmrebs >> PMREBS_PMRSZU_SHIFT) & PMREBS_PMRSZU_MASK)
474#define NVME_PMREBS_RBB(pmrebs) \
475 ((pmrebs >> PMREBS_RBB_SHIFT) & PMREBS_RBB_MASK)
476#define NVME_PMREBS_PMRWBZ(pmrebs) \
477 ((pmrebs >> PMREBS_PMRWBZ_SHIFT) & PMREBS_PMRWBZ_MASK)
478
479#define NVME_PMREBS_SET_PMRSZU(pmrebs, val) \
480 (pmrebs |= (uint64_t)(val & PMREBS_PMRSZU_MASK) << PMREBS_PMRSZU_SHIFT)
481#define NVME_PMREBS_SET_RBB(pmrebs, val) \
482 (pmrebs |= (uint64_t)(val & PMREBS_RBB_MASK) << PMREBS_RBB_SHIFT)
483#define NVME_PMREBS_SET_PMRWBZ(pmrebs, val) \
484 (pmrebs |= (uint64_t)(val & PMREBS_PMRWBZ_MASK) << PMREBS_PMRWBZ_SHIFT)
485
486enum NvmePmrswtpShift {
487 PMRSWTP_PMRSWTU_SHIFT = 0,
488 PMRSWTP_PMRSWTV_SHIFT = 8,
489};
490
491enum NvmePmrswtpMask {
492 PMRSWTP_PMRSWTU_MASK = 0xf,
493 PMRSWTP_PMRSWTV_MASK = 0xffffff,
494};
495
496#define NVME_PMRSWTP_PMRSWTU(pmrswtp) \
497 ((pmrswtp >> PMRSWTP_PMRSWTU_SHIFT) & PMRSWTP_PMRSWTU_MASK)
498#define NVME_PMRSWTP_PMRSWTV(pmrswtp) \
499 ((pmrswtp >> PMRSWTP_PMRSWTV_SHIFT) & PMRSWTP_PMRSWTV_MASK)
500
501#define NVME_PMRSWTP_SET_PMRSWTU(pmrswtp, val) \
502 (pmrswtp |= (uint64_t)(val & PMRSWTP_PMRSWTU_MASK) << PMRSWTP_PMRSWTU_SHIFT)
503#define NVME_PMRSWTP_SET_PMRSWTV(pmrswtp, val) \
504 (pmrswtp |= (uint64_t)(val & PMRSWTP_PMRSWTV_MASK) << PMRSWTP_PMRSWTV_SHIFT)
505
506enum NvmePmrmsclShift {
507 PMRMSCL_CMSE_SHIFT = 1,
508 PMRMSCL_CBA_SHIFT = 12,
509};
510
511enum NvmePmrmsclMask {
512 PMRMSCL_CMSE_MASK = 0x1,
513 PMRMSCL_CBA_MASK = 0xfffff,
514};
515
516#define NVME_PMRMSCL_CMSE(pmrmscl) \
517 ((pmrmscl >> PMRMSCL_CMSE_SHIFT) & PMRMSCL_CMSE_MASK)
518#define NVME_PMRMSCL_CBA(pmrmscl) \
519 ((pmrmscl >> PMRMSCL_CBA_SHIFT) & PMRMSCL_CBA_MASK)
520
521#define NVME_PMRMSCL_SET_CMSE(pmrmscl, val) \
522 (pmrmscl |= (uint32_t)(val & PMRMSCL_CMSE_MASK) << PMRMSCL_CMSE_SHIFT)
523#define NVME_PMRMSCL_SET_CBA(pmrmscl, val) \
524 (pmrmscl |= (uint32_t)(val & PMRMSCL_CBA_MASK) << PMRMSCL_CBA_SHIFT)
525
526enum NvmeSglDescriptorType {
527 NVME_SGL_DESCR_TYPE_DATA_BLOCK = 0x0,
528 NVME_SGL_DESCR_TYPE_BIT_BUCKET = 0x1,
529 NVME_SGL_DESCR_TYPE_SEGMENT = 0x2,
530 NVME_SGL_DESCR_TYPE_LAST_SEGMENT = 0x3,
531 NVME_SGL_DESCR_TYPE_KEYED_DATA_BLOCK = 0x4,
532
533 NVME_SGL_DESCR_TYPE_VENDOR_SPECIFIC = 0xf,
534};
535
536enum NvmeSglDescriptorSubtype {
537 NVME_SGL_DESCR_SUBTYPE_ADDRESS = 0x0,
538};
539
540typedef struct QEMU_PACKED NvmeSglDescriptor {
541 uint64_t addr;
542 uint32_t len;
543 uint8_t rsvd[3];
544 uint8_t type;
545} NvmeSglDescriptor;
546
547#define NVME_SGL_TYPE(type) ((type >> 4) & 0xf)
548#define NVME_SGL_SUBTYPE(type) (type & 0xf)
549
550typedef union NvmeCmdDptr {
551 struct {
552 uint64_t prp1;
553 uint64_t prp2;
554 };
555
556 NvmeSglDescriptor sgl;
557} NvmeCmdDptr;
558
559enum NvmePsdt {
560 NVME_PSDT_PRP = 0x0,
561 NVME_PSDT_SGL_MPTR_CONTIGUOUS = 0x1,
562 NVME_PSDT_SGL_MPTR_SGL = 0x2,
563};
564
565typedef struct QEMU_PACKED NvmeCmd {
566 uint8_t opcode;
567 uint8_t flags;
568 uint16_t cid;
569 uint32_t nsid;
570 uint64_t res1;
571 uint64_t mptr;
572 NvmeCmdDptr dptr;
573 uint32_t cdw10;
574 uint32_t cdw11;
575 uint32_t cdw12;
576 uint32_t cdw13;
577 uint32_t cdw14;
578 uint32_t cdw15;
579} NvmeCmd;
580
581#define NVME_CMD_FLAGS_FUSE(flags) (flags & 0x3)
582#define NVME_CMD_FLAGS_PSDT(flags) ((flags >> 6) & 0x3)
583
584enum NvmeAdminCommands {
585 NVME_ADM_CMD_DELETE_SQ = 0x00,
586 NVME_ADM_CMD_CREATE_SQ = 0x01,
587 NVME_ADM_CMD_GET_LOG_PAGE = 0x02,
588 NVME_ADM_CMD_DELETE_CQ = 0x04,
589 NVME_ADM_CMD_CREATE_CQ = 0x05,
590 NVME_ADM_CMD_IDENTIFY = 0x06,
591 NVME_ADM_CMD_ABORT = 0x08,
592 NVME_ADM_CMD_SET_FEATURES = 0x09,
593 NVME_ADM_CMD_GET_FEATURES = 0x0a,
594 NVME_ADM_CMD_ASYNC_EV_REQ = 0x0c,
595 NVME_ADM_CMD_ACTIVATE_FW = 0x10,
596 NVME_ADM_CMD_DOWNLOAD_FW = 0x11,
597 NVME_ADM_CMD_NS_ATTACHMENT = 0x15,
598 NVME_ADM_CMD_VIRT_MNGMT = 0x1c,
599 NVME_ADM_CMD_DBBUF_CONFIG = 0x7c,
600 NVME_ADM_CMD_FORMAT_NVM = 0x80,
601 NVME_ADM_CMD_SECURITY_SEND = 0x81,
602 NVME_ADM_CMD_SECURITY_RECV = 0x82,
603};
604
605enum NvmeIoCommands {
606 NVME_CMD_FLUSH = 0x00,
607 NVME_CMD_WRITE = 0x01,
608 NVME_CMD_READ = 0x02,
609 NVME_CMD_WRITE_UNCOR = 0x04,
610 NVME_CMD_COMPARE = 0x05,
611 NVME_CMD_WRITE_ZEROES = 0x08,
612 NVME_CMD_DSM = 0x09,
613 NVME_CMD_VERIFY = 0x0c,
614 NVME_CMD_COPY = 0x19,
615 NVME_CMD_ZONE_MGMT_SEND = 0x79,
616 NVME_CMD_ZONE_MGMT_RECV = 0x7a,
617 NVME_CMD_ZONE_APPEND = 0x7d,
618};
619
620typedef struct QEMU_PACKED NvmeDeleteQ {
621 uint8_t opcode;
622 uint8_t flags;
623 uint16_t cid;
624 uint32_t rsvd1[9];
625 uint16_t qid;
626 uint16_t rsvd10;
627 uint32_t rsvd11[5];
628} NvmeDeleteQ;
629
630typedef struct QEMU_PACKED NvmeCreateCq {
631 uint8_t opcode;
632 uint8_t flags;
633 uint16_t cid;
634 uint32_t rsvd1[5];
635 uint64_t prp1;
636 uint64_t rsvd8;
637 uint16_t cqid;
638 uint16_t qsize;
639 uint16_t cq_flags;
640 uint16_t irq_vector;
641 uint32_t rsvd12[4];
642} NvmeCreateCq;
643
644#define NVME_CQ_FLAGS_PC(cq_flags) (cq_flags & 0x1)
645#define NVME_CQ_FLAGS_IEN(cq_flags) ((cq_flags >> 1) & 0x1)
646
647enum NvmeFlagsCq {
648 NVME_CQ_PC = 1,
649 NVME_CQ_IEN = 2,
650};
651
652typedef struct QEMU_PACKED NvmeCreateSq {
653 uint8_t opcode;
654 uint8_t flags;
655 uint16_t cid;
656 uint32_t rsvd1[5];
657 uint64_t prp1;
658 uint64_t rsvd8;
659 uint16_t sqid;
660 uint16_t qsize;
661 uint16_t sq_flags;
662 uint16_t cqid;
663 uint32_t rsvd12[4];
664} NvmeCreateSq;
665
666#define NVME_SQ_FLAGS_PC(sq_flags) (sq_flags & 0x1)
667#define NVME_SQ_FLAGS_QPRIO(sq_flags) ((sq_flags >> 1) & 0x3)
668
669enum NvmeFlagsSq {
670 NVME_SQ_PC = 1,
671
672 NVME_SQ_PRIO_URGENT = 0,
673 NVME_SQ_PRIO_HIGH = 1,
674 NVME_SQ_PRIO_NORMAL = 2,
675 NVME_SQ_PRIO_LOW = 3,
676};
677
678typedef struct QEMU_PACKED NvmeIdentify {
679 uint8_t opcode;
680 uint8_t flags;
681 uint16_t cid;
682 uint32_t nsid;
683 uint64_t rsvd2[2];
684 uint64_t prp1;
685 uint64_t prp2;
686 uint8_t cns;
687 uint8_t rsvd10;
688 uint16_t ctrlid;
689 uint16_t nvmsetid;
690 uint8_t rsvd11;
691 uint8_t csi;
692 uint32_t rsvd12[4];
693} NvmeIdentify;
694
695typedef struct QEMU_PACKED NvmeRwCmd {
696 uint8_t opcode;
697 uint8_t flags;
698 uint16_t cid;
699 uint32_t nsid;
700 uint32_t cdw2;
701 uint32_t cdw3;
702 uint64_t mptr;
703 NvmeCmdDptr dptr;
704 uint64_t slba;
705 uint16_t nlb;
706 uint16_t control;
707 uint32_t dsmgmt;
708 uint32_t reftag;
709 uint16_t apptag;
710 uint16_t appmask;
711} NvmeRwCmd;
712
713enum {
714 NVME_RW_LR = 1 << 15,
715 NVME_RW_FUA = 1 << 14,
716 NVME_RW_DSM_FREQ_UNSPEC = 0,
717 NVME_RW_DSM_FREQ_TYPICAL = 1,
718 NVME_RW_DSM_FREQ_RARE = 2,
719 NVME_RW_DSM_FREQ_READS = 3,
720 NVME_RW_DSM_FREQ_WRITES = 4,
721 NVME_RW_DSM_FREQ_RW = 5,
722 NVME_RW_DSM_FREQ_ONCE = 6,
723 NVME_RW_DSM_FREQ_PREFETCH = 7,
724 NVME_RW_DSM_FREQ_TEMP = 8,
725 NVME_RW_DSM_LATENCY_NONE = 0 << 4,
726 NVME_RW_DSM_LATENCY_IDLE = 1 << 4,
727 NVME_RW_DSM_LATENCY_NORM = 2 << 4,
728 NVME_RW_DSM_LATENCY_LOW = 3 << 4,
729 NVME_RW_DSM_SEQ_REQ = 1 << 6,
730 NVME_RW_DSM_COMPRESSED = 1 << 7,
731 NVME_RW_PIREMAP = 1 << 9,
732 NVME_RW_PRINFO_PRACT = 1 << 13,
733 NVME_RW_PRINFO_PRCHK_GUARD = 1 << 12,
734 NVME_RW_PRINFO_PRCHK_APP = 1 << 11,
735 NVME_RW_PRINFO_PRCHK_REF = 1 << 10,
736 NVME_RW_PRINFO_PRCHK_MASK = 7 << 10,
737};
738
739#define NVME_RW_PRINFO(control) ((control >> 10) & 0xf)
740
741enum {
742 NVME_PRINFO_PRACT = 1 << 3,
743 NVME_PRINFO_PRCHK_GUARD = 1 << 2,
744 NVME_PRINFO_PRCHK_APP = 1 << 1,
745 NVME_PRINFO_PRCHK_REF = 1 << 0,
746 NVME_PRINFO_PRCHK_MASK = 7 << 0,
747};
748
749typedef struct QEMU_PACKED NvmeDsmCmd {
750 uint8_t opcode;
751 uint8_t flags;
752 uint16_t cid;
753 uint32_t nsid;
754 uint64_t rsvd2[2];
755 NvmeCmdDptr dptr;
756 uint32_t nr;
757 uint32_t attributes;
758 uint32_t rsvd12[4];
759} NvmeDsmCmd;
760
761enum {
762 NVME_DSMGMT_IDR = 1 << 0,
763 NVME_DSMGMT_IDW = 1 << 1,
764 NVME_DSMGMT_AD = 1 << 2,
765};
766
767typedef struct QEMU_PACKED NvmeDsmRange {
768 uint32_t cattr;
769 uint32_t nlb;
770 uint64_t slba;
771} NvmeDsmRange;
772
773enum {
774 NVME_COPY_FORMAT_0 = 0x0,
775 NVME_COPY_FORMAT_1 = 0x1,
776};
777
778typedef struct QEMU_PACKED NvmeCopyCmd {
779 uint8_t opcode;
780 uint8_t flags;
781 uint16_t cid;
782 uint32_t nsid;
783 uint32_t cdw2;
784 uint32_t cdw3;
785 uint32_t rsvd2[2];
786 NvmeCmdDptr dptr;
787 uint64_t sdlba;
788 uint8_t nr;
789 uint8_t control[3];
790 uint16_t rsvd13;
791 uint16_t dspec;
792 uint32_t reftag;
793 uint16_t apptag;
794 uint16_t appmask;
795} NvmeCopyCmd;
796
797typedef struct QEMU_PACKED NvmeCopySourceRangeFormat0 {
798 uint8_t rsvd0[8];
799 uint64_t slba;
800 uint16_t nlb;
801 uint8_t rsvd18[6];
802 uint32_t reftag;
803 uint16_t apptag;
804 uint16_t appmask;
805} NvmeCopySourceRangeFormat0;
806
807typedef struct QEMU_PACKED NvmeCopySourceRangeFormat1 {
808 uint8_t rsvd0[8];
809 uint64_t slba;
810 uint16_t nlb;
811 uint8_t rsvd18[8];
812 uint8_t sr[10];
813 uint16_t apptag;
814 uint16_t appmask;
815} NvmeCopySourceRangeFormat1;
816
817enum NvmeAsyncEventRequest {
818 NVME_AER_TYPE_ERROR = 0,
819 NVME_AER_TYPE_SMART = 1,
820 NVME_AER_TYPE_NOTICE = 2,
821 NVME_AER_TYPE_IO_SPECIFIC = 6,
822 NVME_AER_TYPE_VENDOR_SPECIFIC = 7,
823 NVME_AER_INFO_ERR_INVALID_DB_REGISTER = 0,
824 NVME_AER_INFO_ERR_INVALID_DB_VALUE = 1,
825 NVME_AER_INFO_ERR_DIAG_FAIL = 2,
826 NVME_AER_INFO_ERR_PERS_INTERNAL_ERR = 3,
827 NVME_AER_INFO_ERR_TRANS_INTERNAL_ERR = 4,
828 NVME_AER_INFO_ERR_FW_IMG_LOAD_ERR = 5,
829 NVME_AER_INFO_SMART_RELIABILITY = 0,
830 NVME_AER_INFO_SMART_TEMP_THRESH = 1,
831 NVME_AER_INFO_SMART_SPARE_THRESH = 2,
832 NVME_AER_INFO_NOTICE_NS_ATTR_CHANGED = 0,
833};
834
835typedef struct QEMU_PACKED NvmeAerResult {
836 uint8_t event_type;
837 uint8_t event_info;
838 uint8_t log_page;
839 uint8_t resv;
840} NvmeAerResult;
841
842typedef struct QEMU_PACKED NvmeZonedResult {
843 uint64_t slba;
844} NvmeZonedResult;
845
846typedef struct QEMU_PACKED NvmeCqe {
847 uint32_t result;
848 uint32_t dw1;
849 uint16_t sq_head;
850 uint16_t sq_id;
851 uint16_t cid;
852 uint16_t status;
853} NvmeCqe;
854
855enum NvmeStatusCodes {
856 NVME_SUCCESS = 0x0000,
857 NVME_INVALID_OPCODE = 0x0001,
858 NVME_INVALID_FIELD = 0x0002,
859 NVME_CID_CONFLICT = 0x0003,
860 NVME_DATA_TRAS_ERROR = 0x0004,
861 NVME_POWER_LOSS_ABORT = 0x0005,
862 NVME_INTERNAL_DEV_ERROR = 0x0006,
863 NVME_CMD_ABORT_REQ = 0x0007,
864 NVME_CMD_ABORT_SQ_DEL = 0x0008,
865 NVME_CMD_ABORT_FAILED_FUSE = 0x0009,
866 NVME_CMD_ABORT_MISSING_FUSE = 0x000a,
867 NVME_INVALID_NSID = 0x000b,
868 NVME_CMD_SEQ_ERROR = 0x000c,
869 NVME_INVALID_SGL_SEG_DESCR = 0x000d,
870 NVME_INVALID_NUM_SGL_DESCRS = 0x000e,
871 NVME_DATA_SGL_LEN_INVALID = 0x000f,
872 NVME_MD_SGL_LEN_INVALID = 0x0010,
873 NVME_SGL_DESCR_TYPE_INVALID = 0x0011,
874 NVME_INVALID_USE_OF_CMB = 0x0012,
875 NVME_INVALID_PRP_OFFSET = 0x0013,
876 NVME_CMD_SET_CMB_REJECTED = 0x002b,
877 NVME_INVALID_CMD_SET = 0x002c,
878 NVME_LBA_RANGE = 0x0080,
879 NVME_CAP_EXCEEDED = 0x0081,
880 NVME_NS_NOT_READY = 0x0082,
881 NVME_NS_RESV_CONFLICT = 0x0083,
882 NVME_FORMAT_IN_PROGRESS = 0x0084,
883 NVME_INVALID_CQID = 0x0100,
884 NVME_INVALID_QID = 0x0101,
885 NVME_MAX_QSIZE_EXCEEDED = 0x0102,
886 NVME_ACL_EXCEEDED = 0x0103,
887 NVME_RESERVED = 0x0104,
888 NVME_AER_LIMIT_EXCEEDED = 0x0105,
889 NVME_INVALID_FW_SLOT = 0x0106,
890 NVME_INVALID_FW_IMAGE = 0x0107,
891 NVME_INVALID_IRQ_VECTOR = 0x0108,
892 NVME_INVALID_LOG_ID = 0x0109,
893 NVME_INVALID_FORMAT = 0x010a,
894 NVME_FW_REQ_RESET = 0x010b,
895 NVME_INVALID_QUEUE_DEL = 0x010c,
896 NVME_FID_NOT_SAVEABLE = 0x010d,
897 NVME_FEAT_NOT_CHANGEABLE = 0x010e,
898 NVME_FEAT_NOT_NS_SPEC = 0x010f,
899 NVME_FW_REQ_SUSYSTEM_RESET = 0x0110,
900 NVME_NS_ALREADY_ATTACHED = 0x0118,
901 NVME_NS_PRIVATE = 0x0119,
902 NVME_NS_NOT_ATTACHED = 0x011a,
903 NVME_NS_CTRL_LIST_INVALID = 0x011c,
904 NVME_INVALID_CTRL_ID = 0x011f,
905 NVME_INVALID_SEC_CTRL_STATE = 0x0120,
906 NVME_INVALID_NUM_RESOURCES = 0x0121,
907 NVME_INVALID_RESOURCE_ID = 0x0122,
908 NVME_CONFLICTING_ATTRS = 0x0180,
909 NVME_INVALID_PROT_INFO = 0x0181,
910 NVME_WRITE_TO_RO = 0x0182,
911 NVME_CMD_SIZE_LIMIT = 0x0183,
912 NVME_INVALID_ZONE_OP = 0x01b6,
913 NVME_NOZRWA = 0x01b7,
914 NVME_ZONE_BOUNDARY_ERROR = 0x01b8,
915 NVME_ZONE_FULL = 0x01b9,
916 NVME_ZONE_READ_ONLY = 0x01ba,
917 NVME_ZONE_OFFLINE = 0x01bb,
918 NVME_ZONE_INVALID_WRITE = 0x01bc,
919 NVME_ZONE_TOO_MANY_ACTIVE = 0x01bd,
920 NVME_ZONE_TOO_MANY_OPEN = 0x01be,
921 NVME_ZONE_INVAL_TRANSITION = 0x01bf,
922 NVME_WRITE_FAULT = 0x0280,
923 NVME_UNRECOVERED_READ = 0x0281,
924 NVME_E2E_GUARD_ERROR = 0x0282,
925 NVME_E2E_APP_ERROR = 0x0283,
926 NVME_E2E_REF_ERROR = 0x0284,
927 NVME_CMP_FAILURE = 0x0285,
928 NVME_ACCESS_DENIED = 0x0286,
929 NVME_DULB = 0x0287,
930 NVME_E2E_STORAGE_TAG_ERROR = 0x0288,
931 NVME_MORE = 0x2000,
932 NVME_DNR = 0x4000,
933 NVME_NO_COMPLETE = 0xffff,
934};
935
936typedef struct QEMU_PACKED NvmeFwSlotInfoLog {
937 uint8_t afi;
938 uint8_t reserved1[7];
939 uint8_t frs1[8];
940 uint8_t frs2[8];
941 uint8_t frs3[8];
942 uint8_t frs4[8];
943 uint8_t frs5[8];
944 uint8_t frs6[8];
945 uint8_t frs7[8];
946 uint8_t reserved2[448];
947} NvmeFwSlotInfoLog;
948
949typedef struct QEMU_PACKED NvmeErrorLog {
950 uint64_t error_count;
951 uint16_t sqid;
952 uint16_t cid;
953 uint16_t status_field;
954 uint16_t param_error_location;
955 uint64_t lba;
956 uint32_t nsid;
957 uint8_t vs;
958 uint8_t resv[35];
959} NvmeErrorLog;
960
961typedef struct QEMU_PACKED NvmeSmartLog {
962 uint8_t critical_warning;
963 uint16_t temperature;
964 uint8_t available_spare;
965 uint8_t available_spare_threshold;
966 uint8_t percentage_used;
967 uint8_t reserved1[26];
968 uint64_t data_units_read[2];
969 uint64_t data_units_written[2];
970 uint64_t host_read_commands[2];
971 uint64_t host_write_commands[2];
972 uint64_t controller_busy_time[2];
973 uint64_t power_cycles[2];
974 uint64_t power_on_hours[2];
975 uint64_t unsafe_shutdowns[2];
976 uint64_t media_errors[2];
977 uint64_t number_of_error_log_entries[2];
978 uint8_t reserved2[320];
979} NvmeSmartLog;
980
981#define NVME_SMART_WARN_MAX 6
982enum NvmeSmartWarn {
983 NVME_SMART_SPARE = 1 << 0,
984 NVME_SMART_TEMPERATURE = 1 << 1,
985 NVME_SMART_RELIABILITY = 1 << 2,
986 NVME_SMART_MEDIA_READ_ONLY = 1 << 3,
987 NVME_SMART_FAILED_VOLATILE_MEDIA = 1 << 4,
988 NVME_SMART_PMR_UNRELIABLE = 1 << 5,
989};
990
991typedef struct NvmeEffectsLog {
992 uint32_t acs[256];
993 uint32_t iocs[256];
994 uint8_t resv[2048];
995} NvmeEffectsLog;
996
997enum {
998 NVME_CMD_EFF_CSUPP = 1 << 0,
999 NVME_CMD_EFF_LBCC = 1 << 1,
1000 NVME_CMD_EFF_NCC = 1 << 2,
1001 NVME_CMD_EFF_NIC = 1 << 3,
1002 NVME_CMD_EFF_CCC = 1 << 4,
1003 NVME_CMD_EFF_CSE_MASK = 3 << 16,
1004 NVME_CMD_EFF_UUID_SEL = 1 << 19,
1005};
1006
1007enum NvmeLogIdentifier {
1008 NVME_LOG_ERROR_INFO = 0x01,
1009 NVME_LOG_SMART_INFO = 0x02,
1010 NVME_LOG_FW_SLOT_INFO = 0x03,
1011 NVME_LOG_CHANGED_NSLIST = 0x04,
1012 NVME_LOG_CMD_EFFECTS = 0x05,
1013};
1014
1015typedef struct QEMU_PACKED NvmePSD {
1016 uint16_t mp;
1017 uint16_t reserved;
1018 uint32_t enlat;
1019 uint32_t exlat;
1020 uint8_t rrt;
1021 uint8_t rrl;
1022 uint8_t rwt;
1023 uint8_t rwl;
1024 uint8_t resv[16];
1025} NvmePSD;
1026
1027#define NVME_CONTROLLER_LIST_SIZE 2048
1028#define NVME_IDENTIFY_DATA_SIZE 4096
1029
1030enum NvmeIdCns {
1031 NVME_ID_CNS_NS = 0x00,
1032 NVME_ID_CNS_CTRL = 0x01,
1033 NVME_ID_CNS_NS_ACTIVE_LIST = 0x02,
1034 NVME_ID_CNS_NS_DESCR_LIST = 0x03,
1035 NVME_ID_CNS_CS_NS = 0x05,
1036 NVME_ID_CNS_CS_CTRL = 0x06,
1037 NVME_ID_CNS_CS_NS_ACTIVE_LIST = 0x07,
1038 NVME_ID_CNS_NS_PRESENT_LIST = 0x10,
1039 NVME_ID_CNS_NS_PRESENT = 0x11,
1040 NVME_ID_CNS_NS_ATTACHED_CTRL_LIST = 0x12,
1041 NVME_ID_CNS_CTRL_LIST = 0x13,
1042 NVME_ID_CNS_PRIMARY_CTRL_CAP = 0x14,
1043 NVME_ID_CNS_SECONDARY_CTRL_LIST = 0x15,
1044 NVME_ID_CNS_CS_NS_PRESENT_LIST = 0x1a,
1045 NVME_ID_CNS_CS_NS_PRESENT = 0x1b,
1046 NVME_ID_CNS_IO_COMMAND_SET = 0x1c,
1047};
1048
1049typedef struct QEMU_PACKED NvmeIdCtrl {
1050 uint16_t vid;
1051 uint16_t ssvid;
1052 uint8_t sn[20];
1053 uint8_t mn[40];
1054 uint8_t fr[8];
1055 uint8_t rab;
1056 uint8_t ieee[3];
1057 uint8_t cmic;
1058 uint8_t mdts;
1059 uint16_t cntlid;
1060 uint32_t ver;
1061 uint32_t rtd3r;
1062 uint32_t rtd3e;
1063 uint32_t oaes;
1064 uint32_t ctratt;
1065 uint8_t rsvd100[11];
1066 uint8_t cntrltype;
1067 uint8_t fguid[16];
1068 uint8_t rsvd128[128];
1069 uint16_t oacs;
1070 uint8_t acl;
1071 uint8_t aerl;
1072 uint8_t frmw;
1073 uint8_t lpa;
1074 uint8_t elpe;
1075 uint8_t npss;
1076 uint8_t avscc;
1077 uint8_t apsta;
1078 uint16_t wctemp;
1079 uint16_t cctemp;
1080 uint16_t mtfa;
1081 uint32_t hmpre;
1082 uint32_t hmmin;
1083 uint8_t tnvmcap[16];
1084 uint8_t unvmcap[16];
1085 uint32_t rpmbs;
1086 uint16_t edstt;
1087 uint8_t dsto;
1088 uint8_t fwug;
1089 uint16_t kas;
1090 uint16_t hctma;
1091 uint16_t mntmt;
1092 uint16_t mxtmt;
1093 uint32_t sanicap;
1094 uint8_t rsvd332[180];
1095 uint8_t sqes;
1096 uint8_t cqes;
1097 uint16_t maxcmd;
1098 uint32_t nn;
1099 uint16_t oncs;
1100 uint16_t fuses;
1101 uint8_t fna;
1102 uint8_t vwc;
1103 uint16_t awun;
1104 uint16_t awupf;
1105 uint8_t nvscc;
1106 uint8_t rsvd531;
1107 uint16_t acwu;
1108 uint16_t ocfs;
1109 uint32_t sgls;
1110 uint8_t rsvd540[228];
1111 uint8_t subnqn[256];
1112 uint8_t rsvd1024[1024];
1113 NvmePSD psd[32];
1114 uint8_t vs[1024];
1115} NvmeIdCtrl;
1116
1117typedef struct NvmeIdCtrlZoned {
1118 uint8_t zasl;
1119 uint8_t rsvd1[4095];
1120} NvmeIdCtrlZoned;
1121
1122typedef struct NvmeIdCtrlNvm {
1123 uint8_t vsl;
1124 uint8_t wzsl;
1125 uint8_t wusl;
1126 uint8_t dmrl;
1127 uint32_t dmrsl;
1128 uint64_t dmsl;
1129 uint8_t rsvd16[4080];
1130} NvmeIdCtrlNvm;
1131
1132enum NvmeIdCtrlOaes {
1133 NVME_OAES_NS_ATTR = 1 << 8,
1134};
1135
1136enum NvmeIdCtrlCtratt {
1137 NVME_CTRATT_ELBAS = 1 << 15,
1138};
1139
1140enum NvmeIdCtrlOacs {
1141 NVME_OACS_SECURITY = 1 << 0,
1142 NVME_OACS_FORMAT = 1 << 1,
1143 NVME_OACS_FW = 1 << 2,
1144 NVME_OACS_NS_MGMT = 1 << 3,
1145 NVME_OACS_DBBUF = 1 << 8,
1146};
1147
1148enum NvmeIdCtrlOncs {
1149 NVME_ONCS_COMPARE = 1 << 0,
1150 NVME_ONCS_WRITE_UNCORR = 1 << 1,
1151 NVME_ONCS_DSM = 1 << 2,
1152 NVME_ONCS_WRITE_ZEROES = 1 << 3,
1153 NVME_ONCS_FEATURES = 1 << 4,
1154 NVME_ONCS_RESRVATIONS = 1 << 5,
1155 NVME_ONCS_TIMESTAMP = 1 << 6,
1156 NVME_ONCS_VERIFY = 1 << 7,
1157 NVME_ONCS_COPY = 1 << 8,
1158};
1159
1160enum NvmeIdCtrlOcfs {
1161 NVME_OCFS_COPY_FORMAT_0 = 1 << NVME_COPY_FORMAT_0,
1162 NVME_OCFS_COPY_FORMAT_1 = 1 << NVME_COPY_FORMAT_1,
1163};
1164
1165enum NvmeIdctrlVwc {
1166 NVME_VWC_PRESENT = 1 << 0,
1167 NVME_VWC_NSID_BROADCAST_NO_SUPPORT = 0 << 1,
1168 NVME_VWC_NSID_BROADCAST_RESERVED = 1 << 1,
1169 NVME_VWC_NSID_BROADCAST_CTRL_SPEC = 2 << 1,
1170 NVME_VWC_NSID_BROADCAST_SUPPORT = 3 << 1,
1171};
1172
1173enum NvmeIdCtrlFrmw {
1174 NVME_FRMW_SLOT1_RO = 1 << 0,
1175};
1176
1177enum NvmeIdCtrlLpa {
1178 NVME_LPA_NS_SMART = 1 << 0,
1179 NVME_LPA_CSE = 1 << 1,
1180 NVME_LPA_EXTENDED = 1 << 2,
1181};
1182
1183enum NvmeIdCtrlCmic {
1184 NVME_CMIC_MULTI_CTRL = 1 << 1,
1185};
1186
1187enum NvmeNsAttachmentOperation {
1188 NVME_NS_ATTACHMENT_ATTACH = 0x0,
1189 NVME_NS_ATTACHMENT_DETACH = 0x1,
1190};
1191
1192#define NVME_CTRL_SQES_MIN(sqes) ((sqes) & 0xf)
1193#define NVME_CTRL_SQES_MAX(sqes) (((sqes) >> 4) & 0xf)
1194#define NVME_CTRL_CQES_MIN(cqes) ((cqes) & 0xf)
1195#define NVME_CTRL_CQES_MAX(cqes) (((cqes) >> 4) & 0xf)
1196
1197#define NVME_CTRL_SGLS_SUPPORT_MASK (0x3 << 0)
1198#define NVME_CTRL_SGLS_SUPPORT_NO_ALIGN (0x1 << 0)
1199#define NVME_CTRL_SGLS_SUPPORT_DWORD_ALIGN (0x1 << 1)
1200#define NVME_CTRL_SGLS_KEYED (0x1 << 2)
1201#define NVME_CTRL_SGLS_BITBUCKET (0x1 << 16)
1202#define NVME_CTRL_SGLS_MPTR_CONTIGUOUS (0x1 << 17)
1203#define NVME_CTRL_SGLS_EXCESS_LENGTH (0x1 << 18)
1204#define NVME_CTRL_SGLS_MPTR_SGL (0x1 << 19)
1205#define NVME_CTRL_SGLS_ADDR_OFFSET (0x1 << 20)
1206
1207#define NVME_ARB_AB(arb) (arb & 0x7)
1208#define NVME_ARB_AB_NOLIMIT 0x7
1209#define NVME_ARB_LPW(arb) ((arb >> 8) & 0xff)
1210#define NVME_ARB_MPW(arb) ((arb >> 16) & 0xff)
1211#define NVME_ARB_HPW(arb) ((arb >> 24) & 0xff)
1212
1213#define NVME_INTC_THR(intc) (intc & 0xff)
1214#define NVME_INTC_TIME(intc) ((intc >> 8) & 0xff)
1215
1216#define NVME_INTVC_NOCOALESCING (0x1 << 16)
1217
1218#define NVME_TEMP_THSEL(temp) ((temp >> 20) & 0x3)
1219#define NVME_TEMP_THSEL_OVER 0x0
1220#define NVME_TEMP_THSEL_UNDER 0x1
1221
1222#define NVME_TEMP_TMPSEL(temp) ((temp >> 16) & 0xf)
1223#define NVME_TEMP_TMPSEL_COMPOSITE 0x0
1224
1225#define NVME_TEMP_TMPTH(temp) (temp & 0xffff)
1226
1227#define NVME_AEC_SMART(aec) (aec & 0xff)
1228#define NVME_AEC_NS_ATTR(aec) ((aec >> 8) & 0x1)
1229#define NVME_AEC_FW_ACTIVATION(aec) ((aec >> 9) & 0x1)
1230
1231#define NVME_ERR_REC_TLER(err_rec) (err_rec & 0xffff)
1232#define NVME_ERR_REC_DULBE(err_rec) (err_rec & 0x10000)
1233
1234enum NvmeFeatureIds {
1235 NVME_ARBITRATION = 0x1,
1236 NVME_POWER_MANAGEMENT = 0x2,
1237 NVME_LBA_RANGE_TYPE = 0x3,
1238 NVME_TEMPERATURE_THRESHOLD = 0x4,
1239 NVME_ERROR_RECOVERY = 0x5,
1240 NVME_VOLATILE_WRITE_CACHE = 0x6,
1241 NVME_NUMBER_OF_QUEUES = 0x7,
1242 NVME_INTERRUPT_COALESCING = 0x8,
1243 NVME_INTERRUPT_VECTOR_CONF = 0x9,
1244 NVME_WRITE_ATOMICITY = 0xa,
1245 NVME_ASYNCHRONOUS_EVENT_CONF = 0xb,
1246 NVME_TIMESTAMP = 0xe,
1247 NVME_HOST_BEHAVIOR_SUPPORT = 0x16,
1248 NVME_COMMAND_SET_PROFILE = 0x19,
1249 NVME_SOFTWARE_PROGRESS_MARKER = 0x80,
1250 NVME_FID_MAX = 0x100,
1251};
1252
1253typedef enum NvmeFeatureCap {
1254 NVME_FEAT_CAP_SAVE = 1 << 0,
1255 NVME_FEAT_CAP_NS = 1 << 1,
1256 NVME_FEAT_CAP_CHANGE = 1 << 2,
1257} NvmeFeatureCap;
1258
1259typedef enum NvmeGetFeatureSelect {
1260 NVME_GETFEAT_SELECT_CURRENT = 0x0,
1261 NVME_GETFEAT_SELECT_DEFAULT = 0x1,
1262 NVME_GETFEAT_SELECT_SAVED = 0x2,
1263 NVME_GETFEAT_SELECT_CAP = 0x3,
1264} NvmeGetFeatureSelect;
1265
1266#define NVME_GETSETFEAT_FID_MASK 0xff
1267#define NVME_GETSETFEAT_FID(dw10) (dw10 & NVME_GETSETFEAT_FID_MASK)
1268
1269#define NVME_GETFEAT_SELECT_SHIFT 8
1270#define NVME_GETFEAT_SELECT_MASK 0x7
1271#define NVME_GETFEAT_SELECT(dw10) \
1272 ((dw10 >> NVME_GETFEAT_SELECT_SHIFT) & NVME_GETFEAT_SELECT_MASK)
1273
1274#define NVME_SETFEAT_SAVE_SHIFT 31
1275#define NVME_SETFEAT_SAVE_MASK 0x1
1276#define NVME_SETFEAT_SAVE(dw10) \
1277 ((dw10 >> NVME_SETFEAT_SAVE_SHIFT) & NVME_SETFEAT_SAVE_MASK)
1278
1279typedef struct QEMU_PACKED NvmeRangeType {
1280 uint8_t type;
1281 uint8_t attributes;
1282 uint8_t rsvd2[14];
1283 uint64_t slba;
1284 uint64_t nlb;
1285 uint8_t guid[16];
1286 uint8_t rsvd48[16];
1287} NvmeRangeType;
1288
1289typedef struct NvmeHostBehaviorSupport {
1290 uint8_t acre;
1291 uint8_t etdas;
1292 uint8_t lbafee;
1293 uint8_t rsvd3[509];
1294} NvmeHostBehaviorSupport;
1295
1296typedef struct QEMU_PACKED NvmeLBAF {
1297 uint16_t ms;
1298 uint8_t ds;
1299 uint8_t rp;
1300} NvmeLBAF;
1301
1302typedef struct QEMU_PACKED NvmeLBAFE {
1303 uint64_t zsze;
1304 uint8_t zdes;
1305 uint8_t rsvd9[7];
1306} NvmeLBAFE;
1307
1308#define NVME_NSID_BROADCAST 0xffffffff
1309#define NVME_MAX_NLBAF 64
1310
1311typedef struct QEMU_PACKED NvmeIdNs {
1312 uint64_t nsze;
1313 uint64_t ncap;
1314 uint64_t nuse;
1315 uint8_t nsfeat;
1316 uint8_t nlbaf;
1317 uint8_t flbas;
1318 uint8_t mc;
1319 uint8_t dpc;
1320 uint8_t dps;
1321 uint8_t nmic;
1322 uint8_t rescap;
1323 uint8_t fpi;
1324 uint8_t dlfeat;
1325 uint16_t nawun;
1326 uint16_t nawupf;
1327 uint16_t nacwu;
1328 uint16_t nabsn;
1329 uint16_t nabo;
1330 uint16_t nabspf;
1331 uint16_t noiob;
1332 uint8_t nvmcap[16];
1333 uint16_t npwg;
1334 uint16_t npwa;
1335 uint16_t npdg;
1336 uint16_t npda;
1337 uint16_t nows;
1338 uint16_t mssrl;
1339 uint32_t mcl;
1340 uint8_t msrc;
1341 uint8_t rsvd81[23];
1342 uint8_t nguid[16];
1343 uint64_t eui64;
1344 NvmeLBAF lbaf[NVME_MAX_NLBAF];
1345 uint8_t vs[3712];
1346} NvmeIdNs;
1347
1348#define NVME_ID_NS_NVM_ELBAF_PIF(elbaf) (((elbaf) >> 7) & 0x3)
1349
1350typedef struct QEMU_PACKED NvmeIdNsNvm {
1351 uint64_t lbstm;
1352 uint8_t pic;
1353 uint8_t rsvd9[3];
1354 uint32_t elbaf[NVME_MAX_NLBAF];
1355 uint8_t rsvd268[3828];
1356} NvmeIdNsNvm;
1357
1358typedef struct QEMU_PACKED NvmeIdNsDescr {
1359 uint8_t nidt;
1360 uint8_t nidl;
1361 uint8_t rsvd2[2];
1362} NvmeIdNsDescr;
1363
1364enum NvmeNsIdentifierLength {
1365 NVME_NIDL_EUI64 = 8,
1366 NVME_NIDL_NGUID = 16,
1367 NVME_NIDL_UUID = 16,
1368 NVME_NIDL_CSI = 1,
1369};
1370
1371enum NvmeNsIdentifierType {
1372 NVME_NIDT_EUI64 = 0x01,
1373 NVME_NIDT_NGUID = 0x02,
1374 NVME_NIDT_UUID = 0x03,
1375 NVME_NIDT_CSI = 0x04,
1376};
1377
1378enum NvmeIdNsNmic {
1379 NVME_NMIC_NS_SHARED = 1 << 0,
1380};
1381
1382enum NvmeCsi {
1383 NVME_CSI_NVM = 0x00,
1384 NVME_CSI_ZONED = 0x02,
1385};
1386
1387#define NVME_SET_CSI(vec, csi) (vec |= (uint8_t)(1 << (csi)))
1388
1389typedef struct QEMU_PACKED NvmeIdNsZoned {
1390 uint16_t zoc;
1391 uint16_t ozcs;
1392 uint32_t mar;
1393 uint32_t mor;
1394 uint32_t rrl;
1395 uint32_t frl;
1396 uint8_t rsvd12[24];
1397 uint32_t numzrwa;
1398 uint16_t zrwafg;
1399 uint16_t zrwas;
1400 uint8_t zrwacap;
1401 uint8_t rsvd53[2763];
1402 NvmeLBAFE lbafe[16];
1403 uint8_t rsvd3072[768];
1404 uint8_t vs[256];
1405} NvmeIdNsZoned;
1406
1407enum NvmeIdNsZonedOzcs {
1408 NVME_ID_NS_ZONED_OZCS_RAZB = 1 << 0,
1409 NVME_ID_NS_ZONED_OZCS_ZRWASUP = 1 << 1,
1410};
1411
1412enum NvmeIdNsZonedZrwacap {
1413 NVME_ID_NS_ZONED_ZRWACAP_EXPFLUSHSUP = 1 << 0,
1414};
1415
1416
1417#define NVME_ID_NS_DLFEAT_GUARD_CRC(dlfeat) ((dlfeat) & 0x10)
1418#define NVME_ID_NS_DLFEAT_WRITE_ZEROES(dlfeat) ((dlfeat) & 0x08)
1419
1420#define NVME_ID_NS_DLFEAT_READ_BEHAVIOR(dlfeat) ((dlfeat) & 0x7)
1421#define NVME_ID_NS_DLFEAT_READ_BEHAVIOR_UNDEFINED 0
1422#define NVME_ID_NS_DLFEAT_READ_BEHAVIOR_ZEROES 1
1423#define NVME_ID_NS_DLFEAT_READ_BEHAVIOR_ONES 2
1424
1425
1426#define NVME_ID_NS_NSFEAT_THIN(nsfeat) ((nsfeat & 0x1))
1427#define NVME_ID_NS_NSFEAT_DULBE(nsfeat) ((nsfeat >> 2) & 0x1)
1428#define NVME_ID_NS_FLBAS_EXTENDED(flbas) ((flbas >> 4) & 0x1)
1429#define NVME_ID_NS_FLBAS_INDEX(flbas) ((flbas & 0xf))
1430#define NVME_ID_NS_MC_SEPARATE(mc) ((mc >> 1) & 0x1)
1431#define NVME_ID_NS_MC_EXTENDED(mc) ((mc & 0x1))
1432#define NVME_ID_NS_DPC_LAST_EIGHT(dpc) ((dpc >> 4) & 0x1)
1433#define NVME_ID_NS_DPC_FIRST_EIGHT(dpc) ((dpc >> 3) & 0x1)
1434#define NVME_ID_NS_DPC_TYPE_3(dpc) ((dpc >> 2) & 0x1)
1435#define NVME_ID_NS_DPC_TYPE_2(dpc) ((dpc >> 1) & 0x1)
1436#define NVME_ID_NS_DPC_TYPE_1(dpc) ((dpc & 0x1))
1437#define NVME_ID_NS_DPC_TYPE_MASK 0x7
1438
1439enum NvmeIdNsDps {
1440 NVME_ID_NS_DPS_TYPE_NONE = 0,
1441 NVME_ID_NS_DPS_TYPE_1 = 1,
1442 NVME_ID_NS_DPS_TYPE_2 = 2,
1443 NVME_ID_NS_DPS_TYPE_3 = 3,
1444 NVME_ID_NS_DPS_TYPE_MASK = 0x7,
1445 NVME_ID_NS_DPS_FIRST_EIGHT = 8,
1446};
1447
1448enum NvmeIdNsFlbas {
1449 NVME_ID_NS_FLBAS_EXTENDED = 1 << 4,
1450};
1451
1452enum NvmeIdNsMc {
1453 NVME_ID_NS_MC_EXTENDED = 1 << 0,
1454 NVME_ID_NS_MC_SEPARATE = 1 << 1,
1455};
1456
1457#define NVME_ID_NS_DPS_TYPE(dps) (dps & NVME_ID_NS_DPS_TYPE_MASK)
1458
1459enum NvmePIFormat {
1460 NVME_PI_GUARD_16 = 0,
1461 NVME_PI_GUARD_64 = 2,
1462};
1463
1464typedef union NvmeDifTuple {
1465 struct {
1466 uint16_t guard;
1467 uint16_t apptag;
1468 uint32_t reftag;
1469 } g16;
1470
1471 struct {
1472 uint64_t guard;
1473 uint16_t apptag;
1474 uint8_t sr[6];
1475 } g64;
1476} NvmeDifTuple;
1477
1478enum NvmeZoneAttr {
1479 NVME_ZA_FINISHED_BY_CTLR = 1 << 0,
1480 NVME_ZA_FINISH_RECOMMENDED = 1 << 1,
1481 NVME_ZA_RESET_RECOMMENDED = 1 << 2,
1482 NVME_ZA_ZRWA_VALID = 1 << 3,
1483 NVME_ZA_ZD_EXT_VALID = 1 << 7,
1484};
1485
1486typedef struct QEMU_PACKED NvmeZoneReportHeader {
1487 uint64_t nr_zones;
1488 uint8_t rsvd[56];
1489} NvmeZoneReportHeader;
1490
1491enum NvmeZoneReceiveAction {
1492 NVME_ZONE_REPORT = 0,
1493 NVME_ZONE_REPORT_EXTENDED = 1,
1494};
1495
1496enum NvmeZoneReportType {
1497 NVME_ZONE_REPORT_ALL = 0,
1498 NVME_ZONE_REPORT_EMPTY = 1,
1499 NVME_ZONE_REPORT_IMPLICITLY_OPEN = 2,
1500 NVME_ZONE_REPORT_EXPLICITLY_OPEN = 3,
1501 NVME_ZONE_REPORT_CLOSED = 4,
1502 NVME_ZONE_REPORT_FULL = 5,
1503 NVME_ZONE_REPORT_READ_ONLY = 6,
1504 NVME_ZONE_REPORT_OFFLINE = 7,
1505};
1506
1507enum NvmeZoneType {
1508 NVME_ZONE_TYPE_RESERVED = 0x00,
1509 NVME_ZONE_TYPE_SEQ_WRITE = 0x02,
1510};
1511
1512typedef struct QEMU_PACKED NvmeZoneSendCmd {
1513 uint8_t opcode;
1514 uint8_t flags;
1515 uint16_t cid;
1516 uint32_t nsid;
1517 uint32_t rsvd8[4];
1518 NvmeCmdDptr dptr;
1519 uint64_t slba;
1520 uint32_t rsvd48;
1521 uint8_t zsa;
1522 uint8_t zsflags;
1523 uint8_t rsvd54[2];
1524 uint32_t rsvd56[2];
1525} NvmeZoneSendCmd;
1526
1527enum NvmeZoneSendAction {
1528 NVME_ZONE_ACTION_RSD = 0x00,
1529 NVME_ZONE_ACTION_CLOSE = 0x01,
1530 NVME_ZONE_ACTION_FINISH = 0x02,
1531 NVME_ZONE_ACTION_OPEN = 0x03,
1532 NVME_ZONE_ACTION_RESET = 0x04,
1533 NVME_ZONE_ACTION_OFFLINE = 0x05,
1534 NVME_ZONE_ACTION_SET_ZD_EXT = 0x10,
1535 NVME_ZONE_ACTION_ZRWA_FLUSH = 0x11,
1536};
1537
1538enum {
1539 NVME_ZSFLAG_SELECT_ALL = 1 << 0,
1540 NVME_ZSFLAG_ZRWA_ALLOC = 1 << 1,
1541};
1542
1543typedef struct QEMU_PACKED NvmeZoneDescr {
1544 uint8_t zt;
1545 uint8_t zs;
1546 uint8_t za;
1547 uint8_t rsvd3[5];
1548 uint64_t zcap;
1549 uint64_t zslba;
1550 uint64_t wp;
1551 uint8_t rsvd32[32];
1552} NvmeZoneDescr;
1553
1554typedef enum NvmeZoneState {
1555 NVME_ZONE_STATE_RESERVED = 0x00,
1556 NVME_ZONE_STATE_EMPTY = 0x01,
1557 NVME_ZONE_STATE_IMPLICITLY_OPEN = 0x02,
1558 NVME_ZONE_STATE_EXPLICITLY_OPEN = 0x03,
1559 NVME_ZONE_STATE_CLOSED = 0x04,
1560 NVME_ZONE_STATE_READ_ONLY = 0x0d,
1561 NVME_ZONE_STATE_FULL = 0x0e,
1562 NVME_ZONE_STATE_OFFLINE = 0x0f,
1563} NvmeZoneState;
1564
1565typedef struct QEMU_PACKED NvmePriCtrlCap {
1566 uint16_t cntlid;
1567 uint16_t portid;
1568 uint8_t crt;
1569 uint8_t rsvd5[27];
1570 uint32_t vqfrt;
1571 uint32_t vqrfa;
1572 uint16_t vqrfap;
1573 uint16_t vqprt;
1574 uint16_t vqfrsm;
1575 uint16_t vqgran;
1576 uint8_t rsvd48[16];
1577 uint32_t vifrt;
1578 uint32_t virfa;
1579 uint16_t virfap;
1580 uint16_t viprt;
1581 uint16_t vifrsm;
1582 uint16_t vigran;
1583 uint8_t rsvd80[4016];
1584} NvmePriCtrlCap;
1585
1586typedef enum NvmePriCtrlCapCrt {
1587 NVME_CRT_VQ = 1 << 0,
1588 NVME_CRT_VI = 1 << 1,
1589} NvmePriCtrlCapCrt;
1590
1591typedef struct QEMU_PACKED NvmeSecCtrlEntry {
1592 uint16_t scid;
1593 uint16_t pcid;
1594 uint8_t scs;
1595 uint8_t rsvd5[3];
1596 uint16_t vfn;
1597 uint16_t nvq;
1598 uint16_t nvi;
1599 uint8_t rsvd14[18];
1600} NvmeSecCtrlEntry;
1601
1602typedef struct QEMU_PACKED NvmeSecCtrlList {
1603 uint8_t numcntl;
1604 uint8_t rsvd1[31];
1605 NvmeSecCtrlEntry sec[127];
1606} NvmeSecCtrlList;
1607
1608typedef enum NvmeVirtMngmtAction {
1609 NVME_VIRT_MNGMT_ACTION_PRM_ALLOC = 0x01,
1610 NVME_VIRT_MNGMT_ACTION_SEC_OFFLINE = 0x07,
1611 NVME_VIRT_MNGMT_ACTION_SEC_ASSIGN = 0x08,
1612 NVME_VIRT_MNGMT_ACTION_SEC_ONLINE = 0x09,
1613} NvmeVirtMngmtAction;
1614
1615typedef enum NvmeVirtualResourceType {
1616 NVME_VIRT_RES_QUEUE = 0x00,
1617 NVME_VIRT_RES_INTERRUPT = 0x01,
1618} NvmeVirtualResourceType;
1619
1620static inline void _nvme_check_size(void)
1621{
1622 QEMU_BUILD_BUG_ON(sizeof(NvmeBar) != 4096);
1623 QEMU_BUILD_BUG_ON(sizeof(NvmeAerResult) != 4);
1624 QEMU_BUILD_BUG_ON(sizeof(NvmeZonedResult) != 8);
1625 QEMU_BUILD_BUG_ON(sizeof(NvmeCqe) != 16);
1626 QEMU_BUILD_BUG_ON(sizeof(NvmeDsmRange) != 16);
1627 QEMU_BUILD_BUG_ON(sizeof(NvmeCopySourceRangeFormat0) != 32);
1628 QEMU_BUILD_BUG_ON(sizeof(NvmeCopySourceRangeFormat1) != 40);
1629 QEMU_BUILD_BUG_ON(sizeof(NvmeCmd) != 64);
1630 QEMU_BUILD_BUG_ON(sizeof(NvmeDeleteQ) != 64);
1631 QEMU_BUILD_BUG_ON(sizeof(NvmeCreateCq) != 64);
1632 QEMU_BUILD_BUG_ON(sizeof(NvmeCreateSq) != 64);
1633 QEMU_BUILD_BUG_ON(sizeof(NvmeIdentify) != 64);
1634 QEMU_BUILD_BUG_ON(sizeof(NvmeRwCmd) != 64);
1635 QEMU_BUILD_BUG_ON(sizeof(NvmeDsmCmd) != 64);
1636 QEMU_BUILD_BUG_ON(sizeof(NvmeCopyCmd) != 64);
1637 QEMU_BUILD_BUG_ON(sizeof(NvmeRangeType) != 64);
1638 QEMU_BUILD_BUG_ON(sizeof(NvmeHostBehaviorSupport) != 512);
1639 QEMU_BUILD_BUG_ON(sizeof(NvmeErrorLog) != 64);
1640 QEMU_BUILD_BUG_ON(sizeof(NvmeFwSlotInfoLog) != 512);
1641 QEMU_BUILD_BUG_ON(sizeof(NvmeSmartLog) != 512);
1642 QEMU_BUILD_BUG_ON(sizeof(NvmeEffectsLog) != 4096);
1643 QEMU_BUILD_BUG_ON(sizeof(NvmeIdCtrl) != 4096);
1644 QEMU_BUILD_BUG_ON(sizeof(NvmeIdCtrlZoned) != 4096);
1645 QEMU_BUILD_BUG_ON(sizeof(NvmeIdCtrlNvm) != 4096);
1646 QEMU_BUILD_BUG_ON(sizeof(NvmeLBAF) != 4);
1647 QEMU_BUILD_BUG_ON(sizeof(NvmeLBAFE) != 16);
1648 QEMU_BUILD_BUG_ON(sizeof(NvmeIdNs) != 4096);
1649 QEMU_BUILD_BUG_ON(sizeof(NvmeIdNsNvm) != 4096);
1650 QEMU_BUILD_BUG_ON(sizeof(NvmeIdNsZoned) != 4096);
1651 QEMU_BUILD_BUG_ON(sizeof(NvmeSglDescriptor) != 16);
1652 QEMU_BUILD_BUG_ON(sizeof(NvmeIdNsDescr) != 4);
1653 QEMU_BUILD_BUG_ON(sizeof(NvmeZoneDescr) != 64);
1654 QEMU_BUILD_BUG_ON(sizeof(NvmeDifTuple) != 16);
1655 QEMU_BUILD_BUG_ON(sizeof(NvmePriCtrlCap) != 4096);
1656 QEMU_BUILD_BUG_ON(sizeof(NvmeSecCtrlEntry) != 32);
1657 QEMU_BUILD_BUG_ON(sizeof(NvmeSecCtrlList) != 4096);
1658}
1659#endif
1660
