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20#include "qemu/osdep.h"
21#include "qemu.h"
22#include "user-internals.h"
23#include "cpu_loop-common.h"
24#include "signal-common.h"
25
26void cpu_loop(CPUMBState *env)
27{
28 CPUState *cs = env_cpu(env);
29 int trapnr, ret, si_code;
30
31 while (1) {
32 cpu_exec_start(cs);
33 trapnr = cpu_exec(cs);
34 cpu_exec_end(cs);
35 process_queued_cpu_work(cs);
36
37 switch (trapnr) {
38 case EXCP_INTERRUPT:
39
40 break;
41 case EXCP_SYSCALL:
42
43 env->regs[14] += 4;
44 env->pc = env->regs[14];
45 ret = do_syscall(env,
46 env->regs[12],
47 env->regs[5],
48 env->regs[6],
49 env->regs[7],
50 env->regs[8],
51 env->regs[9],
52 env->regs[10],
53 0, 0);
54 if (ret == -QEMU_ERESTARTSYS) {
55
56 env->pc -= 4;
57 } else if (ret != -QEMU_ESIGRETURN) {
58 env->regs[3] = ret;
59 }
60
61
62
63
64
65
66 env->regs[14] = env->pc;
67 break;
68
69 case EXCP_HW_EXCP:
70 env->regs[17] = env->pc + 4;
71 if (env->iflags & D_FLAG) {
72 env->esr |= 1 << 12;
73 env->pc -= 4;
74
75 }
76 env->iflags &= ~(IMM_FLAG | D_FLAG);
77 switch (env->esr & 31) {
78 case ESR_EC_DIVZERO:
79 si_code = TARGET_FPE_INTDIV;
80 break;
81 case ESR_EC_FPU:
82
83
84
85
86
87 si_code = env->fsr;
88 if (si_code & FSR_IO) {
89 si_code = TARGET_FPE_FLTINV;
90 } else if (si_code & FSR_OF) {
91 si_code = TARGET_FPE_FLTOVF;
92 } else if (si_code & FSR_UF) {
93 si_code = TARGET_FPE_FLTUND;
94 } else if (si_code & FSR_DZ) {
95 si_code = TARGET_FPE_FLTDIV;
96 } else if (si_code & FSR_DO) {
97 si_code = TARGET_FPE_FLTRES;
98 }
99 break;
100 default:
101 fprintf(stderr, "Unhandled hw-exception: 0x%x\n",
102 env->esr & ESR_EC_MASK);
103 cpu_dump_state(cs, stderr, 0);
104 exit(EXIT_FAILURE);
105 }
106 force_sig_fault(TARGET_SIGFPE, si_code, env->pc);
107 break;
108
109 case EXCP_DEBUG:
110 force_sig_fault(TARGET_SIGTRAP, TARGET_TRAP_BRKPT, env->pc);
111 break;
112 case EXCP_ATOMIC:
113 cpu_exec_step_atomic(cs);
114 break;
115 default:
116 fprintf(stderr, "Unhandled trap: 0x%x\n", trapnr);
117 cpu_dump_state(cs, stderr, 0);
118 exit(EXIT_FAILURE);
119 }
120 process_pending_signals (env);
121 }
122}
123
124void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs)
125{
126 env->regs[0] = regs->r0;
127 env->regs[1] = regs->r1;
128 env->regs[2] = regs->r2;
129 env->regs[3] = regs->r3;
130 env->regs[4] = regs->r4;
131 env->regs[5] = regs->r5;
132 env->regs[6] = regs->r6;
133 env->regs[7] = regs->r7;
134 env->regs[8] = regs->r8;
135 env->regs[9] = regs->r9;
136 env->regs[10] = regs->r10;
137 env->regs[11] = regs->r11;
138 env->regs[12] = regs->r12;
139 env->regs[13] = regs->r13;
140 env->regs[14] = regs->r14;
141 env->regs[15] = regs->r15;
142 env->regs[16] = regs->r16;
143 env->regs[17] = regs->r17;
144 env->regs[18] = regs->r18;
145 env->regs[19] = regs->r19;
146 env->regs[20] = regs->r20;
147 env->regs[21] = regs->r21;
148 env->regs[22] = regs->r22;
149 env->regs[23] = regs->r23;
150 env->regs[24] = regs->r24;
151 env->regs[25] = regs->r25;
152 env->regs[26] = regs->r26;
153 env->regs[27] = regs->r27;
154 env->regs[28] = regs->r28;
155 env->regs[29] = regs->r29;
156 env->regs[30] = regs->r30;
157 env->regs[31] = regs->r31;
158 env->pc = regs->pc;
159}
160