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8#ifndef MIPS_INTERNAL_H
9#define MIPS_INTERNAL_H
10
11#include "exec/memattrs.h"
12#ifdef CONFIG_TCG
13#include "tcg/tcg-internal.h"
14#endif
15#include "cpu.h"
16
17
18
19
20
21enum mips_mmu_types {
22 MMU_TYPE_NONE = 0,
23 MMU_TYPE_R4000 = 1,
24 MMU_TYPE_BAT = 2,
25 MMU_TYPE_FMT = 3,
26 MMU_TYPE_DVF = 4,
27 MMU_TYPE_R3000,
28 MMU_TYPE_R6000,
29 MMU_TYPE_R8000
30};
31
32struct mips_def_t {
33 const char *name;
34 int32_t CP0_PRid;
35 int32_t CP0_Config0;
36 int32_t CP0_Config1;
37 int32_t CP0_Config2;
38 int32_t CP0_Config3;
39 int32_t CP0_Config4;
40 int32_t CP0_Config4_rw_bitmask;
41 int32_t CP0_Config5;
42 int32_t CP0_Config5_rw_bitmask;
43 int32_t CP0_Config6;
44 int32_t CP0_Config6_rw_bitmask;
45 int32_t CP0_Config7;
46 int32_t CP0_Config7_rw_bitmask;
47 target_ulong CP0_LLAddr_rw_bitmask;
48 int CP0_LLAddr_shift;
49 int32_t SYNCI_Step;
50
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57
58
59 int32_t CCRes;
60 int32_t CP0_Status_rw_bitmask;
61 int32_t CP0_TCStatus_rw_bitmask;
62 int32_t CP0_SRSCtl;
63 int32_t CP1_fcr0;
64 int32_t CP1_fcr31_rw_bitmask;
65 int32_t CP1_fcr31;
66 int32_t MSAIR;
67 int32_t SEGBITS;
68 int32_t PABITS;
69 int32_t CP0_SRSConf0_rw_bitmask;
70 int32_t CP0_SRSConf0;
71 int32_t CP0_SRSConf1_rw_bitmask;
72 int32_t CP0_SRSConf1;
73 int32_t CP0_SRSConf2_rw_bitmask;
74 int32_t CP0_SRSConf2;
75 int32_t CP0_SRSConf3_rw_bitmask;
76 int32_t CP0_SRSConf3;
77 int32_t CP0_SRSConf4_rw_bitmask;
78 int32_t CP0_SRSConf4;
79 int32_t CP0_PageGrain_rw_bitmask;
80 int32_t CP0_PageGrain;
81 target_ulong CP0_EBaseWG_rw_bitmask;
82 uint64_t insn_flags;
83 enum mips_mmu_types mmu_type;
84 int32_t SAARP;
85};
86
87extern const char regnames[32][3];
88extern const char fregnames[32][4];
89
90extern const struct mips_def_t mips_defs[];
91extern const int mips_defs_number;
92
93int mips_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
94int mips_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
95
96#define USEG_LIMIT ((target_ulong)(int32_t)0x7FFFFFFFUL)
97#define KSEG0_BASE ((target_ulong)(int32_t)0x80000000UL)
98#define KSEG1_BASE ((target_ulong)(int32_t)0xA0000000UL)
99#define KSEG2_BASE ((target_ulong)(int32_t)0xC0000000UL)
100#define KSEG3_BASE ((target_ulong)(int32_t)0xE0000000UL)
101
102#define KVM_KSEG0_BASE ((target_ulong)(int32_t)0x40000000UL)
103#define KVM_KSEG2_BASE ((target_ulong)(int32_t)0x60000000UL)
104
105#if !defined(CONFIG_USER_ONLY)
106
107enum {
108 TLBRET_XI = -6,
109 TLBRET_RI = -5,
110 TLBRET_DIRTY = -4,
111 TLBRET_INVALID = -3,
112 TLBRET_NOMATCH = -2,
113 TLBRET_BADADDR = -1,
114 TLBRET_MATCH = 0
115};
116
117int get_physical_address(CPUMIPSState *env, hwaddr *physical,
118 int *prot, target_ulong real_address,
119 MMUAccessType access_type, int mmu_idx);
120hwaddr mips_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
121
122typedef struct r4k_tlb_t r4k_tlb_t;
123struct r4k_tlb_t {
124 target_ulong VPN;
125 uint32_t PageMask;
126 uint16_t ASID;
127 uint32_t MMID;
128 unsigned int G:1;
129 unsigned int C0:3;
130 unsigned int C1:3;
131 unsigned int V0:1;
132 unsigned int V1:1;
133 unsigned int D0:1;
134 unsigned int D1:1;
135 unsigned int XI0:1;
136 unsigned int XI1:1;
137 unsigned int RI0:1;
138 unsigned int RI1:1;
139 unsigned int EHINV:1;
140 uint64_t PFN[2];
141};
142
143struct CPUMIPSTLBContext {
144 uint32_t nb_tlb;
145 uint32_t tlb_in_use;
146 int (*map_address)(CPUMIPSState *env, hwaddr *physical, int *prot,
147 target_ulong address, MMUAccessType access_type);
148 void (*helper_tlbwi)(CPUMIPSState *env);
149 void (*helper_tlbwr)(CPUMIPSState *env);
150 void (*helper_tlbp)(CPUMIPSState *env);
151 void (*helper_tlbr)(CPUMIPSState *env);
152 void (*helper_tlbinv)(CPUMIPSState *env);
153 void (*helper_tlbinvf)(CPUMIPSState *env);
154 union {
155 struct {
156 r4k_tlb_t tlb[MIPS_TLB_MAX];
157 } r4k;
158 } mmu;
159};
160
161void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc);
162void cpu_mips_store_status(CPUMIPSState *env, target_ulong val);
163void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val);
164
165extern const VMStateDescription vmstate_mips_cpu;
166
167#endif
168
169static inline bool cpu_mips_hw_interrupts_enabled(CPUMIPSState *env)
170{
171 return (env->CP0_Status & (1 << CP0St_IE)) &&
172 !(env->CP0_Status & (1 << CP0St_EXL)) &&
173 !(env->CP0_Status & (1 << CP0St_ERL)) &&
174 !(env->hflags & MIPS_HFLAG_DM) &&
175
176
177
178
179
180 !(env->active_tc.CP0_TCStatus & (1 << CP0TCSt_IXMT));
181}
182
183
184static inline bool cpu_mips_hw_interrupts_pending(CPUMIPSState *env)
185{
186 int32_t pending;
187 int32_t status;
188 bool r;
189
190 pending = env->CP0_Cause & CP0Ca_IP_mask;
191 status = env->CP0_Status & CP0Ca_IP_mask;
192
193 if (env->CP0_Config3 & (1 << CP0C3_VEIC)) {
194
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197
198
199 r = pending > status;
200 } else {
201
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205
206 r = (pending & status) != 0;
207 }
208 return r;
209}
210
211void msa_reset(CPUMIPSState *env);
212
213
214uint32_t cpu_mips_get_count(CPUMIPSState *env);
215void cpu_mips_store_count(CPUMIPSState *env, uint32_t value);
216void cpu_mips_store_compare(CPUMIPSState *env, uint32_t value);
217void cpu_mips_start_count(CPUMIPSState *env);
218void cpu_mips_stop_count(CPUMIPSState *env);
219
220static inline void mips_env_set_pc(CPUMIPSState *env, target_ulong value)
221{
222 env->active_tc.PC = value & ~(target_ulong)1;
223 if (value & 1) {
224 env->hflags |= MIPS_HFLAG_M16;
225 } else {
226 env->hflags &= ~(MIPS_HFLAG_M16);
227 }
228}
229
230static inline void restore_pamask(CPUMIPSState *env)
231{
232 if (env->hflags & MIPS_HFLAG_ELPA) {
233 env->PAMask = (1ULL << env->PABITS) - 1;
234 } else {
235 env->PAMask = PAMASK_BASE;
236 }
237}
238
239static inline int mips_vpe_active(CPUMIPSState *env)
240{
241 int active = 1;
242
243
244 if (!(env->mvp->CP0_MVPControl & (1 << CP0MVPCo_EVP))) {
245 active = 0;
246 }
247
248 if (!(env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA))) {
249 active = 0;
250 }
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258
259
260 if (!(env->active_tc.CP0_TCStatus & (1 << CP0TCSt_A))) {
261
262 active = 0;
263 }
264 if (env->active_tc.CP0_TCHalt & 1) {
265
266 active = 0;
267 }
268
269 return active;
270}
271
272static inline int mips_vp_active(CPUMIPSState *env)
273{
274 CPUState *other_cs = first_cpu;
275
276
277 if ((env->CP0_VPControl >> CP0VPCtl_DIS) & 1) {
278 return 1;
279 }
280
281
282 CPU_FOREACH(other_cs) {
283 MIPSCPU *other_cpu = MIPS_CPU(other_cs);
284 if ((&other_cpu->env != env) &&
285 ((other_cpu->env.CP0_VPControl >> CP0VPCtl_DIS) & 1)) {
286 return 0;
287 }
288 }
289 return 1;
290}
291
292static inline void compute_hflags(CPUMIPSState *env)
293{
294 env->hflags &= ~(MIPS_HFLAG_COP1X | MIPS_HFLAG_64 | MIPS_HFLAG_CP0 |
295 MIPS_HFLAG_F64 | MIPS_HFLAG_FPU | MIPS_HFLAG_KSU |
296 MIPS_HFLAG_AWRAP | MIPS_HFLAG_DSP | MIPS_HFLAG_DSP_R2 |
297 MIPS_HFLAG_DSP_R3 | MIPS_HFLAG_SBRI | MIPS_HFLAG_MSA |
298 MIPS_HFLAG_FRE | MIPS_HFLAG_ELPA | MIPS_HFLAG_ERL);
299 if (env->CP0_Status & (1 << CP0St_ERL)) {
300 env->hflags |= MIPS_HFLAG_ERL;
301 }
302 if (!(env->CP0_Status & (1 << CP0St_EXL)) &&
303 !(env->CP0_Status & (1 << CP0St_ERL)) &&
304 !(env->hflags & MIPS_HFLAG_DM)) {
305 env->hflags |= (env->CP0_Status >> CP0St_KSU) &
306 MIPS_HFLAG_KSU;
307 }
308#if defined(TARGET_MIPS64)
309 if ((env->insn_flags & ISA_MIPS3) &&
310 (((env->hflags & MIPS_HFLAG_KSU) != MIPS_HFLAG_UM) ||
311 (env->CP0_Status & (1 << CP0St_PX)) ||
312 (env->CP0_Status & (1 << CP0St_UX)))) {
313 env->hflags |= MIPS_HFLAG_64;
314 }
315
316 if (!(env->insn_flags & ISA_MIPS3)) {
317 env->hflags |= MIPS_HFLAG_AWRAP;
318 } else if (((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_UM) &&
319 !(env->CP0_Status & (1 << CP0St_UX))) {
320 env->hflags |= MIPS_HFLAG_AWRAP;
321 } else if (env->insn_flags & ISA_MIPS_R6) {
322
323 if ((((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_SM) &&
324 !(env->CP0_Status & (1 << CP0St_SX))) ||
325 (((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_KM) &&
326 !(env->CP0_Status & (1 << CP0St_KX)))) {
327 env->hflags |= MIPS_HFLAG_AWRAP;
328 }
329 }
330#endif
331 if (((env->CP0_Status & (1 << CP0St_CU0)) &&
332 !(env->insn_flags & ISA_MIPS_R6)) ||
333 !(env->hflags & MIPS_HFLAG_KSU)) {
334 env->hflags |= MIPS_HFLAG_CP0;
335 }
336 if (env->CP0_Status & (1 << CP0St_CU1)) {
337 env->hflags |= MIPS_HFLAG_FPU;
338 }
339 if (env->CP0_Status & (1 << CP0St_FR)) {
340 env->hflags |= MIPS_HFLAG_F64;
341 }
342 if (((env->hflags & MIPS_HFLAG_KSU) != MIPS_HFLAG_KM) &&
343 (env->CP0_Config5 & (1 << CP0C5_SBRI))) {
344 env->hflags |= MIPS_HFLAG_SBRI;
345 }
346 if (env->insn_flags & ASE_DSP_R3) {
347
348
349
350
351 if (env->CP0_Status & (1 << CP0St_MX)) {
352 env->hflags |= MIPS_HFLAG_DSP | MIPS_HFLAG_DSP_R2 |
353 MIPS_HFLAG_DSP_R3;
354 }
355 } else if (env->insn_flags & ASE_DSP_R2) {
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357
358
359
360 if (env->CP0_Status & (1 << CP0St_MX)) {
361 env->hflags |= MIPS_HFLAG_DSP | MIPS_HFLAG_DSP_R2;
362 }
363
364 } else if (env->insn_flags & ASE_DSP) {
365
366
367
368
369 if (env->CP0_Status & (1 << CP0St_MX)) {
370 env->hflags |= MIPS_HFLAG_DSP;
371 }
372
373 }
374 if (env->insn_flags & ISA_MIPS_R2) {
375 if (env->active_fpu.fcr0 & (1 << FCR0_F64)) {
376 env->hflags |= MIPS_HFLAG_COP1X;
377 }
378 } else if (env->insn_flags & ISA_MIPS_R1) {
379 if (env->hflags & MIPS_HFLAG_64) {
380 env->hflags |= MIPS_HFLAG_COP1X;
381 }
382 } else if (env->insn_flags & ISA_MIPS4) {
383
384
385
386
387
388
389 if (env->CP0_Status & (1U << CP0St_CU3)) {
390 env->hflags |= MIPS_HFLAG_COP1X;
391 }
392 }
393 if (ase_msa_available(env)) {
394 if (env->CP0_Config5 & (1 << CP0C5_MSAEn)) {
395 env->hflags |= MIPS_HFLAG_MSA;
396 }
397 }
398 if (env->active_fpu.fcr0 & (1 << FCR0_FREP)) {
399 if (env->CP0_Config5 & (1 << CP0C5_FRE)) {
400 env->hflags |= MIPS_HFLAG_FRE;
401 }
402 }
403 if (env->CP0_Config3 & (1 << CP0C3_LPA)) {
404 if (env->CP0_PageGrain & (1 << CP0PG_ELPA)) {
405 env->hflags |= MIPS_HFLAG_ELPA;
406 }
407 }
408}
409
410#endif
411