1
2
3#ifndef TARGET_RISCV_CPU_BITS_H
4#define TARGET_RISCV_CPU_BITS_H
5
6#define get_field(reg, mask) (((reg) & \
7 (uint64_t)(mask)) / ((mask) & ~((mask) << 1)))
8#define set_field(reg, mask, val) (((reg) & ~(uint64_t)(mask)) | \
9 (((uint64_t)(val) * ((mask) & ~((mask) << 1))) & \
10 (uint64_t)(mask)))
11
12
13#define FSR_RD_SHIFT 5
14#define FSR_RD (0x7 << FSR_RD_SHIFT)
15
16
17#define FPEXC_NX 0x01
18#define FPEXC_UF 0x02
19#define FPEXC_OF 0x04
20#define FPEXC_DZ 0x08
21#define FPEXC_NV 0x10
22
23
24#define FSR_AEXC_SHIFT 0
25#define FSR_NVA (FPEXC_NV << FSR_AEXC_SHIFT)
26#define FSR_OFA (FPEXC_OF << FSR_AEXC_SHIFT)
27#define FSR_UFA (FPEXC_UF << FSR_AEXC_SHIFT)
28#define FSR_DZA (FPEXC_DZ << FSR_AEXC_SHIFT)
29#define FSR_NXA (FPEXC_NX << FSR_AEXC_SHIFT)
30#define FSR_AEXC (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA)
31
32
33#define FSR_VXRM_SHIFT 9
34#define FSR_VXRM (0x3 << FSR_VXRM_SHIFT)
35
36
37#define FSR_VXSAT_SHIFT 8
38#define FSR_VXSAT (0x1 << FSR_VXSAT_SHIFT)
39
40
41
42
43#define CSR_USTATUS 0x000
44#define CSR_UIE 0x004
45#define CSR_UTVEC 0x005
46
47
48#define CSR_USCRATCH 0x040
49#define CSR_UEPC 0x041
50#define CSR_UCAUSE 0x042
51#define CSR_UTVAL 0x043
52#define CSR_UIP 0x044
53
54
55#define CSR_FFLAGS 0x001
56#define CSR_FRM 0x002
57#define CSR_FCSR 0x003
58
59
60#define CSR_VSTART 0x008
61#define CSR_VXSAT 0x009
62#define CSR_VXRM 0x00a
63#define CSR_VCSR 0x00f
64#define CSR_VL 0xc20
65#define CSR_VTYPE 0xc21
66#define CSR_VLENB 0xc22
67
68
69#define VCSR_VXSAT_SHIFT 0
70#define VCSR_VXSAT (0x1 << VCSR_VXSAT_SHIFT)
71#define VCSR_VXRM_SHIFT 1
72#define VCSR_VXRM (0x3 << VCSR_VXRM_SHIFT)
73
74
75#define CSR_CYCLE 0xc00
76#define CSR_TIME 0xc01
77#define CSR_INSTRET 0xc02
78#define CSR_HPMCOUNTER3 0xc03
79#define CSR_HPMCOUNTER4 0xc04
80#define CSR_HPMCOUNTER5 0xc05
81#define CSR_HPMCOUNTER6 0xc06
82#define CSR_HPMCOUNTER7 0xc07
83#define CSR_HPMCOUNTER8 0xc08
84#define CSR_HPMCOUNTER9 0xc09
85#define CSR_HPMCOUNTER10 0xc0a
86#define CSR_HPMCOUNTER11 0xc0b
87#define CSR_HPMCOUNTER12 0xc0c
88#define CSR_HPMCOUNTER13 0xc0d
89#define CSR_HPMCOUNTER14 0xc0e
90#define CSR_HPMCOUNTER15 0xc0f
91#define CSR_HPMCOUNTER16 0xc10
92#define CSR_HPMCOUNTER17 0xc11
93#define CSR_HPMCOUNTER18 0xc12
94#define CSR_HPMCOUNTER19 0xc13
95#define CSR_HPMCOUNTER20 0xc14
96#define CSR_HPMCOUNTER21 0xc15
97#define CSR_HPMCOUNTER22 0xc16
98#define CSR_HPMCOUNTER23 0xc17
99#define CSR_HPMCOUNTER24 0xc18
100#define CSR_HPMCOUNTER25 0xc19
101#define CSR_HPMCOUNTER26 0xc1a
102#define CSR_HPMCOUNTER27 0xc1b
103#define CSR_HPMCOUNTER28 0xc1c
104#define CSR_HPMCOUNTER29 0xc1d
105#define CSR_HPMCOUNTER30 0xc1e
106#define CSR_HPMCOUNTER31 0xc1f
107#define CSR_CYCLEH 0xc80
108#define CSR_TIMEH 0xc81
109#define CSR_INSTRETH 0xc82
110#define CSR_HPMCOUNTER3H 0xc83
111#define CSR_HPMCOUNTER4H 0xc84
112#define CSR_HPMCOUNTER5H 0xc85
113#define CSR_HPMCOUNTER6H 0xc86
114#define CSR_HPMCOUNTER7H 0xc87
115#define CSR_HPMCOUNTER8H 0xc88
116#define CSR_HPMCOUNTER9H 0xc89
117#define CSR_HPMCOUNTER10H 0xc8a
118#define CSR_HPMCOUNTER11H 0xc8b
119#define CSR_HPMCOUNTER12H 0xc8c
120#define CSR_HPMCOUNTER13H 0xc8d
121#define CSR_HPMCOUNTER14H 0xc8e
122#define CSR_HPMCOUNTER15H 0xc8f
123#define CSR_HPMCOUNTER16H 0xc90
124#define CSR_HPMCOUNTER17H 0xc91
125#define CSR_HPMCOUNTER18H 0xc92
126#define CSR_HPMCOUNTER19H 0xc93
127#define CSR_HPMCOUNTER20H 0xc94
128#define CSR_HPMCOUNTER21H 0xc95
129#define CSR_HPMCOUNTER22H 0xc96
130#define CSR_HPMCOUNTER23H 0xc97
131#define CSR_HPMCOUNTER24H 0xc98
132#define CSR_HPMCOUNTER25H 0xc99
133#define CSR_HPMCOUNTER26H 0xc9a
134#define CSR_HPMCOUNTER27H 0xc9b
135#define CSR_HPMCOUNTER28H 0xc9c
136#define CSR_HPMCOUNTER29H 0xc9d
137#define CSR_HPMCOUNTER30H 0xc9e
138#define CSR_HPMCOUNTER31H 0xc9f
139
140
141#define CSR_MCYCLE 0xb00
142#define CSR_MINSTRET 0xb02
143#define CSR_MCYCLEH 0xb80
144#define CSR_MINSTRETH 0xb82
145
146
147#define CSR_MVENDORID 0xf11
148#define CSR_MARCHID 0xf12
149#define CSR_MIMPID 0xf13
150#define CSR_MHARTID 0xf14
151#define CSR_MCONFIGPTR 0xf15
152
153
154#define CSR_MSTATUS 0x300
155#define CSR_MISA 0x301
156#define CSR_MEDELEG 0x302
157#define CSR_MIDELEG 0x303
158#define CSR_MIE 0x304
159#define CSR_MTVEC 0x305
160#define CSR_MCOUNTEREN 0x306
161
162
163#define CSR_MSTATUSH 0x310
164
165
166#define CSR_MSCRATCH 0x340
167#define CSR_MEPC 0x341
168#define CSR_MCAUSE 0x342
169#define CSR_MTVAL 0x343
170#define CSR_MIP 0x344
171
172
173#define CSR_MISELECT 0x350
174#define CSR_MIREG 0x351
175
176
177#define CSR_MTOPEI 0x35c
178#define CSR_MTOPI 0xfb0
179
180
181#define CSR_MVIEN 0x308
182#define CSR_MVIP 0x309
183
184
185#define CSR_MIDELEGH 0x313
186#define CSR_MIEH 0x314
187#define CSR_MVIENH 0x318
188#define CSR_MVIPH 0x319
189#define CSR_MIPH 0x354
190
191
192#define CSR_SSTATUS 0x100
193#define CSR_SIE 0x104
194#define CSR_STVEC 0x105
195#define CSR_SCOUNTEREN 0x106
196
197
198#define CSR_SENVCFG 0x10A
199
200
201#define CSR_SSCRATCH 0x140
202#define CSR_SEPC 0x141
203#define CSR_SCAUSE 0x142
204#define CSR_STVAL 0x143
205#define CSR_SIP 0x144
206
207
208#define CSR_STIMECMP 0x14D
209#define CSR_STIMECMPH 0x15D
210
211
212#define CSR_SPTBR 0x180
213#define CSR_SATP 0x180
214
215
216#define CSR_SISELECT 0x150
217#define CSR_SIREG 0x151
218
219
220#define CSR_STOPEI 0x15c
221#define CSR_STOPI 0xdb0
222
223
224#define CSR_SIEH 0x114
225#define CSR_SIPH 0x154
226
227
228#define CSR_HSTATUS 0x600
229#define CSR_HEDELEG 0x602
230#define CSR_HIDELEG 0x603
231#define CSR_HIE 0x604
232#define CSR_HCOUNTEREN 0x606
233#define CSR_HGEIE 0x607
234#define CSR_HTVAL 0x643
235#define CSR_HVIP 0x645
236#define CSR_HIP 0x644
237#define CSR_HTINST 0x64A
238#define CSR_HGEIP 0xE12
239#define CSR_HGATP 0x680
240#define CSR_HTIMEDELTA 0x605
241#define CSR_HTIMEDELTAH 0x615
242
243
244#define CSR_HENVCFG 0x60A
245#define CSR_HENVCFGH 0x61A
246
247
248#define CSR_VSSTATUS 0x200
249#define CSR_VSIE 0x204
250#define CSR_VSTVEC 0x205
251#define CSR_VSSCRATCH 0x240
252#define CSR_VSEPC 0x241
253#define CSR_VSCAUSE 0x242
254#define CSR_VSTVAL 0x243
255#define CSR_VSIP 0x244
256#define CSR_VSATP 0x280
257
258
259#define CSR_VSTIMECMP 0x24D
260#define CSR_VSTIMECMPH 0x25D
261
262#define CSR_MTINST 0x34a
263#define CSR_MTVAL2 0x34b
264
265
266#define CSR_HVIEN 0x608
267#define CSR_HVICTL 0x609
268#define CSR_HVIPRIO1 0x646
269#define CSR_HVIPRIO2 0x647
270
271
272#define CSR_VSISELECT 0x250
273#define CSR_VSIREG 0x251
274
275
276#define CSR_VSTOPEI 0x25c
277#define CSR_VSTOPI 0xeb0
278
279
280#define CSR_HIDELEGH 0x613
281#define CSR_HVIENH 0x618
282#define CSR_HVIPH 0x655
283#define CSR_HVIPRIO1H 0x656
284#define CSR_HVIPRIO2H 0x657
285#define CSR_VSIEH 0x214
286#define CSR_VSIPH 0x254
287
288
289#define CSR_MENVCFG 0x30A
290#define CSR_MENVCFGH 0x31A
291
292
293#define CSR_MSECCFG 0x747
294#define CSR_MSECCFGH 0x757
295
296#define CSR_PMPCFG0 0x3a0
297#define CSR_PMPCFG1 0x3a1
298#define CSR_PMPCFG2 0x3a2
299#define CSR_PMPCFG3 0x3a3
300#define CSR_PMPADDR0 0x3b0
301#define CSR_PMPADDR1 0x3b1
302#define CSR_PMPADDR2 0x3b2
303#define CSR_PMPADDR3 0x3b3
304#define CSR_PMPADDR4 0x3b4
305#define CSR_PMPADDR5 0x3b5
306#define CSR_PMPADDR6 0x3b6
307#define CSR_PMPADDR7 0x3b7
308#define CSR_PMPADDR8 0x3b8
309#define CSR_PMPADDR9 0x3b9
310#define CSR_PMPADDR10 0x3ba
311#define CSR_PMPADDR11 0x3bb
312#define CSR_PMPADDR12 0x3bc
313#define CSR_PMPADDR13 0x3bd
314#define CSR_PMPADDR14 0x3be
315#define CSR_PMPADDR15 0x3bf
316
317
318#define CSR_TSELECT 0x7a0
319#define CSR_TDATA1 0x7a1
320#define CSR_TDATA2 0x7a2
321#define CSR_TDATA3 0x7a3
322#define CSR_TINFO 0x7a4
323
324
325#define CSR_DCSR 0x7b0
326#define CSR_DPC 0x7b1
327#define CSR_DSCRATCH 0x7b2
328
329
330#define CSR_MHPMCOUNTER3 0xb03
331#define CSR_MHPMCOUNTER4 0xb04
332#define CSR_MHPMCOUNTER5 0xb05
333#define CSR_MHPMCOUNTER6 0xb06
334#define CSR_MHPMCOUNTER7 0xb07
335#define CSR_MHPMCOUNTER8 0xb08
336#define CSR_MHPMCOUNTER9 0xb09
337#define CSR_MHPMCOUNTER10 0xb0a
338#define CSR_MHPMCOUNTER11 0xb0b
339#define CSR_MHPMCOUNTER12 0xb0c
340#define CSR_MHPMCOUNTER13 0xb0d
341#define CSR_MHPMCOUNTER14 0xb0e
342#define CSR_MHPMCOUNTER15 0xb0f
343#define CSR_MHPMCOUNTER16 0xb10
344#define CSR_MHPMCOUNTER17 0xb11
345#define CSR_MHPMCOUNTER18 0xb12
346#define CSR_MHPMCOUNTER19 0xb13
347#define CSR_MHPMCOUNTER20 0xb14
348#define CSR_MHPMCOUNTER21 0xb15
349#define CSR_MHPMCOUNTER22 0xb16
350#define CSR_MHPMCOUNTER23 0xb17
351#define CSR_MHPMCOUNTER24 0xb18
352#define CSR_MHPMCOUNTER25 0xb19
353#define CSR_MHPMCOUNTER26 0xb1a
354#define CSR_MHPMCOUNTER27 0xb1b
355#define CSR_MHPMCOUNTER28 0xb1c
356#define CSR_MHPMCOUNTER29 0xb1d
357#define CSR_MHPMCOUNTER30 0xb1e
358#define CSR_MHPMCOUNTER31 0xb1f
359
360
361#define CSR_MCOUNTINHIBIT 0x320
362
363#define CSR_MHPMEVENT3 0x323
364#define CSR_MHPMEVENT4 0x324
365#define CSR_MHPMEVENT5 0x325
366#define CSR_MHPMEVENT6 0x326
367#define CSR_MHPMEVENT7 0x327
368#define CSR_MHPMEVENT8 0x328
369#define CSR_MHPMEVENT9 0x329
370#define CSR_MHPMEVENT10 0x32a
371#define CSR_MHPMEVENT11 0x32b
372#define CSR_MHPMEVENT12 0x32c
373#define CSR_MHPMEVENT13 0x32d
374#define CSR_MHPMEVENT14 0x32e
375#define CSR_MHPMEVENT15 0x32f
376#define CSR_MHPMEVENT16 0x330
377#define CSR_MHPMEVENT17 0x331
378#define CSR_MHPMEVENT18 0x332
379#define CSR_MHPMEVENT19 0x333
380#define CSR_MHPMEVENT20 0x334
381#define CSR_MHPMEVENT21 0x335
382#define CSR_MHPMEVENT22 0x336
383#define CSR_MHPMEVENT23 0x337
384#define CSR_MHPMEVENT24 0x338
385#define CSR_MHPMEVENT25 0x339
386#define CSR_MHPMEVENT26 0x33a
387#define CSR_MHPMEVENT27 0x33b
388#define CSR_MHPMEVENT28 0x33c
389#define CSR_MHPMEVENT29 0x33d
390#define CSR_MHPMEVENT30 0x33e
391#define CSR_MHPMEVENT31 0x33f
392
393#define CSR_MHPMEVENT3H 0x723
394#define CSR_MHPMEVENT4H 0x724
395#define CSR_MHPMEVENT5H 0x725
396#define CSR_MHPMEVENT6H 0x726
397#define CSR_MHPMEVENT7H 0x727
398#define CSR_MHPMEVENT8H 0x728
399#define CSR_MHPMEVENT9H 0x729
400#define CSR_MHPMEVENT10H 0x72a
401#define CSR_MHPMEVENT11H 0x72b
402#define CSR_MHPMEVENT12H 0x72c
403#define CSR_MHPMEVENT13H 0x72d
404#define CSR_MHPMEVENT14H 0x72e
405#define CSR_MHPMEVENT15H 0x72f
406#define CSR_MHPMEVENT16H 0x730
407#define CSR_MHPMEVENT17H 0x731
408#define CSR_MHPMEVENT18H 0x732
409#define CSR_MHPMEVENT19H 0x733
410#define CSR_MHPMEVENT20H 0x734
411#define CSR_MHPMEVENT21H 0x735
412#define CSR_MHPMEVENT22H 0x736
413#define CSR_MHPMEVENT23H 0x737
414#define CSR_MHPMEVENT24H 0x738
415#define CSR_MHPMEVENT25H 0x739
416#define CSR_MHPMEVENT26H 0x73a
417#define CSR_MHPMEVENT27H 0x73b
418#define CSR_MHPMEVENT28H 0x73c
419#define CSR_MHPMEVENT29H 0x73d
420#define CSR_MHPMEVENT30H 0x73e
421#define CSR_MHPMEVENT31H 0x73f
422
423#define CSR_MHPMCOUNTER3H 0xb83
424#define CSR_MHPMCOUNTER4H 0xb84
425#define CSR_MHPMCOUNTER5H 0xb85
426#define CSR_MHPMCOUNTER6H 0xb86
427#define CSR_MHPMCOUNTER7H 0xb87
428#define CSR_MHPMCOUNTER8H 0xb88
429#define CSR_MHPMCOUNTER9H 0xb89
430#define CSR_MHPMCOUNTER10H 0xb8a
431#define CSR_MHPMCOUNTER11H 0xb8b
432#define CSR_MHPMCOUNTER12H 0xb8c
433#define CSR_MHPMCOUNTER13H 0xb8d
434#define CSR_MHPMCOUNTER14H 0xb8e
435#define CSR_MHPMCOUNTER15H 0xb8f
436#define CSR_MHPMCOUNTER16H 0xb90
437#define CSR_MHPMCOUNTER17H 0xb91
438#define CSR_MHPMCOUNTER18H 0xb92
439#define CSR_MHPMCOUNTER19H 0xb93
440#define CSR_MHPMCOUNTER20H 0xb94
441#define CSR_MHPMCOUNTER21H 0xb95
442#define CSR_MHPMCOUNTER22H 0xb96
443#define CSR_MHPMCOUNTER23H 0xb97
444#define CSR_MHPMCOUNTER24H 0xb98
445#define CSR_MHPMCOUNTER25H 0xb99
446#define CSR_MHPMCOUNTER26H 0xb9a
447#define CSR_MHPMCOUNTER27H 0xb9b
448#define CSR_MHPMCOUNTER28H 0xb9c
449#define CSR_MHPMCOUNTER29H 0xb9d
450#define CSR_MHPMCOUNTER30H 0xb9e
451#define CSR_MHPMCOUNTER31H 0xb9f
452
453
454
455
456
457#define CSR_UMTE 0x4c0
458#define CSR_UPMMASK 0x4c1
459#define CSR_UPMBASE 0x4c2
460
461
462
463
464
465#define CSR_MMTE 0x3c0
466#define CSR_MPMMASK 0x3c1
467#define CSR_MPMBASE 0x3c2
468
469
470
471
472
473#define CSR_SMTE 0x1c0
474#define CSR_SPMMASK 0x1c1
475#define CSR_SPMBASE 0x1c2
476
477
478
479
480
481#define CSR_VSMTE 0x2c0
482#define CSR_VSPMMASK 0x2c1
483#define CSR_VSPMBASE 0x2c2
484#define CSR_SCOUNTOVF 0xda0
485
486
487#define CSR_SEED 0x015
488
489
490#define MSTATUS_UIE 0x00000001
491#define MSTATUS_SIE 0x00000002
492#define MSTATUS_MIE 0x00000008
493#define MSTATUS_UPIE 0x00000010
494#define MSTATUS_SPIE 0x00000020
495#define MSTATUS_UBE 0x00000040
496#define MSTATUS_MPIE 0x00000080
497#define MSTATUS_SPP 0x00000100
498#define MSTATUS_VS 0x00000600
499#define MSTATUS_MPP 0x00001800
500#define MSTATUS_FS 0x00006000
501#define MSTATUS_XS 0x00018000
502#define MSTATUS_MPRV 0x00020000
503#define MSTATUS_SUM 0x00040000
504#define MSTATUS_MXR 0x00080000
505#define MSTATUS_TVM 0x00100000
506#define MSTATUS_TW 0x00200000
507#define MSTATUS_TSR 0x00400000
508#define MSTATUS_GVA 0x4000000000ULL
509#define MSTATUS_MPV 0x8000000000ULL
510
511#define MSTATUS64_UXL 0x0000000300000000ULL
512#define MSTATUS64_SXL 0x0000000C00000000ULL
513
514#define MSTATUS32_SD 0x80000000
515#define MSTATUS64_SD 0x8000000000000000ULL
516#define MSTATUSH128_SD 0x8000000000000000ULL
517
518#define MISA32_MXL 0xC0000000
519#define MISA64_MXL 0xC000000000000000ULL
520
521typedef enum {
522 MXL_RV32 = 1,
523 MXL_RV64 = 2,
524 MXL_RV128 = 3,
525} RISCVMXL;
526
527
528#define SSTATUS_UIE 0x00000001
529#define SSTATUS_SIE 0x00000002
530#define SSTATUS_UPIE 0x00000010
531#define SSTATUS_SPIE 0x00000020
532#define SSTATUS_SPP 0x00000100
533#define SSTATUS_VS 0x00000600
534#define SSTATUS_FS 0x00006000
535#define SSTATUS_XS 0x00018000
536#define SSTATUS_SUM 0x00040000
537#define SSTATUS_MXR 0x00080000
538
539#define SSTATUS64_UXL 0x0000000300000000ULL
540
541#define SSTATUS32_SD 0x80000000
542#define SSTATUS64_SD 0x8000000000000000ULL
543
544
545#define HSTATUS_VSBE 0x00000020
546#define HSTATUS_GVA 0x00000040
547#define HSTATUS_SPV 0x00000080
548#define HSTATUS_SPVP 0x00000100
549#define HSTATUS_HU 0x00000200
550#define HSTATUS_VGEIN 0x0003F000
551#define HSTATUS_VTVM 0x00100000
552#define HSTATUS_VTW 0x00200000
553#define HSTATUS_VTSR 0x00400000
554#define HSTATUS_VSXL 0x300000000
555
556#define HSTATUS32_WPRI 0xFF8FF87E
557#define HSTATUS64_WPRI 0xFFFFFFFFFF8FF87EULL
558
559#define COUNTEREN_CY (1 << 0)
560#define COUNTEREN_TM (1 << 1)
561#define COUNTEREN_IR (1 << 2)
562#define COUNTEREN_HPM3 (1 << 3)
563
564
565#define VSSTATUS64_UXL 0x0000000300000000ULL
566
567
568#define PRV_U 0
569#define PRV_S 1
570#define PRV_H 2
571#define PRV_M 3
572
573
574#define VIRT_ONOFF 1
575
576
577#define SATP32_MODE 0x80000000
578#define SATP32_ASID 0x7fc00000
579#define SATP32_PPN 0x003fffff
580
581
582#define SATP64_MODE 0xF000000000000000ULL
583#define SATP64_ASID 0x0FFFF00000000000ULL
584#define SATP64_PPN 0x00000FFFFFFFFFFFULL
585
586
587#define VM_1_10_MBARE 0
588#define VM_1_10_SV32 1
589#define VM_1_10_SV39 8
590#define VM_1_10_SV48 9
591#define VM_1_10_SV57 10
592#define VM_1_10_SV64 11
593
594
595#define PTE_V 0x001
596#define PTE_R 0x002
597#define PTE_W 0x004
598#define PTE_X 0x008
599#define PTE_U 0x010
600#define PTE_G 0x020
601#define PTE_A 0x040
602#define PTE_D 0x080
603#define PTE_SOFT 0x300
604#define PTE_PBMT 0x6000000000000000ULL
605#define PTE_N 0x8000000000000000ULL
606#define PTE_ATTR (PTE_N | PTE_PBMT)
607
608
609#define PTE_PPN_SHIFT 10
610
611
612#define PTE_PPN_MASK 0x3FFFFFFFFFFC00ULL
613
614
615#define PGSHIFT 12
616
617
618#define DEFAULT_RSTVEC 0x1000
619
620
621typedef enum RISCVException {
622 RISCV_EXCP_NONE = -1,
623 RISCV_EXCP_INST_ADDR_MIS = 0x0,
624 RISCV_EXCP_INST_ACCESS_FAULT = 0x1,
625 RISCV_EXCP_ILLEGAL_INST = 0x2,
626 RISCV_EXCP_BREAKPOINT = 0x3,
627 RISCV_EXCP_LOAD_ADDR_MIS = 0x4,
628 RISCV_EXCP_LOAD_ACCESS_FAULT = 0x5,
629 RISCV_EXCP_STORE_AMO_ADDR_MIS = 0x6,
630 RISCV_EXCP_STORE_AMO_ACCESS_FAULT = 0x7,
631 RISCV_EXCP_U_ECALL = 0x8,
632 RISCV_EXCP_S_ECALL = 0x9,
633 RISCV_EXCP_VS_ECALL = 0xa,
634 RISCV_EXCP_M_ECALL = 0xb,
635 RISCV_EXCP_INST_PAGE_FAULT = 0xc,
636 RISCV_EXCP_LOAD_PAGE_FAULT = 0xd,
637 RISCV_EXCP_STORE_PAGE_FAULT = 0xf,
638 RISCV_EXCP_SEMIHOST = 0x10,
639 RISCV_EXCP_INST_GUEST_PAGE_FAULT = 0x14,
640 RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT = 0x15,
641 RISCV_EXCP_VIRT_INSTRUCTION_FAULT = 0x16,
642 RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT = 0x17,
643} RISCVException;
644
645#define RISCV_EXCP_INT_FLAG 0x80000000
646#define RISCV_EXCP_INT_MASK 0x7fffffff
647
648
649#define IRQ_U_SOFT 0
650#define IRQ_S_SOFT 1
651#define IRQ_VS_SOFT 2
652#define IRQ_M_SOFT 3
653#define IRQ_U_TIMER 4
654#define IRQ_S_TIMER 5
655#define IRQ_VS_TIMER 6
656#define IRQ_M_TIMER 7
657#define IRQ_U_EXT 8
658#define IRQ_S_EXT 9
659#define IRQ_VS_EXT 10
660#define IRQ_M_EXT 11
661#define IRQ_S_GEXT 12
662#define IRQ_PMU_OVF 13
663#define IRQ_LOCAL_MAX 16
664#define IRQ_LOCAL_GUEST_MAX (TARGET_LONG_BITS - 1)
665
666
667#define MIP_USIP (1 << IRQ_U_SOFT)
668#define MIP_SSIP (1 << IRQ_S_SOFT)
669#define MIP_VSSIP (1 << IRQ_VS_SOFT)
670#define MIP_MSIP (1 << IRQ_M_SOFT)
671#define MIP_UTIP (1 << IRQ_U_TIMER)
672#define MIP_STIP (1 << IRQ_S_TIMER)
673#define MIP_VSTIP (1 << IRQ_VS_TIMER)
674#define MIP_MTIP (1 << IRQ_M_TIMER)
675#define MIP_UEIP (1 << IRQ_U_EXT)
676#define MIP_SEIP (1 << IRQ_S_EXT)
677#define MIP_VSEIP (1 << IRQ_VS_EXT)
678#define MIP_MEIP (1 << IRQ_M_EXT)
679#define MIP_SGEIP (1 << IRQ_S_GEXT)
680#define MIP_LCOFIP (1 << IRQ_PMU_OVF)
681
682
683#define SIP_SSIP MIP_SSIP
684#define SIP_STIP MIP_STIP
685#define SIP_SEIP MIP_SEIP
686#define SIP_LCOFIP MIP_LCOFIP
687
688
689#define MIE_SEIE (1 << IRQ_S_EXT)
690#define MIE_UEIE (1 << IRQ_U_EXT)
691#define MIE_STIE (1 << IRQ_S_TIMER)
692#define MIE_UTIE (1 << IRQ_U_TIMER)
693#define MIE_SSIE (1 << IRQ_S_SOFT)
694#define MIE_USIE (1 << IRQ_U_SOFT)
695
696
697#define PM_ENABLE 0x00000001ULL
698#define PM_CURRENT 0x00000002ULL
699#define PM_INSN 0x00000004ULL
700#define PM_XS_MASK 0x00000003ULL
701
702
703#define PM_EXT_DISABLE 0x00000000ULL
704#define PM_EXT_INITIAL 0x00000001ULL
705#define PM_EXT_CLEAN 0x00000002ULL
706#define PM_EXT_DIRTY 0x00000003ULL
707
708
709#define MENVCFG_FIOM BIT(0)
710#define MENVCFG_CBIE (3UL << 4)
711#define MENVCFG_CBCFE BIT(6)
712#define MENVCFG_CBZE BIT(7)
713#define MENVCFG_PBMTE (1ULL << 62)
714#define MENVCFG_STCE (1ULL << 63)
715
716
717#define MENVCFGH_PBMTE BIT(30)
718#define MENVCFGH_STCE BIT(31)
719
720#define SENVCFG_FIOM MENVCFG_FIOM
721#define SENVCFG_CBIE MENVCFG_CBIE
722#define SENVCFG_CBCFE MENVCFG_CBCFE
723#define SENVCFG_CBZE MENVCFG_CBZE
724
725#define HENVCFG_FIOM MENVCFG_FIOM
726#define HENVCFG_CBIE MENVCFG_CBIE
727#define HENVCFG_CBCFE MENVCFG_CBCFE
728#define HENVCFG_CBZE MENVCFG_CBZE
729#define HENVCFG_PBMTE MENVCFG_PBMTE
730#define HENVCFG_STCE MENVCFG_STCE
731
732
733#define HENVCFGH_PBMTE MENVCFGH_PBMTE
734#define HENVCFGH_STCE MENVCFGH_STCE
735
736
737#define XS_OFFSET 0ULL
738#define U_OFFSET 2ULL
739#define S_OFFSET 5ULL
740#define M_OFFSET 8ULL
741
742#define PM_XS_BITS (PM_XS_MASK << XS_OFFSET)
743#define U_PM_ENABLE (PM_ENABLE << U_OFFSET)
744#define U_PM_CURRENT (PM_CURRENT << U_OFFSET)
745#define U_PM_INSN (PM_INSN << U_OFFSET)
746#define S_PM_ENABLE (PM_ENABLE << S_OFFSET)
747#define S_PM_CURRENT (PM_CURRENT << S_OFFSET)
748#define S_PM_INSN (PM_INSN << S_OFFSET)
749#define M_PM_ENABLE (PM_ENABLE << M_OFFSET)
750#define M_PM_CURRENT (PM_CURRENT << M_OFFSET)
751#define M_PM_INSN (PM_INSN << M_OFFSET)
752
753
754#define MMTE_PM_XS_BITS PM_XS_BITS
755#define MMTE_U_PM_ENABLE U_PM_ENABLE
756#define MMTE_U_PM_CURRENT U_PM_CURRENT
757#define MMTE_U_PM_INSN U_PM_INSN
758#define MMTE_S_PM_ENABLE S_PM_ENABLE
759#define MMTE_S_PM_CURRENT S_PM_CURRENT
760#define MMTE_S_PM_INSN S_PM_INSN
761#define MMTE_M_PM_ENABLE M_PM_ENABLE
762#define MMTE_M_PM_CURRENT M_PM_CURRENT
763#define MMTE_M_PM_INSN M_PM_INSN
764#define MMTE_MASK (MMTE_U_PM_ENABLE | MMTE_U_PM_CURRENT | MMTE_U_PM_INSN | \
765 MMTE_S_PM_ENABLE | MMTE_S_PM_CURRENT | MMTE_S_PM_INSN | \
766 MMTE_M_PM_ENABLE | MMTE_M_PM_CURRENT | MMTE_M_PM_INSN | \
767 MMTE_PM_XS_BITS)
768
769
770#define SMTE_PM_XS_BITS PM_XS_BITS
771#define SMTE_U_PM_ENABLE U_PM_ENABLE
772#define SMTE_U_PM_CURRENT U_PM_CURRENT
773#define SMTE_U_PM_INSN U_PM_INSN
774#define SMTE_S_PM_ENABLE S_PM_ENABLE
775#define SMTE_S_PM_CURRENT S_PM_CURRENT
776#define SMTE_S_PM_INSN S_PM_INSN
777#define SMTE_MASK (SMTE_U_PM_ENABLE | SMTE_U_PM_CURRENT | SMTE_U_PM_INSN | \
778 SMTE_S_PM_ENABLE | SMTE_S_PM_CURRENT | SMTE_S_PM_INSN | \
779 SMTE_PM_XS_BITS)
780
781
782#define UMTE_U_PM_ENABLE U_PM_ENABLE
783#define UMTE_U_PM_CURRENT U_PM_CURRENT
784#define UMTE_U_PM_INSN U_PM_INSN
785#define UMTE_MASK (UMTE_U_PM_ENABLE | MMTE_U_PM_CURRENT | UMTE_U_PM_INSN)
786
787
788#define ISELECT_IPRIO0 0x30
789#define ISELECT_IPRIO15 0x3f
790#define ISELECT_IMSIC_EIDELIVERY 0x70
791#define ISELECT_IMSIC_EITHRESHOLD 0x72
792#define ISELECT_IMSIC_EIP0 0x80
793#define ISELECT_IMSIC_EIP63 0xbf
794#define ISELECT_IMSIC_EIE0 0xc0
795#define ISELECT_IMSIC_EIE63 0xff
796#define ISELECT_IMSIC_FIRST ISELECT_IMSIC_EIDELIVERY
797#define ISELECT_IMSIC_LAST ISELECT_IMSIC_EIE63
798#define ISELECT_MASK 0x1ff
799
800
801#define ISELECT_IMSIC_TOPEI (ISELECT_MASK + 1)
802
803
804#define IMSIC_TOPEI_IID_SHIFT 16
805#define IMSIC_TOPEI_IID_MASK 0x7ff
806#define IMSIC_TOPEI_IPRIO_MASK 0x7ff
807#define IMSIC_EIPx_BITS 32
808#define IMSIC_EIEx_BITS 32
809
810
811#define TOPI_IID_SHIFT 16
812#define TOPI_IID_MASK 0xfff
813#define TOPI_IPRIO_MASK 0xff
814
815
816#define IPRIO_IRQ_BITS 8
817#define IPRIO_MMAXIPRIO 255
818#define IPRIO_DEFAULT_UPPER 4
819#define IPRIO_DEFAULT_MIDDLE (IPRIO_DEFAULT_UPPER + 12)
820#define IPRIO_DEFAULT_M IPRIO_DEFAULT_MIDDLE
821#define IPRIO_DEFAULT_S (IPRIO_DEFAULT_M + 3)
822#define IPRIO_DEFAULT_SGEXT (IPRIO_DEFAULT_S + 3)
823#define IPRIO_DEFAULT_VS (IPRIO_DEFAULT_SGEXT + 1)
824#define IPRIO_DEFAULT_LOWER (IPRIO_DEFAULT_VS + 3)
825
826
827#define HVICTL_VTI 0x40000000
828#define HVICTL_IID 0x0fff0000
829#define HVICTL_IPRIOM 0x00000100
830#define HVICTL_IPRIO 0x000000ff
831#define HVICTL_VALID_MASK \
832 (HVICTL_VTI | HVICTL_IID | HVICTL_IPRIOM | HVICTL_IPRIO)
833
834
835#define SEED_OPST (0b11 << 30)
836#define SEED_OPST_BIST (0b00 << 30)
837#define SEED_OPST_WAIT (0b01 << 30)
838#define SEED_OPST_ES16 (0b10 << 30)
839#define SEED_OPST_DEAD (0b11 << 30)
840
841#define MIE_LCOFIE (1 << IRQ_PMU_OVF)
842
843#define MHPMEVENT_BIT_OF BIT_ULL(63)
844#define MHPMEVENTH_BIT_OF BIT(31)
845#define MHPMEVENT_BIT_MINH BIT_ULL(62)
846#define MHPMEVENTH_BIT_MINH BIT(30)
847#define MHPMEVENT_BIT_SINH BIT_ULL(61)
848#define MHPMEVENTH_BIT_SINH BIT(29)
849#define MHPMEVENT_BIT_UINH BIT_ULL(60)
850#define MHPMEVENTH_BIT_UINH BIT(28)
851#define MHPMEVENT_BIT_VSINH BIT_ULL(59)
852#define MHPMEVENTH_BIT_VSINH BIT(27)
853#define MHPMEVENT_BIT_VUINH BIT_ULL(58)
854#define MHPMEVENTH_BIT_VUINH BIT(26)
855
856#define MHPMEVENT_SSCOF_MASK _ULL(0xFFFF000000000000)
857#define MHPMEVENT_IDX_MASK 0xFFFFF
858#define MHPMEVENT_SSCOF_RESVD 16
859
860#endif
861