LXR qemu/include/hw/arm/allwinner-h3.h

   1/*
   2 * Allwinner H3 System on Chip emulation
   3 *
   4 * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
   5 *
   6 * This program is free software: you can redistribute it and/or modify
   7 * it under the terms of the GNU General Public License as published by
   8 * the Free Software Foundation, either version 2 of the License, or
   9 * (at your option) any later version.
  10 *
  11 * This program is distributed in the hope that it will be useful,
  12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 * GNU General Public License for more details.
  15 *
  16 * You should have received a copy of the GNU General Public License
  17 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  18 */
  19
  20/*
  21 * The Allwinner H3 is a System on Chip containing four ARM Cortex-A7
  22 * processor cores. Features and specifications include DDR2/DDR3 memory,
  23 * SD/MMC storage cards, 10/100/1000Mbit Ethernet, USB 2.0, HDMI and
  24 * various I/O modules.
  25 *
  26 * This implementation is based on the following datasheet:
  27 *
  28 *   https://linux-sunxi.org/File:Allwinner_H3_Datasheet_V1.2.pdf
  29 *
  30 * The latest datasheet and more info can be found on the Linux Sunxi wiki:
  31 *
  32 *   https://linux-sunxi.org/H3
  33 */
  34
  35#ifndef HW_ARM_ALLWINNER_H3_H
  36#define HW_ARM_ALLWINNER_H3_H
  37
  38#include "qom/object.h"
  39#include "hw/arm/boot.h"
  40#include "hw/timer/allwinner-a10-pit.h"
  41#include "hw/intc/arm_gic.h"
  42#include "hw/misc/allwinner-h3-ccu.h"
  43#include "hw/misc/allwinner-cpucfg.h"
  44#include "hw/misc/allwinner-h3-dramc.h"
  45#include "hw/misc/allwinner-h3-sysctrl.h"
  46#include "hw/misc/allwinner-sid.h"
  47#include "hw/sd/allwinner-sdhost.h"
  48#include "hw/net/allwinner-sun8i-emac.h"
  49#include "hw/rtc/allwinner-rtc.h"
  50#include "hw/i2c/allwinner-i2c.h"
  51#include "target/arm/cpu.h"
  52#include "sysemu/block-backend.h"
  53
  54/**
  55 * Allwinner H3 device list
  56 *
  57 * This enumeration is can be used refer to a particular device in the
  58 * Allwinner H3 SoC. For example, the physical memory base address for
  59 * each device can be found in the AwH3State object in the memmap member
  60 * using the device enum value as index.
  61 *
  62 * @see AwH3State
  63 */
  64enum {
  65    AW_H3_DEV_SRAM_A1,
  66    AW_H3_DEV_SRAM_A2,
  67    AW_H3_DEV_SRAM_C,
  68    AW_H3_DEV_SYSCTRL,
  69    AW_H3_DEV_MMC0,
  70    AW_H3_DEV_SID,
  71    AW_H3_DEV_EHCI0,
  72    AW_H3_DEV_OHCI0,
  73    AW_H3_DEV_EHCI1,
  74    AW_H3_DEV_OHCI1,
  75    AW_H3_DEV_EHCI2,
  76    AW_H3_DEV_OHCI2,
  77    AW_H3_DEV_EHCI3,
  78    AW_H3_DEV_OHCI3,
  79    AW_H3_DEV_CCU,
  80    AW_H3_DEV_PIT,
  81    AW_H3_DEV_UART0,
  82    AW_H3_DEV_UART1,
  83    AW_H3_DEV_UART2,
  84    AW_H3_DEV_UART3,
  85    AW_H3_DEV_EMAC,
  86    AW_H3_DEV_TWI0,
  87    AW_H3_DEV_TWI1,
  88    AW_H3_DEV_TWI2,
  89    AW_H3_DEV_DRAMCOM,
  90    AW_H3_DEV_DRAMCTL,
  91    AW_H3_DEV_DRAMPHY,
  92    AW_H3_DEV_GIC_DIST,
  93    AW_H3_DEV_GIC_CPU,
  94    AW_H3_DEV_GIC_HYP,
  95    AW_H3_DEV_GIC_VCPU,
  96    AW_H3_DEV_RTC,
  97    AW_H3_DEV_CPUCFG,
  98    AW_H3_DEV_R_TWI,
  99    AW_H3_DEV_SDRAM
 100};
 101
 102/** Total number of CPU cores in the H3 SoC */
 103#define AW_H3_NUM_CPUS      (4)
 104
 105/**
 106 * Allwinner H3 object model
 107 * @{
 108 */
 109
 110/** Object type for the Allwinner H3 SoC */
 111#define TYPE_AW_H3 "allwinner-h3"
 112
 113/** Convert input object to Allwinner H3 state object */
 114OBJECT_DECLARE_SIMPLE_TYPE(AwH3State, AW_H3)
 115
 116/** @} */
 117
 118/**
 119 * Allwinner H3 object
 120 *
 121 * This struct contains the state of all the devices
 122 * which are currently emulated by the H3 SoC code.
 123 */
 124struct AwH3State {
 125    /*< private >*/
 126    DeviceState parent_obj;
 127    /*< public >*/
 128
 129    ARMCPU cpus[AW_H3_NUM_CPUS];
 130    const hwaddr *memmap;
 131    AwA10PITState timer;
 132    AwH3ClockCtlState ccu;
 133    AwCpuCfgState cpucfg;
 134    AwH3DramCtlState dramc;
 135    AwH3SysCtrlState sysctrl;
 136    AwSidState sid;
 137    AwSdHostState mmc0;
 138    AWI2CState i2c0;
 139    AWI2CState i2c1;
 140    AWI2CState i2c2;
 141    AWI2CState r_twi;
 142    AwSun8iEmacState emac;
 143    AwRtcState rtc;
 144    GICState gic;
 145    MemoryRegion sram_a1;
 146    MemoryRegion sram_a2;
 147    MemoryRegion sram_c;
 148};
 149
 150/**
 151 * Emulate Boot ROM firmware setup functionality.
 152 *
 153 * A real Allwinner H3 SoC contains a Boot ROM
 154 * which is the first code that runs right after
 155 * the SoC is powered on. The Boot ROM is responsible
 156 * for loading user code (e.g. a bootloader) from any
 157 * of the supported external devices and writing the
 158 * downloaded code to internal SRAM. After loading the SoC
 159 * begins executing the code written to SRAM.
 160 *
 161 * This function emulates the Boot ROM by copying 32 KiB
 162 * of data from the given block device and writes it to
 163 * the start of the first internal SRAM memory.
 164 *
 165 * @s: Allwinner H3 state object pointer
 166 * @blk: Block backend device object pointer
 167 */
 168void allwinner_h3_bootrom_setup(AwH3State *s, BlockBackend *blk);
 169
 170#endif /* HW_ARM_ALLWINNER_H3_H */
 171