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8#include "qemu/osdep.h"
9#include "qemu/log.h"
10#include "qemu/qemu-print.h"
11#include "qapi/error.h"
12#include "qemu/module.h"
13#include "sysemu/qtest.h"
14#include "exec/exec-all.h"
15#include "cpu.h"
16#include "internals.h"
17#include "fpu/softfloat-helpers.h"
18#include "cpu-csr.h"
19#include "sysemu/reset.h"
20#include "tcg/tcg.h"
21
22const char * const regnames[32] = {
23 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
24 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
25 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
26 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
27};
28
29const char * const fregnames[32] = {
30 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
31 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
32 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
33 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
34};
35
36static const char * const excp_names[] = {
37 [EXCCODE_INT] = "Interrupt",
38 [EXCCODE_PIL] = "Page invalid exception for load",
39 [EXCCODE_PIS] = "Page invalid exception for store",
40 [EXCCODE_PIF] = "Page invalid exception for fetch",
41 [EXCCODE_PME] = "Page modified exception",
42 [EXCCODE_PNR] = "Page Not Readable exception",
43 [EXCCODE_PNX] = "Page Not Executable exception",
44 [EXCCODE_PPI] = "Page Privilege error",
45 [EXCCODE_ADEF] = "Address error for instruction fetch",
46 [EXCCODE_ADEM] = "Address error for Memory access",
47 [EXCCODE_SYS] = "Syscall",
48 [EXCCODE_BRK] = "Break",
49 [EXCCODE_INE] = "Instruction Non-Existent",
50 [EXCCODE_IPE] = "Instruction privilege error",
51 [EXCCODE_FPD] = "Floating Point Disabled",
52 [EXCCODE_FPE] = "Floating Point Exception",
53 [EXCCODE_DBP] = "Debug breakpoint",
54 [EXCCODE_BCE] = "Bound Check Exception",
55};
56
57const char *loongarch_exception_name(int32_t exception)
58{
59 assert(excp_names[exception]);
60 return excp_names[exception];
61}
62
63void G_NORETURN do_raise_exception(CPULoongArchState *env,
64 uint32_t exception,
65 uintptr_t pc)
66{
67 CPUState *cs = env_cpu(env);
68
69 qemu_log_mask(CPU_LOG_INT, "%s: %d (%s)\n",
70 __func__,
71 exception,
72 loongarch_exception_name(exception));
73 cs->exception_index = exception;
74
75 cpu_loop_exit_restore(cs, pc);
76}
77
78static void loongarch_cpu_set_pc(CPUState *cs, vaddr value)
79{
80 LoongArchCPU *cpu = LOONGARCH_CPU(cs);
81 CPULoongArchState *env = &cpu->env;
82
83 env->pc = value;
84}
85
86static vaddr loongarch_cpu_get_pc(CPUState *cs)
87{
88 LoongArchCPU *cpu = LOONGARCH_CPU(cs);
89 CPULoongArchState *env = &cpu->env;
90
91 return env->pc;
92}
93
94#ifndef CONFIG_USER_ONLY
95#include "hw/loongarch/virt.h"
96
97void loongarch_cpu_set_irq(void *opaque, int irq, int level)
98{
99 LoongArchCPU *cpu = opaque;
100 CPULoongArchState *env = &cpu->env;
101 CPUState *cs = CPU(cpu);
102
103 if (irq < 0 || irq >= N_IRQS) {
104 return;
105 }
106
107 env->CSR_ESTAT = deposit64(env->CSR_ESTAT, irq, 1, level != 0);
108
109 if (FIELD_EX64(env->CSR_ESTAT, CSR_ESTAT, IS)) {
110 cpu_interrupt(cs, CPU_INTERRUPT_HARD);
111 } else {
112 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
113 }
114}
115
116static inline bool cpu_loongarch_hw_interrupts_enabled(CPULoongArchState *env)
117{
118 bool ret = 0;
119
120 ret = (FIELD_EX64(env->CSR_CRMD, CSR_CRMD, IE) &&
121 !(FIELD_EX64(env->CSR_DBG, CSR_DBG, DST)));
122
123 return ret;
124}
125
126
127static inline bool cpu_loongarch_hw_interrupts_pending(CPULoongArchState *env)
128{
129 uint32_t pending;
130 uint32_t status;
131
132 pending = FIELD_EX64(env->CSR_ESTAT, CSR_ESTAT, IS);
133 status = FIELD_EX64(env->CSR_ECFG, CSR_ECFG, LIE);
134
135 return (pending & status) != 0;
136}
137
138static void loongarch_cpu_do_interrupt(CPUState *cs)
139{
140 LoongArchCPU *cpu = LOONGARCH_CPU(cs);
141 CPULoongArchState *env = &cpu->env;
142 bool update_badinstr = 1;
143 int cause = -1;
144 const char *name;
145 bool tlbfill = FIELD_EX64(env->CSR_TLBRERA, CSR_TLBRERA, ISTLBR);
146 uint32_t vec_size = FIELD_EX64(env->CSR_ECFG, CSR_ECFG, VS);
147
148 if (cs->exception_index != EXCCODE_INT) {
149 if (cs->exception_index < 0 ||
150 cs->exception_index >= ARRAY_SIZE(excp_names)) {
151 name = "unknown";
152 } else {
153 name = excp_names[cs->exception_index];
154 }
155
156 qemu_log_mask(CPU_LOG_INT,
157 "%s enter: pc " TARGET_FMT_lx " ERA " TARGET_FMT_lx
158 " TLBRERA " TARGET_FMT_lx " %s exception\n", __func__,
159 env->pc, env->CSR_ERA, env->CSR_TLBRERA, name);
160 }
161
162 switch (cs->exception_index) {
163 case EXCCODE_DBP:
164 env->CSR_DBG = FIELD_DP64(env->CSR_DBG, CSR_DBG, DCL, 1);
165 env->CSR_DBG = FIELD_DP64(env->CSR_DBG, CSR_DBG, ECODE, 0xC);
166 goto set_DERA;
167 set_DERA:
168 env->CSR_DERA = env->pc;
169 env->CSR_DBG = FIELD_DP64(env->CSR_DBG, CSR_DBG, DST, 1);
170 env->pc = env->CSR_EENTRY + 0x480;
171 break;
172 case EXCCODE_INT:
173 if (FIELD_EX64(env->CSR_DBG, CSR_DBG, DST)) {
174 env->CSR_DBG = FIELD_DP64(env->CSR_DBG, CSR_DBG, DEI, 1);
175 goto set_DERA;
176 }
177 QEMU_FALLTHROUGH;
178 case EXCCODE_PIF:
179 case EXCCODE_ADEF:
180 cause = cs->exception_index;
181 update_badinstr = 0;
182 break;
183 case EXCCODE_SYS:
184 case EXCCODE_BRK:
185 case EXCCODE_INE:
186 case EXCCODE_IPE:
187 case EXCCODE_FPD:
188 case EXCCODE_FPE:
189 case EXCCODE_BCE:
190 env->CSR_BADV = env->pc;
191 QEMU_FALLTHROUGH;
192 case EXCCODE_ADEM:
193 case EXCCODE_PIL:
194 case EXCCODE_PIS:
195 case EXCCODE_PME:
196 case EXCCODE_PNR:
197 case EXCCODE_PNX:
198 case EXCCODE_PPI:
199 cause = cs->exception_index;
200 break;
201 default:
202 qemu_log("Error: exception(%d) has not been supported\n",
203 cs->exception_index);
204 abort();
205 }
206
207 if (update_badinstr) {
208 env->CSR_BADI = cpu_ldl_code(env, env->pc);
209 }
210
211
212 if (tlbfill) {
213 env->CSR_TLBRPRMD = FIELD_DP64(env->CSR_TLBRPRMD, CSR_TLBRPRMD, PPLV,
214 FIELD_EX64(env->CSR_CRMD,
215 CSR_CRMD, PLV));
216 env->CSR_TLBRPRMD = FIELD_DP64(env->CSR_TLBRPRMD, CSR_TLBRPRMD, PIE,
217 FIELD_EX64(env->CSR_CRMD, CSR_CRMD, IE));
218
219 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, DA, 1);
220 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, PG, 0);
221 env->CSR_TLBRERA = FIELD_DP64(env->CSR_TLBRERA, CSR_TLBRERA,
222 PC, (env->pc >> 2));
223 } else {
224 env->CSR_ESTAT = FIELD_DP64(env->CSR_ESTAT, CSR_ESTAT, ECODE,
225 EXCODE_MCODE(cause));
226 env->CSR_ESTAT = FIELD_DP64(env->CSR_ESTAT, CSR_ESTAT, ESUBCODE,
227 EXCODE_SUBCODE(cause));
228 env->CSR_PRMD = FIELD_DP64(env->CSR_PRMD, CSR_PRMD, PPLV,
229 FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PLV));
230 env->CSR_PRMD = FIELD_DP64(env->CSR_PRMD, CSR_PRMD, PIE,
231 FIELD_EX64(env->CSR_CRMD, CSR_CRMD, IE));
232 env->CSR_ERA = env->pc;
233 }
234
235 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, PLV, 0);
236 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, IE, 0);
237
238 if (vec_size) {
239 vec_size = (1 << vec_size) * 4;
240 }
241
242 if (cs->exception_index == EXCCODE_INT) {
243
244 uint32_t vector = 0;
245 uint32_t pending = FIELD_EX64(env->CSR_ESTAT, CSR_ESTAT, IS);
246 pending &= FIELD_EX64(env->CSR_ECFG, CSR_ECFG, LIE);
247
248
249 vector = 31 - clz32(pending);
250 env->pc = env->CSR_EENTRY + (EXCCODE_EXTERNAL_INT + vector) * vec_size;
251 qemu_log_mask(CPU_LOG_INT,
252 "%s: PC " TARGET_FMT_lx " ERA " TARGET_FMT_lx
253 " cause %d\n" " A " TARGET_FMT_lx " D "
254 TARGET_FMT_lx " vector = %d ExC " TARGET_FMT_lx "ExS"
255 TARGET_FMT_lx "\n",
256 __func__, env->pc, env->CSR_ERA,
257 cause, env->CSR_BADV, env->CSR_DERA, vector,
258 env->CSR_ECFG, env->CSR_ESTAT);
259 } else {
260 if (tlbfill) {
261 env->pc = env->CSR_TLBRENTRY;
262 } else {
263 env->pc = env->CSR_EENTRY;
264 env->pc += EXCODE_MCODE(cause) * vec_size;
265 }
266 qemu_log_mask(CPU_LOG_INT,
267 "%s: PC " TARGET_FMT_lx " ERA " TARGET_FMT_lx
268 " cause %d%s\n, ESTAT " TARGET_FMT_lx
269 " EXCFG " TARGET_FMT_lx " BADVA " TARGET_FMT_lx
270 "BADI " TARGET_FMT_lx " SYS_NUM " TARGET_FMT_lu
271 " cpu %d asid " TARGET_FMT_lx "\n", __func__, env->pc,
272 tlbfill ? env->CSR_TLBRERA : env->CSR_ERA,
273 cause, tlbfill ? "(refill)" : "", env->CSR_ESTAT,
274 env->CSR_ECFG,
275 tlbfill ? env->CSR_TLBRBADV : env->CSR_BADV,
276 env->CSR_BADI, env->gpr[11], cs->cpu_index,
277 env->CSR_ASID);
278 }
279 cs->exception_index = -1;
280}
281
282static void loongarch_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
283 vaddr addr, unsigned size,
284 MMUAccessType access_type,
285 int mmu_idx, MemTxAttrs attrs,
286 MemTxResult response,
287 uintptr_t retaddr)
288{
289 LoongArchCPU *cpu = LOONGARCH_CPU(cs);
290 CPULoongArchState *env = &cpu->env;
291
292 if (access_type == MMU_INST_FETCH) {
293 do_raise_exception(env, EXCCODE_ADEF, retaddr);
294 } else {
295 do_raise_exception(env, EXCCODE_ADEM, retaddr);
296 }
297}
298
299static bool loongarch_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
300{
301 if (interrupt_request & CPU_INTERRUPT_HARD) {
302 LoongArchCPU *cpu = LOONGARCH_CPU(cs);
303 CPULoongArchState *env = &cpu->env;
304
305 if (cpu_loongarch_hw_interrupts_enabled(env) &&
306 cpu_loongarch_hw_interrupts_pending(env)) {
307
308 cs->exception_index = EXCCODE_INT;
309 loongarch_cpu_do_interrupt(cs);
310 return true;
311 }
312 }
313 return false;
314}
315#endif
316
317#ifdef CONFIG_TCG
318static void loongarch_cpu_synchronize_from_tb(CPUState *cs,
319 const TranslationBlock *tb)
320{
321 LoongArchCPU *cpu = LOONGARCH_CPU(cs);
322 CPULoongArchState *env = &cpu->env;
323
324 tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL));
325 env->pc = tb->pc;
326}
327
328static void loongarch_restore_state_to_opc(CPUState *cs,
329 const TranslationBlock *tb,
330 const uint64_t *data)
331{
332 LoongArchCPU *cpu = LOONGARCH_CPU(cs);
333 CPULoongArchState *env = &cpu->env;
334
335 env->pc = data[0];
336}
337#endif
338
339static bool loongarch_cpu_has_work(CPUState *cs)
340{
341#ifdef CONFIG_USER_ONLY
342 return true;
343#else
344 LoongArchCPU *cpu = LOONGARCH_CPU(cs);
345 CPULoongArchState *env = &cpu->env;
346 bool has_work = false;
347
348 if ((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
349 cpu_loongarch_hw_interrupts_pending(env)) {
350 has_work = true;
351 }
352
353 return has_work;
354#endif
355}
356
357static void loongarch_la464_initfn(Object *obj)
358{
359 LoongArchCPU *cpu = LOONGARCH_CPU(obj);
360 CPULoongArchState *env = &cpu->env;
361 int i;
362
363 for (i = 0; i < 21; i++) {
364 env->cpucfg[i] = 0x0;
365 }
366
367 cpu->dtb_compatible = "loongarch,Loongson-3A5000";
368 env->cpucfg[0] = 0x14c010;
369
370 uint32_t data = 0;
371 data = FIELD_DP32(data, CPUCFG1, ARCH, 2);
372 data = FIELD_DP32(data, CPUCFG1, PGMMU, 1);
373 data = FIELD_DP32(data, CPUCFG1, IOCSR, 1);
374 data = FIELD_DP32(data, CPUCFG1, PALEN, 0x2f);
375 data = FIELD_DP32(data, CPUCFG1, VALEN, 0x2f);
376 data = FIELD_DP32(data, CPUCFG1, UAL, 1);
377 data = FIELD_DP32(data, CPUCFG1, RI, 1);
378 data = FIELD_DP32(data, CPUCFG1, EP, 1);
379 data = FIELD_DP32(data, CPUCFG1, RPLV, 1);
380 data = FIELD_DP32(data, CPUCFG1, HP, 1);
381 data = FIELD_DP32(data, CPUCFG1, IOCSR_BRD, 1);
382 env->cpucfg[1] = data;
383
384 data = 0;
385 data = FIELD_DP32(data, CPUCFG2, FP, 1);
386 data = FIELD_DP32(data, CPUCFG2, FP_SP, 1);
387 data = FIELD_DP32(data, CPUCFG2, FP_DP, 1);
388 data = FIELD_DP32(data, CPUCFG2, FP_VER, 1);
389 data = FIELD_DP32(data, CPUCFG2, LLFTP, 1);
390 data = FIELD_DP32(data, CPUCFG2, LLFTP_VER, 1);
391 data = FIELD_DP32(data, CPUCFG2, LAM, 1);
392 env->cpucfg[2] = data;
393
394 env->cpucfg[4] = 100 * 1000 * 1000;
395
396 data = 0;
397 data = FIELD_DP32(data, CPUCFG5, CC_MUL, 1);
398 data = FIELD_DP32(data, CPUCFG5, CC_DIV, 1);
399 env->cpucfg[5] = data;
400
401 data = 0;
402 data = FIELD_DP32(data, CPUCFG16, L1_IUPRE, 1);
403 data = FIELD_DP32(data, CPUCFG16, L1_DPRE, 1);
404 data = FIELD_DP32(data, CPUCFG16, L2_IUPRE, 1);
405 data = FIELD_DP32(data, CPUCFG16, L2_IUUNIFY, 1);
406 data = FIELD_DP32(data, CPUCFG16, L2_IUPRIV, 1);
407 data = FIELD_DP32(data, CPUCFG16, L3_IUPRE, 1);
408 data = FIELD_DP32(data, CPUCFG16, L3_IUUNIFY, 1);
409 data = FIELD_DP32(data, CPUCFG16, L3_IUINCL, 1);
410 env->cpucfg[16] = data;
411
412 data = 0;
413 data = FIELD_DP32(data, CPUCFG17, L1IU_WAYS, 3);
414 data = FIELD_DP32(data, CPUCFG17, L1IU_SETS, 8);
415 data = FIELD_DP32(data, CPUCFG17, L1IU_SIZE, 6);
416 env->cpucfg[17] = data;
417
418 data = 0;
419 data = FIELD_DP32(data, CPUCFG18, L1D_WAYS, 3);
420 data = FIELD_DP32(data, CPUCFG18, L1D_SETS, 8);
421 data = FIELD_DP32(data, CPUCFG18, L1D_SIZE, 6);
422 env->cpucfg[18] = data;
423
424 data = 0;
425 data = FIELD_DP32(data, CPUCFG19, L2IU_WAYS, 15);
426 data = FIELD_DP32(data, CPUCFG19, L2IU_SETS, 8);
427 data = FIELD_DP32(data, CPUCFG19, L2IU_SIZE, 6);
428 env->cpucfg[19] = data;
429
430 data = 0;
431 data = FIELD_DP32(data, CPUCFG20, L3IU_WAYS, 15);
432 data = FIELD_DP32(data, CPUCFG20, L3IU_SETS, 14);
433 data = FIELD_DP32(data, CPUCFG20, L3IU_SIZE, 6);
434 env->cpucfg[20] = data;
435
436 env->CSR_ASID = FIELD_DP64(0, CSR_ASID, ASIDBITS, 0xa);
437}
438
439static void loongarch_cpu_list_entry(gpointer data, gpointer user_data)
440{
441 const char *typename = object_class_get_name(OBJECT_CLASS(data));
442
443 qemu_printf("%s\n", typename);
444}
445
446void loongarch_cpu_list(void)
447{
448 GSList *list;
449 list = object_class_get_list_sorted(TYPE_LOONGARCH_CPU, false);
450 g_slist_foreach(list, loongarch_cpu_list_entry, NULL);
451 g_slist_free(list);
452}
453
454static void loongarch_cpu_reset_hold(Object *obj)
455{
456 CPUState *cs = CPU(obj);
457 LoongArchCPU *cpu = LOONGARCH_CPU(cs);
458 LoongArchCPUClass *lacc = LOONGARCH_CPU_GET_CLASS(cpu);
459 CPULoongArchState *env = &cpu->env;
460
461 if (lacc->parent_phases.hold) {
462 lacc->parent_phases.hold(obj);
463 }
464
465 env->fcsr0_mask = FCSR0_M1 | FCSR0_M2 | FCSR0_M3;
466 env->fcsr0 = 0x0;
467
468 int n;
469
470 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, PLV, 0);
471 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, IE, 0);
472 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, DA, 1);
473 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, PG, 0);
474 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, DATF, 1);
475 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, DATM, 1);
476
477 env->CSR_EUEN = FIELD_DP64(env->CSR_EUEN, CSR_EUEN, FPE, 0);
478 env->CSR_EUEN = FIELD_DP64(env->CSR_EUEN, CSR_EUEN, SXE, 0);
479 env->CSR_EUEN = FIELD_DP64(env->CSR_EUEN, CSR_EUEN, ASXE, 0);
480 env->CSR_EUEN = FIELD_DP64(env->CSR_EUEN, CSR_EUEN, BTE, 0);
481
482 env->CSR_MISC = 0;
483
484 env->CSR_ECFG = FIELD_DP64(env->CSR_ECFG, CSR_ECFG, VS, 0);
485 env->CSR_ECFG = FIELD_DP64(env->CSR_ECFG, CSR_ECFG, LIE, 0);
486
487 env->CSR_ESTAT = env->CSR_ESTAT & (~MAKE_64BIT_MASK(0, 2));
488 env->CSR_RVACFG = FIELD_DP64(env->CSR_RVACFG, CSR_RVACFG, RBITS, 0);
489 env->CSR_TCFG = FIELD_DP64(env->CSR_TCFG, CSR_TCFG, EN, 0);
490 env->CSR_LLBCTL = FIELD_DP64(env->CSR_LLBCTL, CSR_LLBCTL, KLO, 0);
491 env->CSR_TLBRERA = FIELD_DP64(env->CSR_TLBRERA, CSR_TLBRERA, ISTLBR, 0);
492 env->CSR_MERRCTL = FIELD_DP64(env->CSR_MERRCTL, CSR_MERRCTL, ISMERR, 0);
493
494 env->CSR_PRCFG3 = FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, TLB_TYPE, 2);
495 env->CSR_PRCFG3 = FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, MTLB_ENTRY, 63);
496 env->CSR_PRCFG3 = FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, STLB_WAYS, 7);
497 env->CSR_PRCFG3 = FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, STLB_SETS, 8);
498
499 for (n = 0; n < 4; n++) {
500 env->CSR_DMW[n] = FIELD_DP64(env->CSR_DMW[n], CSR_DMW, PLV0, 0);
501 env->CSR_DMW[n] = FIELD_DP64(env->CSR_DMW[n], CSR_DMW, PLV1, 0);
502 env->CSR_DMW[n] = FIELD_DP64(env->CSR_DMW[n], CSR_DMW, PLV2, 0);
503 env->CSR_DMW[n] = FIELD_DP64(env->CSR_DMW[n], CSR_DMW, PLV3, 0);
504 }
505
506#ifndef CONFIG_USER_ONLY
507 env->pc = 0x1c000000;
508 memset(env->tlb, 0, sizeof(env->tlb));
509#endif
510
511 restore_fp_status(env);
512 cs->exception_index = -1;
513}
514
515static void loongarch_cpu_disas_set_info(CPUState *s, disassemble_info *info)
516{
517 info->print_insn = print_insn_loongarch;
518}
519
520static void loongarch_cpu_realizefn(DeviceState *dev, Error **errp)
521{
522 CPUState *cs = CPU(dev);
523 LoongArchCPUClass *lacc = LOONGARCH_CPU_GET_CLASS(dev);
524 Error *local_err = NULL;
525
526 cpu_exec_realizefn(cs, &local_err);
527 if (local_err != NULL) {
528 error_propagate(errp, local_err);
529 return;
530 }
531
532 loongarch_cpu_register_gdb_regs_for_features(cs);
533
534 cpu_reset(cs);
535 qemu_init_vcpu(cs);
536
537 lacc->parent_realize(dev, errp);
538}
539
540#ifndef CONFIG_USER_ONLY
541static void loongarch_qemu_write(void *opaque, hwaddr addr,
542 uint64_t val, unsigned size)
543{
544}
545
546static uint64_t loongarch_qemu_read(void *opaque, hwaddr addr, unsigned size)
547{
548 switch (addr) {
549 case VERSION_REG:
550 return 0x11ULL;
551 case FEATURE_REG:
552 return 1ULL << IOCSRF_MSI | 1ULL << IOCSRF_EXTIOI |
553 1ULL << IOCSRF_CSRIPI;
554 case VENDOR_REG:
555 return 0x6e6f73676e6f6f4cULL;
556 case CPUNAME_REG:
557 return 0x303030354133ULL;
558 case MISC_FUNC_REG:
559 return 1ULL << IOCSRM_EXTIOI_EN;
560 }
561 return 0ULL;
562}
563
564static const MemoryRegionOps loongarch_qemu_ops = {
565 .read = loongarch_qemu_read,
566 .write = loongarch_qemu_write,
567 .endianness = DEVICE_LITTLE_ENDIAN,
568 .valid = {
569 .min_access_size = 4,
570 .max_access_size = 8,
571 },
572 .impl = {
573 .min_access_size = 8,
574 .max_access_size = 8,
575 },
576};
577#endif
578
579static void loongarch_cpu_init(Object *obj)
580{
581 LoongArchCPU *cpu = LOONGARCH_CPU(obj);
582
583 cpu_set_cpustate_pointers(cpu);
584
585#ifndef CONFIG_USER_ONLY
586 CPULoongArchState *env = &cpu->env;
587 qdev_init_gpio_in(DEVICE(cpu), loongarch_cpu_set_irq, N_IRQS);
588 timer_init_ns(&cpu->timer, QEMU_CLOCK_VIRTUAL,
589 &loongarch_constant_timer_cb, cpu);
590 memory_region_init_io(&env->system_iocsr, OBJECT(cpu), NULL,
591 env, "iocsr", UINT64_MAX);
592 address_space_init(&env->address_space_iocsr, &env->system_iocsr, "IOCSR");
593 memory_region_init_io(&env->iocsr_mem, OBJECT(cpu), &loongarch_qemu_ops,
594 NULL, "iocsr_misc", 0x428);
595 memory_region_add_subregion(&env->system_iocsr, 0, &env->iocsr_mem);
596#endif
597}
598
599static ObjectClass *loongarch_cpu_class_by_name(const char *cpu_model)
600{
601 ObjectClass *oc;
602
603 oc = object_class_by_name(cpu_model);
604 if (!oc) {
605 g_autofree char *typename
606 = g_strdup_printf(LOONGARCH_CPU_TYPE_NAME("%s"), cpu_model);
607 oc = object_class_by_name(typename);
608 if (!oc) {
609 return NULL;
610 }
611 }
612
613 if (object_class_dynamic_cast(oc, TYPE_LOONGARCH_CPU)
614 && !object_class_is_abstract(oc)) {
615 return oc;
616 }
617 return NULL;
618}
619
620void loongarch_cpu_dump_state(CPUState *cs, FILE *f, int flags)
621{
622 LoongArchCPU *cpu = LOONGARCH_CPU(cs);
623 CPULoongArchState *env = &cpu->env;
624 int i;
625
626 qemu_fprintf(f, " PC=%016" PRIx64 " ", env->pc);
627 qemu_fprintf(f, " FCSR0 0x%08x fp_status 0x%02x\n", env->fcsr0,
628 get_float_exception_flags(&env->fp_status));
629
630
631 for (i = 0; i < 32; i++) {
632 if ((i & 3) == 0) {
633 qemu_fprintf(f, " GPR%02d:", i);
634 }
635 qemu_fprintf(f, " %s %016" PRIx64, regnames[i], env->gpr[i]);
636 if ((i & 3) == 3) {
637 qemu_fprintf(f, "\n");
638 }
639 }
640
641 qemu_fprintf(f, "CRMD=%016" PRIx64 "\n", env->CSR_CRMD);
642 qemu_fprintf(f, "PRMD=%016" PRIx64 "\n", env->CSR_PRMD);
643 qemu_fprintf(f, "EUEN=%016" PRIx64 "\n", env->CSR_EUEN);
644 qemu_fprintf(f, "ESTAT=%016" PRIx64 "\n", env->CSR_ESTAT);
645 qemu_fprintf(f, "ERA=%016" PRIx64 "\n", env->CSR_ERA);
646 qemu_fprintf(f, "BADV=%016" PRIx64 "\n", env->CSR_BADV);
647 qemu_fprintf(f, "BADI=%016" PRIx64 "\n", env->CSR_BADI);
648 qemu_fprintf(f, "EENTRY=%016" PRIx64 "\n", env->CSR_EENTRY);
649 qemu_fprintf(f, "PRCFG1=%016" PRIx64 ", PRCFG2=%016" PRIx64 ","
650 " PRCFG3=%016" PRIx64 "\n",
651 env->CSR_PRCFG1, env->CSR_PRCFG3, env->CSR_PRCFG3);
652 qemu_fprintf(f, "TLBRENTRY=%016" PRIx64 "\n", env->CSR_TLBRENTRY);
653 qemu_fprintf(f, "TLBRBADV=%016" PRIx64 "\n", env->CSR_TLBRBADV);
654 qemu_fprintf(f, "TLBRERA=%016" PRIx64 "\n", env->CSR_TLBRERA);
655
656
657 if (flags & CPU_DUMP_FPU) {
658 for (i = 0; i < 32; i++) {
659 qemu_fprintf(f, " %s %016" PRIx64, fregnames[i], env->fpr[i]);
660 if ((i & 3) == 3) {
661 qemu_fprintf(f, "\n");
662 }
663 }
664 }
665}
666
667#ifdef CONFIG_TCG
668#include "hw/core/tcg-cpu-ops.h"
669
670static struct TCGCPUOps loongarch_tcg_ops = {
671 .initialize = loongarch_translate_init,
672 .synchronize_from_tb = loongarch_cpu_synchronize_from_tb,
673 .restore_state_to_opc = loongarch_restore_state_to_opc,
674
675#ifndef CONFIG_USER_ONLY
676 .tlb_fill = loongarch_cpu_tlb_fill,
677 .cpu_exec_interrupt = loongarch_cpu_exec_interrupt,
678 .do_interrupt = loongarch_cpu_do_interrupt,
679 .do_transaction_failed = loongarch_cpu_do_transaction_failed,
680#endif
681};
682#endif
683
684#ifndef CONFIG_USER_ONLY
685#include "hw/core/sysemu-cpu-ops.h"
686
687static const struct SysemuCPUOps loongarch_sysemu_ops = {
688 .get_phys_page_debug = loongarch_cpu_get_phys_page_debug,
689};
690#endif
691
692static gchar *loongarch_gdb_arch_name(CPUState *cs)
693{
694 return g_strdup("loongarch64");
695}
696
697static void loongarch_cpu_class_init(ObjectClass *c, void *data)
698{
699 LoongArchCPUClass *lacc = LOONGARCH_CPU_CLASS(c);
700 CPUClass *cc = CPU_CLASS(c);
701 DeviceClass *dc = DEVICE_CLASS(c);
702 ResettableClass *rc = RESETTABLE_CLASS(c);
703
704 device_class_set_parent_realize(dc, loongarch_cpu_realizefn,
705 &lacc->parent_realize);
706 resettable_class_set_parent_phases(rc, NULL, loongarch_cpu_reset_hold, NULL,
707 &lacc->parent_phases);
708
709 cc->class_by_name = loongarch_cpu_class_by_name;
710 cc->has_work = loongarch_cpu_has_work;
711 cc->dump_state = loongarch_cpu_dump_state;
712 cc->set_pc = loongarch_cpu_set_pc;
713 cc->get_pc = loongarch_cpu_get_pc;
714#ifndef CONFIG_USER_ONLY
715 dc->vmsd = &vmstate_loongarch_cpu;
716 cc->sysemu_ops = &loongarch_sysemu_ops;
717#endif
718 cc->disas_set_info = loongarch_cpu_disas_set_info;
719 cc->gdb_read_register = loongarch_cpu_gdb_read_register;
720 cc->gdb_write_register = loongarch_cpu_gdb_write_register;
721 cc->disas_set_info = loongarch_cpu_disas_set_info;
722 cc->gdb_num_core_regs = 35;
723 cc->gdb_core_xml_file = "loongarch-base64.xml";
724 cc->gdb_stop_before_watchpoint = true;
725 cc->gdb_arch_name = loongarch_gdb_arch_name;
726
727#ifdef CONFIG_TCG
728 cc->tcg_ops = &loongarch_tcg_ops;
729#endif
730}
731
732#define DEFINE_LOONGARCH_CPU_TYPE(model, initfn) \
733 { \
734 .parent = TYPE_LOONGARCH_CPU, \
735 .instance_init = initfn, \
736 .name = LOONGARCH_CPU_TYPE_NAME(model), \
737 }
738
739static const TypeInfo loongarch_cpu_type_infos[] = {
740 {
741 .name = TYPE_LOONGARCH_CPU,
742 .parent = TYPE_CPU,
743 .instance_size = sizeof(LoongArchCPU),
744 .instance_init = loongarch_cpu_init,
745
746 .abstract = true,
747 .class_size = sizeof(LoongArchCPUClass),
748 .class_init = loongarch_cpu_class_init,
749 },
750 DEFINE_LOONGARCH_CPU_TYPE("la464", loongarch_la464_initfn),
751};
752
753DEFINE_TYPES(loongarch_cpu_type_infos)
754
