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20#include "qemu/osdep.h"
21#include "qemu/units.h"
22#include "cpu.h"
23#include "exec/exec-all.h"
24#include "qemu/error-report.h"
25#include "qemu/qemu-print.h"
26#include "sysemu/hw_accel.h"
27#include "kvm_ppc.h"
28#include "mmu-hash64.h"
29#include "exec/log.h"
30#include "hw/hw.h"
31#include "internal.h"
32#include "mmu-book3s-v3.h"
33#include "helper_regs.h"
34
35#ifdef CONFIG_TCG
36#include "exec/helper-proto.h"
37#endif
38
39
40
41#ifdef DEBUG_SLB
42# define LOG_SLB(...) qemu_log_mask(CPU_LOG_MMU, __VA_ARGS__)
43#else
44# define LOG_SLB(...) do { } while (0)
45#endif
46
47
48
49
50
51static ppc_slb_t *slb_lookup(PowerPCCPU *cpu, target_ulong eaddr)
52{
53 CPUPPCState *env = &cpu->env;
54 uint64_t esid_256M, esid_1T;
55 int n;
56
57 LOG_SLB("%s: eaddr " TARGET_FMT_lx "\n", __func__, eaddr);
58
59 esid_256M = (eaddr & SEGMENT_MASK_256M) | SLB_ESID_V;
60 esid_1T = (eaddr & SEGMENT_MASK_1T) | SLB_ESID_V;
61
62 for (n = 0; n < cpu->hash64_opts->slb_size; n++) {
63 ppc_slb_t *slb = &env->slb[n];
64
65 LOG_SLB("%s: slot %d %016" PRIx64 " %016"
66 PRIx64 "\n", __func__, n, slb->esid, slb->vsid);
67
68
69
70
71
72 if (((slb->esid == esid_256M) &&
73 ((slb->vsid & SLB_VSID_B) == SLB_VSID_B_256M))
74 || ((slb->esid == esid_1T) &&
75 ((slb->vsid & SLB_VSID_B) == SLB_VSID_B_1T))) {
76 return slb;
77 }
78 }
79
80 return NULL;
81}
82
83void dump_slb(PowerPCCPU *cpu)
84{
85 CPUPPCState *env = &cpu->env;
86 int i;
87 uint64_t slbe, slbv;
88
89 cpu_synchronize_state(CPU(cpu));
90
91 qemu_printf("SLB\tESID\t\t\tVSID\n");
92 for (i = 0; i < cpu->hash64_opts->slb_size; i++) {
93 slbe = env->slb[i].esid;
94 slbv = env->slb[i].vsid;
95 if (slbe == 0 && slbv == 0) {
96 continue;
97 }
98 qemu_printf("%d\t0x%016" PRIx64 "\t0x%016" PRIx64 "\n",
99 i, slbe, slbv);
100 }
101}
102
103#ifdef CONFIG_TCG
104void helper_SLBIA(CPUPPCState *env, uint32_t ih)
105{
106 PowerPCCPU *cpu = env_archcpu(env);
107 int starting_entry;
108 int n;
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131 env->tlb_need_flush |= TLB_NEED_LOCAL_FLUSH;
132
133 starting_entry = 1;
134
135 if (env->mmu_model == POWERPC_MMU_3_00) {
136 switch (ih) {
137 case 0x7:
138
139 return;
140
141 case 0x3:
142 case 0x4:
143
144 starting_entry = 0;
145 break;
146
147 case 0x5:
148
149 qemu_log_mask(LOG_GUEST_ERROR,
150 "slbia undefined IH field %u.\n", ih);
151 break;
152
153 default:
154
155 break;
156 }
157 }
158
159 for (n = starting_entry; n < cpu->hash64_opts->slb_size; n++) {
160 ppc_slb_t *slb = &env->slb[n];
161
162 if (!(slb->esid & SLB_ESID_V)) {
163 continue;
164 }
165 if (env->mmu_model == POWERPC_MMU_3_00) {
166 if (ih == 0x3 && (slb->vsid & SLB_VSID_C) == 0) {
167
168 continue;
169 }
170 }
171
172 slb->esid &= ~SLB_ESID_V;
173 }
174}
175
176#if defined(TARGET_PPC64)
177void helper_SLBIAG(CPUPPCState *env, target_ulong rs, uint32_t l)
178{
179 PowerPCCPU *cpu = env_archcpu(env);
180 int n;
181
182
183
184
185
186
187
188
189
190
191
192
193
194 env->tlb_need_flush |= TLB_NEED_LOCAL_FLUSH;
195
196 for (n = 0; n < cpu->hash64_opts->slb_size; n++) {
197 ppc_slb_t *slb = &env->slb[n];
198 slb->esid &= ~SLB_ESID_V;
199 }
200}
201#endif
202
203static void __helper_slbie(CPUPPCState *env, target_ulong addr,
204 target_ulong global)
205{
206 PowerPCCPU *cpu = env_archcpu(env);
207 ppc_slb_t *slb;
208
209 slb = slb_lookup(cpu, addr);
210 if (!slb) {
211 return;
212 }
213
214 if (slb->esid & SLB_ESID_V) {
215 slb->esid &= ~SLB_ESID_V;
216
217
218
219
220
221
222 env->tlb_need_flush |=
223 (global == false ? TLB_NEED_LOCAL_FLUSH : TLB_NEED_GLOBAL_FLUSH);
224 }
225}
226
227void helper_SLBIE(CPUPPCState *env, target_ulong addr)
228{
229 __helper_slbie(env, addr, false);
230}
231
232void helper_SLBIEG(CPUPPCState *env, target_ulong addr)
233{
234 __helper_slbie(env, addr, true);
235}
236#endif
237
238int ppc_store_slb(PowerPCCPU *cpu, target_ulong slot,
239 target_ulong esid, target_ulong vsid)
240{
241 CPUPPCState *env = &cpu->env;
242 ppc_slb_t *slb = &env->slb[slot];
243 const PPCHash64SegmentPageSizes *sps = NULL;
244 int i;
245
246 if (slot >= cpu->hash64_opts->slb_size) {
247 return -1;
248 }
249 if (esid & ~(SLB_ESID_ESID | SLB_ESID_V)) {
250 return -1;
251 }
252 if (vsid & (SLB_VSID_B & ~SLB_VSID_B_1T)) {
253 return -1;
254 }
255 if ((vsid & SLB_VSID_B) && !(ppc_hash64_has(cpu, PPC_HASH64_1TSEG))) {
256 return -1;
257 }
258
259 for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) {
260 const PPCHash64SegmentPageSizes *sps1 = &cpu->hash64_opts->sps[i];
261
262 if (!sps1->page_shift) {
263 break;
264 }
265
266 if ((vsid & SLB_VSID_LLP_MASK) == sps1->slb_enc) {
267 sps = sps1;
268 break;
269 }
270 }
271
272 if (!sps) {
273 error_report("Bad page size encoding in SLB store: slot "TARGET_FMT_lu
274 " esid 0x"TARGET_FMT_lx" vsid 0x"TARGET_FMT_lx,
275 slot, esid, vsid);
276 return -1;
277 }
278
279 slb->esid = esid;
280 slb->vsid = vsid;
281 slb->sps = sps;
282
283 LOG_SLB("%s: " TARGET_FMT_lu " " TARGET_FMT_lx " - " TARGET_FMT_lx
284 " => %016" PRIx64 " %016" PRIx64 "\n", __func__, slot, esid, vsid,
285 slb->esid, slb->vsid);
286
287 return 0;
288}
289
290#ifdef CONFIG_TCG
291static int ppc_load_slb_esid(PowerPCCPU *cpu, target_ulong rb,
292 target_ulong *rt)
293{
294 CPUPPCState *env = &cpu->env;
295 int slot = rb & 0xfff;
296 ppc_slb_t *slb = &env->slb[slot];
297
298 if (slot >= cpu->hash64_opts->slb_size) {
299 return -1;
300 }
301
302 *rt = slb->esid;
303 return 0;
304}
305
306static int ppc_load_slb_vsid(PowerPCCPU *cpu, target_ulong rb,
307 target_ulong *rt)
308{
309 CPUPPCState *env = &cpu->env;
310 int slot = rb & 0xfff;
311 ppc_slb_t *slb = &env->slb[slot];
312
313 if (slot >= cpu->hash64_opts->slb_size) {
314 return -1;
315 }
316
317 *rt = slb->vsid;
318 return 0;
319}
320
321static int ppc_find_slb_vsid(PowerPCCPU *cpu, target_ulong rb,
322 target_ulong *rt)
323{
324 CPUPPCState *env = &cpu->env;
325 ppc_slb_t *slb;
326
327 if (!msr_is_64bit(env, env->msr)) {
328 rb &= 0xffffffff;
329 }
330 slb = slb_lookup(cpu, rb);
331 if (slb == NULL) {
332 *rt = (target_ulong)-1ul;
333 } else {
334 *rt = slb->vsid;
335 }
336 return 0;
337}
338
339void helper_SLBMTE(CPUPPCState *env, target_ulong rb, target_ulong rs)
340{
341 PowerPCCPU *cpu = env_archcpu(env);
342
343 if (ppc_store_slb(cpu, rb & 0xfff, rb & ~0xfffULL, rs) < 0) {
344 raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM,
345 POWERPC_EXCP_INVAL, GETPC());
346 }
347}
348
349target_ulong helper_SLBMFEE(CPUPPCState *env, target_ulong rb)
350{
351 PowerPCCPU *cpu = env_archcpu(env);
352 target_ulong rt = 0;
353
354 if (ppc_load_slb_esid(cpu, rb, &rt) < 0) {
355 raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM,
356 POWERPC_EXCP_INVAL, GETPC());
357 }
358 return rt;
359}
360
361target_ulong helper_SLBFEE(CPUPPCState *env, target_ulong rb)
362{
363 PowerPCCPU *cpu = env_archcpu(env);
364 target_ulong rt = 0;
365
366 if (ppc_find_slb_vsid(cpu, rb, &rt) < 0) {
367 raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM,
368 POWERPC_EXCP_INVAL, GETPC());
369 }
370 return rt;
371}
372
373target_ulong helper_SLBMFEV(CPUPPCState *env, target_ulong rb)
374{
375 PowerPCCPU *cpu = env_archcpu(env);
376 target_ulong rt = 0;
377
378 if (ppc_load_slb_vsid(cpu, rb, &rt) < 0) {
379 raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM,
380 POWERPC_EXCP_INVAL, GETPC());
381 }
382 return rt;
383}
384#endif
385
386
387static inline int ppc_hash64_pte_noexec_guard(PowerPCCPU *cpu,
388 ppc_hash_pte64_t pte)
389{
390
391 return (pte.pte1 & HPTE64_R_N) || (pte.pte1 & HPTE64_R_G) ?
392 PAGE_READ | PAGE_WRITE : PAGE_READ | PAGE_WRITE | PAGE_EXEC;
393}
394
395
396static int ppc_hash64_pte_prot(int mmu_idx,
397 ppc_slb_t *slb, ppc_hash_pte64_t pte)
398{
399 unsigned pp, key;
400
401
402
403
404 int prot = 0;
405
406 key = !!(mmuidx_pr(mmu_idx) ? (slb->vsid & SLB_VSID_KP)
407 : (slb->vsid & SLB_VSID_KS));
408 pp = (pte.pte1 & HPTE64_R_PP) | ((pte.pte1 & HPTE64_R_PP0) >> 61);
409
410 if (key == 0) {
411 switch (pp) {
412 case 0x0:
413 case 0x1:
414 case 0x2:
415 prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
416 break;
417
418 case 0x3:
419 case 0x6:
420 prot = PAGE_READ | PAGE_EXEC;
421 break;
422 }
423 } else {
424 switch (pp) {
425 case 0x0:
426 case 0x6:
427 break;
428
429 case 0x1:
430 case 0x3:
431 prot = PAGE_READ | PAGE_EXEC;
432 break;
433
434 case 0x2:
435 prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
436 break;
437 }
438 }
439
440 return prot;
441}
442
443
444static int ppc_hash64_iamr_prot(PowerPCCPU *cpu, int key)
445{
446 CPUPPCState *env = &cpu->env;
447 int iamr_bits = (env->spr[SPR_IAMR] >> 2 * (31 - key)) & 0x3;
448
449
450
451
452
453
454
455
456 return (iamr_bits & 0x1) ? PAGE_READ | PAGE_WRITE :
457 PAGE_READ | PAGE_WRITE | PAGE_EXEC;
458}
459
460static int ppc_hash64_amr_prot(PowerPCCPU *cpu, ppc_hash_pte64_t pte)
461{
462 CPUPPCState *env = &cpu->env;
463 int key, amrbits;
464 int prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
465
466
467 if (!ppc_hash64_has(cpu, PPC_HASH64_AMR)) {
468 return prot;
469 }
470
471 key = HPTE64_R_KEY(pte.pte1);
472 amrbits = (env->spr[SPR_AMR] >> 2 * (31 - key)) & 0x3;
473
474
475
476
477
478
479
480
481 if (amrbits & 0x2) {
482 prot &= ~PAGE_WRITE;
483 }
484
485
486
487
488 if (amrbits & 0x1) {
489 prot &= ~PAGE_READ;
490 }
491
492 switch (env->mmu_model) {
493
494
495
496
497
498
499 case POWERPC_MMU_2_07:
500 case POWERPC_MMU_3_00:
501 prot &= ppc_hash64_iamr_prot(cpu, key);
502 break;
503 default:
504 break;
505 }
506
507 return prot;
508}
509
510const ppc_hash_pte64_t *ppc_hash64_map_hptes(PowerPCCPU *cpu,
511 hwaddr ptex, int n)
512{
513 hwaddr pte_offset = ptex * HASH_PTE_SIZE_64;
514 hwaddr base;
515 hwaddr plen = n * HASH_PTE_SIZE_64;
516 const ppc_hash_pte64_t *hptes;
517
518 if (cpu->vhyp) {
519 PPCVirtualHypervisorClass *vhc =
520 PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
521 return vhc->map_hptes(cpu->vhyp, ptex, n);
522 }
523 base = ppc_hash64_hpt_base(cpu);
524
525 if (!base) {
526 return NULL;
527 }
528
529 hptes = address_space_map(CPU(cpu)->as, base + pte_offset, &plen, false,
530 MEMTXATTRS_UNSPECIFIED);
531 if (plen < (n * HASH_PTE_SIZE_64)) {
532 hw_error("%s: Unable to map all requested HPTEs\n", __func__);
533 }
534 return hptes;
535}
536
537void ppc_hash64_unmap_hptes(PowerPCCPU *cpu, const ppc_hash_pte64_t *hptes,
538 hwaddr ptex, int n)
539{
540 if (cpu->vhyp) {
541 PPCVirtualHypervisorClass *vhc =
542 PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
543 vhc->unmap_hptes(cpu->vhyp, hptes, ptex, n);
544 return;
545 }
546
547 address_space_unmap(CPU(cpu)->as, (void *)hptes, n * HASH_PTE_SIZE_64,
548 false, n * HASH_PTE_SIZE_64);
549}
550
551static unsigned hpte_page_shift(const PPCHash64SegmentPageSizes *sps,
552 uint64_t pte0, uint64_t pte1)
553{
554 int i;
555
556 if (!(pte0 & HPTE64_V_LARGE)) {
557 if (sps->page_shift != 12) {
558
559 return 0;
560 }
561
562 return 12;
563 }
564
565 for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) {
566 const PPCHash64PageSize *ps = &sps->enc[i];
567 uint64_t mask;
568
569 if (!ps->page_shift) {
570 break;
571 }
572
573 if (ps->page_shift == 12) {
574
575 continue;
576 }
577
578 mask = ((1ULL << ps->page_shift) - 1) & HPTE64_R_RPN;
579
580 if ((pte1 & mask) == ((uint64_t)ps->pte_enc << HPTE64_R_RPN_SHIFT)) {
581 return ps->page_shift;
582 }
583 }
584
585 return 0;
586}
587
588static void ppc64_v3_new_to_old_hpte(target_ulong *pte0, target_ulong *pte1)
589{
590
591 *pte0 = (*pte0 & HPTE64_V_COMMON_BITS) |
592 ((*pte1 & HPTE64_R_3_0_SSIZE_MASK) <<
593 (HPTE64_V_SSIZE_SHIFT - HPTE64_R_3_0_SSIZE_SHIFT));
594
595
596 *pte1 = *pte1 & ~HPTE64_R_3_0_SSIZE_MASK;
597}
598
599
600static hwaddr ppc_hash64_pteg_search(PowerPCCPU *cpu, hwaddr hash,
601 const PPCHash64SegmentPageSizes *sps,
602 target_ulong ptem,
603 ppc_hash_pte64_t *pte, unsigned *pshift)
604{
605 int i;
606 const ppc_hash_pte64_t *pteg;
607 target_ulong pte0, pte1;
608 target_ulong ptex;
609
610 ptex = (hash & ppc_hash64_hpt_mask(cpu)) * HPTES_PER_GROUP;
611 pteg = ppc_hash64_map_hptes(cpu, ptex, HPTES_PER_GROUP);
612 if (!pteg) {
613 return -1;
614 }
615 for (i = 0; i < HPTES_PER_GROUP; i++) {
616 pte0 = ppc_hash64_hpte0(cpu, pteg, i);
617
618
619
620
621
622 smp_rmb();
623 pte1 = ppc_hash64_hpte1(cpu, pteg, i);
624
625
626 if (cpu->env.mmu_model == POWERPC_MMU_3_00 && !cpu->vhyp) {
627 ppc64_v3_new_to_old_hpte(&pte0, &pte1);
628 }
629
630
631 if (HPTE64_V_COMPARE(pte0, ptem)) {
632 *pshift = hpte_page_shift(sps, pte0, pte1);
633
634
635
636
637
638
639
640 if (*pshift == 0) {
641 continue;
642 }
643
644
645
646
647 pte->pte0 = pte0;
648 pte->pte1 = pte1;
649 ppc_hash64_unmap_hptes(cpu, pteg, ptex, HPTES_PER_GROUP);
650 return ptex + i;
651 }
652 }
653 ppc_hash64_unmap_hptes(cpu, pteg, ptex, HPTES_PER_GROUP);
654
655
656
657 return -1;
658}
659
660static hwaddr ppc_hash64_htab_lookup(PowerPCCPU *cpu,
661 ppc_slb_t *slb, target_ulong eaddr,
662 ppc_hash_pte64_t *pte, unsigned *pshift)
663{
664 CPUPPCState *env = &cpu->env;
665 hwaddr hash, ptex;
666 uint64_t vsid, epnmask, epn, ptem;
667 const PPCHash64SegmentPageSizes *sps = slb->sps;
668
669
670
671
672
673 assert(sps);
674
675
676 if (env->spr[SPR_LPCR] & LPCR_ISL) {
677
678 sps = &cpu->hash64_opts->sps[0];
679 assert(sps->page_shift == 12);
680 }
681
682 epnmask = ~((1ULL << sps->page_shift) - 1);
683
684 if (slb->vsid & SLB_VSID_B) {
685
686 vsid = (slb->vsid & SLB_VSID_VSID) >> SLB_VSID_SHIFT_1T;
687 epn = (eaddr & ~SEGMENT_MASK_1T) & epnmask;
688 hash = vsid ^ (vsid << 25) ^ (epn >> sps->page_shift);
689 } else {
690
691 vsid = (slb->vsid & SLB_VSID_VSID) >> SLB_VSID_SHIFT;
692 epn = (eaddr & ~SEGMENT_MASK_256M) & epnmask;
693 hash = vsid ^ (epn >> sps->page_shift);
694 }
695 ptem = (slb->vsid & SLB_VSID_PTEM) | ((epn >> 16) & HPTE64_V_AVPN);
696 ptem |= HPTE64_V_VALID;
697
698
699 qemu_log_mask(CPU_LOG_MMU,
700 "htab_base " HWADDR_FMT_plx " htab_mask " HWADDR_FMT_plx
701 " hash " HWADDR_FMT_plx "\n",
702 ppc_hash64_hpt_base(cpu), ppc_hash64_hpt_mask(cpu), hash);
703
704
705 qemu_log_mask(CPU_LOG_MMU,
706 "0 htab=" HWADDR_FMT_plx "/" HWADDR_FMT_plx
707 " vsid=" TARGET_FMT_lx " ptem=" TARGET_FMT_lx
708 " hash=" HWADDR_FMT_plx "\n",
709 ppc_hash64_hpt_base(cpu), ppc_hash64_hpt_mask(cpu),
710 vsid, ptem, hash);
711 ptex = ppc_hash64_pteg_search(cpu, hash, sps, ptem, pte, pshift);
712
713 if (ptex == -1) {
714
715 ptem |= HPTE64_V_SECONDARY;
716 qemu_log_mask(CPU_LOG_MMU,
717 "1 htab=" HWADDR_FMT_plx "/" HWADDR_FMT_plx
718 " vsid=" TARGET_FMT_lx " api=" TARGET_FMT_lx
719 " hash=" HWADDR_FMT_plx "\n", ppc_hash64_hpt_base(cpu),
720 ppc_hash64_hpt_mask(cpu), vsid, ptem, ~hash);
721
722 ptex = ppc_hash64_pteg_search(cpu, ~hash, sps, ptem, pte, pshift);
723 }
724
725 return ptex;
726}
727
728unsigned ppc_hash64_hpte_page_shift_noslb(PowerPCCPU *cpu,
729 uint64_t pte0, uint64_t pte1)
730{
731 int i;
732
733 if (!(pte0 & HPTE64_V_LARGE)) {
734 return 12;
735 }
736
737
738
739
740
741 for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) {
742 const PPCHash64SegmentPageSizes *sps = &cpu->hash64_opts->sps[i];
743 unsigned shift;
744
745 if (!sps->page_shift) {
746 break;
747 }
748
749 shift = hpte_page_shift(sps, pte0, pte1);
750 if (shift) {
751 return shift;
752 }
753 }
754
755 return 0;
756}
757
758static bool ppc_hash64_use_vrma(CPUPPCState *env)
759{
760 switch (env->mmu_model) {
761 case POWERPC_MMU_3_00:
762
763
764
765
766 return true;
767
768 default:
769 return !!(env->spr[SPR_LPCR] & LPCR_VPM0);
770 }
771}
772
773static void ppc_hash64_set_isi(CPUState *cs, int mmu_idx, uint64_t error_code)
774{
775 CPUPPCState *env = &POWERPC_CPU(cs)->env;
776 bool vpm;
777
778 if (!mmuidx_real(mmu_idx)) {
779 vpm = !!(env->spr[SPR_LPCR] & LPCR_VPM1);
780 } else {
781 vpm = ppc_hash64_use_vrma(env);
782 }
783 if (vpm && !mmuidx_hv(mmu_idx)) {
784 cs->exception_index = POWERPC_EXCP_HISI;
785 } else {
786 cs->exception_index = POWERPC_EXCP_ISI;
787 }
788 env->error_code = error_code;
789}
790
791static void ppc_hash64_set_dsi(CPUState *cs, int mmu_idx, uint64_t dar, uint64_t dsisr)
792{
793 CPUPPCState *env = &POWERPC_CPU(cs)->env;
794 bool vpm;
795
796 if (!mmuidx_real(mmu_idx)) {
797 vpm = !!(env->spr[SPR_LPCR] & LPCR_VPM1);
798 } else {
799 vpm = ppc_hash64_use_vrma(env);
800 }
801 if (vpm && !mmuidx_hv(mmu_idx)) {
802 cs->exception_index = POWERPC_EXCP_HDSI;
803 env->spr[SPR_HDAR] = dar;
804 env->spr[SPR_HDSISR] = dsisr;
805 } else {
806 cs->exception_index = POWERPC_EXCP_DSI;
807 env->spr[SPR_DAR] = dar;
808 env->spr[SPR_DSISR] = dsisr;
809 }
810 env->error_code = 0;
811}
812
813
814static void ppc_hash64_set_r(PowerPCCPU *cpu, hwaddr ptex, uint64_t pte1)
815{
816 hwaddr base, offset = ptex * HASH_PTE_SIZE_64 + HPTE64_DW1_R;
817
818 if (cpu->vhyp) {
819 PPCVirtualHypervisorClass *vhc =
820 PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
821 vhc->hpte_set_r(cpu->vhyp, ptex, pte1);
822 return;
823 }
824 base = ppc_hash64_hpt_base(cpu);
825
826
827
828 stb_phys(CPU(cpu)->as, base + offset, ((pte1 >> 8) & 0xff) | 0x01);
829}
830
831static void ppc_hash64_set_c(PowerPCCPU *cpu, hwaddr ptex, uint64_t pte1)
832{
833 hwaddr base, offset = ptex * HASH_PTE_SIZE_64 + HPTE64_DW1_C;
834
835 if (cpu->vhyp) {
836 PPCVirtualHypervisorClass *vhc =
837 PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
838 vhc->hpte_set_c(cpu->vhyp, ptex, pte1);
839 return;
840 }
841 base = ppc_hash64_hpt_base(cpu);
842
843
844 stb_phys(CPU(cpu)->as, base + offset, (pte1 & 0xff) | 0x80);
845}
846
847static target_ulong rmls_limit(PowerPCCPU *cpu)
848{
849 CPUPPCState *env = &cpu->env;
850
851
852
853
854
855
856
857
858
859 static const target_ulong rma_sizes[16] = {
860 [0] = 256 * GiB,
861 [1] = 16 * GiB,
862 [2] = 1 * GiB,
863 [3] = 64 * MiB,
864 [4] = 256 * MiB,
865 [7] = 128 * MiB,
866 [8] = 32 * MiB,
867 };
868 target_ulong rmls = (env->spr[SPR_LPCR] & LPCR_RMLS) >> LPCR_RMLS_SHIFT;
869
870 return rma_sizes[rmls];
871}
872
873static int build_vrma_slbe(PowerPCCPU *cpu, ppc_slb_t *slb)
874{
875 CPUPPCState *env = &cpu->env;
876 target_ulong lpcr = env->spr[SPR_LPCR];
877 uint32_t vrmasd = (lpcr & LPCR_VRMASD) >> LPCR_VRMASD_SHIFT;
878 target_ulong vsid = SLB_VSID_VRMA | ((vrmasd << 4) & SLB_VSID_LLP_MASK);
879 int i;
880
881 for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) {
882 const PPCHash64SegmentPageSizes *sps = &cpu->hash64_opts->sps[i];
883
884 if (!sps->page_shift) {
885 break;
886 }
887
888 if ((vsid & SLB_VSID_LLP_MASK) == sps->slb_enc) {
889 slb->esid = SLB_ESID_V;
890 slb->vsid = vsid;
891 slb->sps = sps;
892 return 0;
893 }
894 }
895
896 error_report("Bad page size encoding in LPCR[VRMASD]; LPCR=0x"
897 TARGET_FMT_lx, lpcr);
898
899 return -1;
900}
901
902bool ppc_hash64_xlate(PowerPCCPU *cpu, vaddr eaddr, MMUAccessType access_type,
903 hwaddr *raddrp, int *psizep, int *protp, int mmu_idx,
904 bool guest_visible)
905{
906 CPUState *cs = CPU(cpu);
907 CPUPPCState *env = &cpu->env;
908 ppc_slb_t vrma_slbe;
909 ppc_slb_t *slb;
910 unsigned apshift;
911 hwaddr ptex;
912 ppc_hash_pte64_t pte;
913 int exec_prot, pp_prot, amr_prot, prot;
914 int need_prot;
915 hwaddr raddr;
916
917
918
919
920
921
922
923
924
925
926 if (mmuidx_real(mmu_idx)) {
927
928
929
930
931 raddr = eaddr & 0x0FFFFFFFFFFFFFFFULL;
932
933 if (cpu->vhyp) {
934
935
936
937
938 } else if (mmuidx_hv(mmu_idx) || !env->has_hv_mode) {
939
940 if (!(eaddr >> 63)) {
941 raddr |= env->spr[SPR_HRMOR];
942 }
943 } else if (ppc_hash64_use_vrma(env)) {
944
945 slb = &vrma_slbe;
946 if (build_vrma_slbe(cpu, slb) != 0) {
947
948 if (guest_visible) {
949 cs->exception_index = POWERPC_EXCP_MCHECK;
950 env->error_code = 0;
951 }
952 return false;
953 }
954
955 goto skip_slb_search;
956 } else {
957 target_ulong limit = rmls_limit(cpu);
958
959
960 if (raddr >= limit) {
961 if (!guest_visible) {
962 return false;
963 }
964 switch (access_type) {
965 case MMU_INST_FETCH:
966 ppc_hash64_set_isi(cs, mmu_idx, SRR1_PROTFAULT);
967 break;
968 case MMU_DATA_LOAD:
969 ppc_hash64_set_dsi(cs, mmu_idx, eaddr, DSISR_PROTFAULT);
970 break;
971 case MMU_DATA_STORE:
972 ppc_hash64_set_dsi(cs, mmu_idx, eaddr,
973 DSISR_PROTFAULT | DSISR_ISSTORE);
974 break;
975 default:
976 g_assert_not_reached();
977 }
978 return false;
979 }
980
981 raddr |= env->spr[SPR_RMOR];
982 }
983
984 *raddrp = raddr;
985 *protp = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
986 *psizep = TARGET_PAGE_BITS;
987 return true;
988 }
989
990
991 slb = slb_lookup(cpu, eaddr);
992 if (!slb) {
993
994 if (ppc64_use_proc_tbl(cpu)) {
995
996 error_report("Segment Table Support Unimplemented");
997 exit(1);
998 }
999
1000 if (!guest_visible) {
1001 return false;
1002 }
1003 switch (access_type) {
1004 case MMU_INST_FETCH:
1005 cs->exception_index = POWERPC_EXCP_ISEG;
1006 env->error_code = 0;
1007 break;
1008 case MMU_DATA_LOAD:
1009 case MMU_DATA_STORE:
1010 cs->exception_index = POWERPC_EXCP_DSEG;
1011 env->error_code = 0;
1012 env->spr[SPR_DAR] = eaddr;
1013 break;
1014 default:
1015 g_assert_not_reached();
1016 }
1017 return false;
1018 }
1019
1020 skip_slb_search:
1021
1022
1023 if (access_type == MMU_INST_FETCH && (slb->vsid & SLB_VSID_N)) {
1024 if (guest_visible) {
1025 ppc_hash64_set_isi(cs, mmu_idx, SRR1_NOEXEC_GUARD);
1026 }
1027 return false;
1028 }
1029
1030
1031 ptex = ppc_hash64_htab_lookup(cpu, slb, eaddr, &pte, &apshift);
1032 if (ptex == -1) {
1033 if (!guest_visible) {
1034 return false;
1035 }
1036 switch (access_type) {
1037 case MMU_INST_FETCH:
1038 ppc_hash64_set_isi(cs, mmu_idx, SRR1_NOPTE);
1039 break;
1040 case MMU_DATA_LOAD:
1041 ppc_hash64_set_dsi(cs, mmu_idx, eaddr, DSISR_NOPTE);
1042 break;
1043 case MMU_DATA_STORE:
1044 ppc_hash64_set_dsi(cs, mmu_idx, eaddr, DSISR_NOPTE | DSISR_ISSTORE);
1045 break;
1046 default:
1047 g_assert_not_reached();
1048 }
1049 return false;
1050 }
1051 qemu_log_mask(CPU_LOG_MMU,
1052 "found PTE at index %08" HWADDR_PRIx "\n", ptex);
1053
1054
1055
1056 exec_prot = ppc_hash64_pte_noexec_guard(cpu, pte);
1057 pp_prot = ppc_hash64_pte_prot(mmu_idx, slb, pte);
1058 amr_prot = ppc_hash64_amr_prot(cpu, pte);
1059 prot = exec_prot & pp_prot & amr_prot;
1060
1061 need_prot = prot_for_access_type(access_type);
1062 if (need_prot & ~prot) {
1063
1064 qemu_log_mask(CPU_LOG_MMU, "PTE access rejected\n");
1065 if (!guest_visible) {
1066 return false;
1067 }
1068 if (access_type == MMU_INST_FETCH) {
1069 int srr1 = 0;
1070 if (PAGE_EXEC & ~exec_prot) {
1071 srr1 |= SRR1_NOEXEC_GUARD;
1072 } else if (PAGE_EXEC & ~pp_prot) {
1073 srr1 |= SRR1_PROTFAULT;
1074 }
1075 if (PAGE_EXEC & ~amr_prot) {
1076 srr1 |= SRR1_IAMR;
1077 }
1078 ppc_hash64_set_isi(cs, mmu_idx, srr1);
1079 } else {
1080 int dsisr = 0;
1081 if (need_prot & ~pp_prot) {
1082 dsisr |= DSISR_PROTFAULT;
1083 }
1084 if (access_type == MMU_DATA_STORE) {
1085 dsisr |= DSISR_ISSTORE;
1086 }
1087 if (need_prot & ~amr_prot) {
1088 dsisr |= DSISR_AMR;
1089 }
1090 ppc_hash64_set_dsi(cs, mmu_idx, eaddr, dsisr);
1091 }
1092 return false;
1093 }
1094
1095 qemu_log_mask(CPU_LOG_MMU, "PTE access granted !\n");
1096
1097
1098
1099 if (!(pte.pte1 & HPTE64_R_R)) {
1100 ppc_hash64_set_r(cpu, ptex, pte.pte1);
1101 }
1102 if (!(pte.pte1 & HPTE64_R_C)) {
1103 if (access_type == MMU_DATA_STORE) {
1104 ppc_hash64_set_c(cpu, ptex, pte.pte1);
1105 } else {
1106
1107
1108
1109
1110 prot &= ~PAGE_WRITE;
1111 }
1112 }
1113
1114
1115
1116 *raddrp = deposit64(pte.pte1 & HPTE64_R_RPN, 0, apshift, eaddr);
1117 *protp = prot;
1118 *psizep = apshift;
1119 return true;
1120}
1121
1122void ppc_hash64_tlb_flush_hpte(PowerPCCPU *cpu, target_ulong ptex,
1123 target_ulong pte0, target_ulong pte1)
1124{
1125
1126
1127
1128
1129
1130 cpu->env.tlb_need_flush = TLB_NEED_GLOBAL_FLUSH | TLB_NEED_LOCAL_FLUSH;
1131}
1132
1133#ifdef CONFIG_TCG
1134void helper_store_lpcr(CPUPPCState *env, target_ulong val)
1135{
1136 PowerPCCPU *cpu = env_archcpu(env);
1137
1138 ppc_store_lpcr(cpu, val);
1139}
1140#endif
1141
1142void ppc_hash64_init(PowerPCCPU *cpu)
1143{
1144 CPUPPCState *env = &cpu->env;
1145 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
1146
1147 if (!pcc->hash64_opts) {
1148 assert(!mmu_is_64bit(env->mmu_model));
1149 return;
1150 }
1151
1152 cpu->hash64_opts = g_memdup(pcc->hash64_opts, sizeof(*cpu->hash64_opts));
1153}
1154
1155void ppc_hash64_finalize(PowerPCCPU *cpu)
1156{
1157 g_free(cpu->hash64_opts);
1158}
1159
1160const PPCHash64Options ppc_hash64_opts_basic = {
1161 .flags = 0,
1162 .slb_size = 64,
1163 .sps = {
1164 { .page_shift = 12,
1165 .slb_enc = 0,
1166 .enc = { { .page_shift = 12, .pte_enc = 0 } }
1167 },
1168 { .page_shift = 24,
1169 .slb_enc = 0x100,
1170 .enc = { { .page_shift = 24, .pte_enc = 0 } }
1171 },
1172 },
1173};
1174
1175const PPCHash64Options ppc_hash64_opts_POWER7 = {
1176 .flags = PPC_HASH64_1TSEG | PPC_HASH64_AMR | PPC_HASH64_CI_LARGEPAGE,
1177 .slb_size = 32,
1178 .sps = {
1179 {
1180 .page_shift = 12,
1181 .slb_enc = 0,
1182 .enc = { { .page_shift = 12, .pte_enc = 0 },
1183 { .page_shift = 16, .pte_enc = 0x7 },
1184 { .page_shift = 24, .pte_enc = 0x38 }, },
1185 },
1186 {
1187 .page_shift = 16,
1188 .slb_enc = SLB_VSID_64K,
1189 .enc = { { .page_shift = 16, .pte_enc = 0x1 },
1190 { .page_shift = 24, .pte_enc = 0x8 }, },
1191 },
1192 {
1193 .page_shift = 24,
1194 .slb_enc = SLB_VSID_16M,
1195 .enc = { { .page_shift = 24, .pte_enc = 0 }, },
1196 },
1197 {
1198 .page_shift = 34,
1199 .slb_enc = SLB_VSID_16G,
1200 .enc = { { .page_shift = 34, .pte_enc = 0x3 }, },
1201 },
1202 }
1203};
1204
1205
1206