1/****************************************************************************** 2 * arch-arm.h 3 * 4 * Guest OS interface to ARM Xen. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to 8 * deal in the Software without restriction, including without limitation the 9 * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or 10 * sell copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 19 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 22 * DEALINGS IN THE SOFTWARE. 23 * 24 * Copyright 2011 (C) Citrix Systems 25 */ 26 27#ifndef __XEN_PUBLIC_ARCH_ARM_H__ 28#define __XEN_PUBLIC_ARCH_ARM_H__ 29 30/* 31 * `incontents 50 arm_abi Hypercall Calling Convention 32 * 33 * A hypercall is issued using the ARM HVC instruction. 34 * 35 * A hypercall can take up to 5 arguments. These are passed in 36 * registers, the first argument in x0/r0 (for arm64/arm32 guests 37 * respectively irrespective of whether the underlying hypervisor is 38 * 32- or 64-bit), the second argument in x1/r1, the third in x2/r2, 39 * the forth in x3/r3 and the fifth in x4/r4. 40 * 41 * The hypercall number is passed in r12 (arm) or x16 (arm64). In both 42 * cases the relevant ARM procedure calling convention specifies this 43 * is an inter-procedure-call scratch register (e.g. for use in linker 44 * stubs). This use does not conflict with use during a hypercall. 45 * 46 * The HVC ISS must contain a Xen specific TAG: XEN_HYPERCALL_TAG. 47 * 48 * The return value is in x0/r0. 49 * 50 * The hypercall will clobber x16/r12 and the argument registers used 51 * by that hypercall (except r0 which is the return value) i.e. in 52 * addition to x16/r12 a 2 argument hypercall will clobber x1/r1 and a 53 * 4 argument hypercall will clobber x1/r1, x2/r2 and x3/r3. 54 * 55 * Parameter structs passed to hypercalls are laid out according to 56 * the Procedure Call Standard for the ARM Architecture (AAPCS, AKA 57 * EABI) and Procedure Call Standard for the ARM 64-bit Architecture 58 * (AAPCS64). Where there is a conflict the 64-bit standard should be 59 * used regardless of guest type. Structures which are passed as 60 * hypercall arguments are always little endian. 61 * 62 * All memory which is shared with other entities in the system 63 * (including the hypervisor and other guests) must reside in memory 64 * which is mapped as Normal Inner Write-Back Outer Write-Back Inner-Shareable. 65 * This applies to: 66 * - hypercall arguments passed via a pointer to guest memory. 67 * - memory shared via the grant table mechanism (including PV I/O 68 * rings etc). 69 * - memory shared with the hypervisor (struct shared_info, struct 70 * vcpu_info, the grant table, etc). 71 * 72 * Any cache allocation hints are acceptable. 73 */ 74 75/* 76 * `incontents 55 arm_hcall Supported Hypercalls 77 * 78 * Xen on ARM makes extensive use of hardware facilities and therefore 79 * only a subset of the potential hypercalls are required. 80 * 81 * Since ARM uses second stage paging any machine/physical addresses 82 * passed to hypercalls are Guest Physical Addresses (Intermediate 83 * Physical Addresses) unless otherwise noted. 84 * 85 * The following hypercalls (and sub operations) are supported on the 86 * ARM platform. Other hypercalls should be considered 87 * unavailable/unsupported. 88 * 89 * HYPERVISOR_memory_op 90 * All generic sub-operations 91 * 92 * HYPERVISOR_domctl 93 * All generic sub-operations, with the exception of: 94 * * XEN_DOMCTL_irq_permission (not yet implemented) 95 * 96 * HYPERVISOR_sched_op 97 * All generic sub-operations, with the exception of: 98 * * SCHEDOP_block -- prefer wfi hardware instruction 99 * 100 * HYPERVISOR_console_io 101 * All generic sub-operations 102 * 103 * HYPERVISOR_xen_version 104 * All generic sub-operations 105 * 106 * HYPERVISOR_event_channel_op 107 * All generic sub-operations 108 * 109 * HYPERVISOR_physdev_op 110 * Exactly these sub-operations are supported: 111 * PHYSDEVOP_pci_device_add 112 * PHYSDEVOP_pci_device_remove 113 * 114 * HYPERVISOR_sysctl 115 * All generic sub-operations, with the exception of: 116 * * XEN_SYSCTL_page_offline_op 117 * * XEN_SYSCTL_get_pmstat 118 * * XEN_SYSCTL_pm_op 119 * 120 * HYPERVISOR_hvm_op 121 * Exactly these sub-operations are supported: 122 * * HVMOP_set_param 123 * * HVMOP_get_param 124 * 125 * HYPERVISOR_grant_table_op 126 * All generic sub-operations 127 * 128 * HYPERVISOR_vcpu_op 129 * Exactly these sub-operations are supported: 130 * * VCPUOP_register_vcpu_info 131 * * VCPUOP_register_runstate_memory_area 132 * 133 * HYPERVISOR_argo_op 134 * All generic sub-operations 135 * 136 * Other notes on the ARM ABI: 137 * 138 * - struct start_info is not exported to ARM guests. 139 * 140 * - struct shared_info is mapped by ARM guests using the 141 * HYPERVISOR_memory_op sub-op XENMEM_add_to_physmap, passing 142 * XENMAPSPACE_shared_info as space parameter. 143 * 144 * - All the per-cpu struct vcpu_info are mapped by ARM guests using the 145 * HYPERVISOR_vcpu_op sub-op VCPUOP_register_vcpu_info, including cpu0 146 * struct vcpu_info. 147 * 148 * - The grant table is mapped using the HYPERVISOR_memory_op sub-op 149 * XENMEM_add_to_physmap, passing XENMAPSPACE_grant_table as space 150 * parameter. The memory range specified under the Xen compatible 151 * hypervisor node on device tree can be used as target gpfn for the 152 * mapping. 153 * 154 * - Xenstore is initialized by using the two hvm_params 155 * HVM_PARAM_STORE_PFN and HVM_PARAM_STORE_EVTCHN. They can be read 156 * with the HYPERVISOR_hvm_op sub-op HVMOP_get_param. 157 * 158 * - The paravirtualized console is initialized by using the two 159 * hvm_params HVM_PARAM_CONSOLE_PFN and HVM_PARAM_CONSOLE_EVTCHN. They 160 * can be read with the HYPERVISOR_hvm_op sub-op HVMOP_get_param. 161 * 162 * - Event channel notifications are delivered using the percpu GIC 163 * interrupt specified under the Xen compatible hypervisor node on 164 * device tree. 165 * 166 * - The device tree Xen compatible node is fully described under Linux 167 * at Documentation/devicetree/bindings/arm/xen.txt. 168 */ 169 170#define XEN_HYPERCALL_TAG 0XEA1 171 172#define int64_aligned_t int64_t __attribute__((aligned(8))) 173#define uint64_aligned_t uint64_t __attribute__((aligned(8))) 174 175#ifndef __ASSEMBLY__ 176#define ___DEFINE_XEN_GUEST_HANDLE(name, type) \ 177 typedef union { type *p; unsigned long q; } \ 178 __guest_handle_ ## name; \ 179 typedef union { type *p; uint64_aligned_t q; } \ 180 __guest_handle_64_ ## name 181 182/* 183 * XEN_GUEST_HANDLE represents a guest pointer, when passed as a field 184 * in a struct in memory. On ARM is always 8 bytes sizes and 8 bytes 185 * aligned. 186 * XEN_GUEST_HANDLE_PARAM represents a guest pointer, when passed as an 187 * hypercall argument. It is 4 bytes on aarch32 and 8 bytes on aarch64. 188 */ 189#define __DEFINE_XEN_GUEST_HANDLE(name, type) \ 190 ___DEFINE_XEN_GUEST_HANDLE(name, type); \ 191 ___DEFINE_XEN_GUEST_HANDLE(const_##name, const type) 192#define DEFINE_XEN_GUEST_HANDLE(name) __DEFINE_XEN_GUEST_HANDLE(name, name) 193#define __XEN_GUEST_HANDLE(name) __guest_handle_64_ ## name 194#define XEN_GUEST_HANDLE(name) __XEN_GUEST_HANDLE(name) 195#define XEN_GUEST_HANDLE_PARAM(name) __guest_handle_ ## name 196#define set_xen_guest_handle_raw(hnd, val) \ 197 do { \ 198 __typeof__(&(hnd)) _sxghr_tmp = &(hnd); \ 199 _sxghr_tmp->q = 0; \ 200 _sxghr_tmp->p = val; \ 201 } while ( 0 ) 202#define set_xen_guest_handle(hnd, val) set_xen_guest_handle_raw(hnd, val) 203 204typedef uint64_t xen_pfn_t; 205#define PRI_xen_pfn PRIx64 206#define PRIu_xen_pfn PRIu64 207 208/* 209 * Maximum number of virtual CPUs in legacy multi-processor guests. 210 * Only one. All other VCPUS must use VCPUOP_register_vcpu_info. 211 */ 212#define XEN_LEGACY_MAX_VCPUS 1 213 214typedef uint64_t xen_ulong_t; 215#define PRI_xen_ulong PRIx64 216 217#if defined(__XEN__) || defined(__XEN_TOOLS__) 218#if defined(__GNUC__) && !defined(__STRICT_ANSI__) 219/* Anonymous union includes both 32- and 64-bit names (e.g., r0/x0). */ 220# define __DECL_REG(n64, n32) union { \ 221 uint64_t n64; \ 222 uint32_t n32; \ 223 } 224#else 225/* Non-gcc sources must always use the proper 64-bit name (e.g., x0). */ 226#define __DECL_REG(n64, n32) uint64_t n64 227#endif 228 229struct vcpu_guest_core_regs 230{ 231 /* Aarch64 Aarch32 */ 232 __DECL_REG(x0, r0_usr); 233 __DECL_REG(x1, r1_usr); 234 __DECL_REG(x2, r2_usr); 235 __DECL_REG(x3, r3_usr); 236 __DECL_REG(x4, r4_usr); 237 __DECL_REG(x5, r5_usr); 238 __DECL_REG(x6, r6_usr); 239 __DECL_REG(x7, r7_usr); 240 __DECL_REG(x8, r8_usr); 241 __DECL_REG(x9, r9_usr); 242 __DECL_REG(x10, r10_usr); 243 __DECL_REG(x11, r11_usr); 244 __DECL_REG(x12, r12_usr); 245 246 __DECL_REG(x13, sp_usr); 247 __DECL_REG(x14, lr_usr); 248 249 __DECL_REG(x15, __unused_sp_hyp); 250 251 __DECL_REG(x16, lr_irq); 252 __DECL_REG(x17, sp_irq); 253 254 __DECL_REG(x18, lr_svc); 255 __DECL_REG(x19, sp_svc); 256 257 __DECL_REG(x20, lr_abt); 258 __DECL_REG(x21, sp_abt); 259 260 __DECL_REG(x22, lr_und); 261 __DECL_REG(x23, sp_und); 262 263 __DECL_REG(x24, r8_fiq); 264 __DECL_REG(x25, r9_fiq); 265 __DECL_REG(x26, r10_fiq); 266 __DECL_REG(x27, r11_fiq); 267 __DECL_REG(x28, r12_fiq); 268 269 __DECL_REG(x29, sp_fiq); 270 __DECL_REG(x30, lr_fiq); 271 272 /* Return address and mode */ 273 __DECL_REG(pc64, pc32); /* ELR_EL2 */ 274 uint64_t cpsr; /* SPSR_EL2 */ 275 276 union { 277 uint64_t spsr_el1; /* AArch64 */ 278 uint32_t spsr_svc; /* AArch32 */ 279 }; 280 281 /* AArch32 guests only */ 282 uint32_t spsr_fiq, spsr_irq, spsr_und, spsr_abt; 283 284 /* AArch64 guests only */ 285 uint64_t sp_el0; 286 uint64_t sp_el1, elr_el1; 287}; 288typedef struct vcpu_guest_core_regs vcpu_guest_core_regs_t; 289DEFINE_XEN_GUEST_HANDLE(vcpu_guest_core_regs_t); 290 291#undef __DECL_REG 292 293struct vcpu_guest_context { 294#define _VGCF_online 0 295#define VGCF_online (1<<_VGCF_online) 296 uint32_t flags; /* VGCF_* */ 297 298 struct vcpu_guest_core_regs user_regs; /* Core CPU registers */ 299 300 uint64_t sctlr; 301 uint64_t ttbcr, ttbr0, ttbr1; 302}; 303typedef struct vcpu_guest_context vcpu_guest_context_t; 304DEFINE_XEN_GUEST_HANDLE(vcpu_guest_context_t); 305 306/* 307 * struct xen_arch_domainconfig's ABI is covered by 308 * XEN_DOMCTL_INTERFACE_VERSION. 309 */ 310#define XEN_DOMCTL_CONFIG_GIC_NATIVE 0 311#define XEN_DOMCTL_CONFIG_GIC_V2 1 312#define XEN_DOMCTL_CONFIG_GIC_V3 2 313 314#define XEN_DOMCTL_CONFIG_TEE_NONE 0 315#define XEN_DOMCTL_CONFIG_TEE_OPTEE 1 316 317struct xen_arch_domainconfig { 318 /* IN/OUT */ 319 uint8_t gic_version; 320 /* IN */ 321 uint16_t tee_type; 322 /* IN */ 323 uint32_t nr_spis; 324 /* 325 * OUT 326 * Based on the property clock-frequency in the DT timer node. 327 * The property may be present when the bootloader/firmware doesn't 328 * set correctly CNTFRQ which hold the timer frequency. 329 * 330 * As it's not possible to trap this register, we have to replicate 331 * the value in the guest DT. 332 * 333 * = 0 => property not present 334 * > 0 => Value of the property 335 * 336 */ 337 uint32_t clock_frequency; 338}; 339#endif /* __XEN__ || __XEN_TOOLS__ */ 340 341struct arch_vcpu_info { 342}; 343typedef struct arch_vcpu_info arch_vcpu_info_t; 344 345struct arch_shared_info { 346}; 347typedef struct arch_shared_info arch_shared_info_t; 348typedef uint64_t xen_callback_t; 349 350#endif 351 352#if defined(__XEN__) || defined(__XEN_TOOLS__) 353 354/* PSR bits (CPSR, SPSR) */ 355 356#define PSR_THUMB (1<<5) /* Thumb Mode enable */ 357#define PSR_FIQ_MASK (1<<6) /* Fast Interrupt mask */ 358#define PSR_IRQ_MASK (1<<7) /* Interrupt mask */ 359#define PSR_ABT_MASK (1<<8) /* Asynchronous Abort mask */ 360#define PSR_BIG_ENDIAN (1<<9) /* arm32: Big Endian Mode */ 361#define PSR_DBG_MASK (1<<9) /* arm64: Debug Exception mask */ 362#define PSR_IT_MASK (0x0600fc00) /* Thumb If-Then Mask */ 363#define PSR_JAZELLE (1<<24) /* Jazelle Mode */ 364 365/* 32 bit modes */ 366#define PSR_MODE_USR 0x10 367#define PSR_MODE_FIQ 0x11 368#define PSR_MODE_IRQ 0x12 369#define PSR_MODE_SVC 0x13 370#define PSR_MODE_MON 0x16 371#define PSR_MODE_ABT 0x17 372#define PSR_MODE_HYP 0x1a 373#define PSR_MODE_UND 0x1b 374#define PSR_MODE_SYS 0x1f 375 376/* 64 bit modes */ 377#define PSR_MODE_BIT 0x10 /* Set iff AArch32 */ 378#define PSR_MODE_EL3h 0x0d 379#define PSR_MODE_EL3t 0x0c 380#define PSR_MODE_EL2h 0x09 381#define PSR_MODE_EL2t 0x08 382#define PSR_MODE_EL1h 0x05 383#define PSR_MODE_EL1t 0x04 384#define PSR_MODE_EL0t 0x00 385 386#define PSR_GUEST32_INIT (PSR_ABT_MASK|PSR_FIQ_MASK|PSR_IRQ_MASK|PSR_MODE_SVC) 387#define PSR_GUEST64_INIT (PSR_ABT_MASK|PSR_FIQ_MASK|PSR_IRQ_MASK|PSR_MODE_EL1h) 388 389#define SCTLR_GUEST_INIT xen_mk_ullong(0x00c50078) 390 391/* 392 * Virtual machine platform (memory layout, interrupts) 393 * 394 * These are defined for consistency between the tools and the 395 * hypervisor. Guests must not rely on these hardcoded values but 396 * should instead use the FDT. 397 */ 398 399/* Physical Address Space */ 400 401/* 402 * vGIC mappings: Only one set of mapping is used by the guest. 403 * Therefore they can overlap. 404 */ 405 406/* vGIC v2 mappings */ 407#define GUEST_GICD_BASE xen_mk_ullong(0x03001000) 408#define GUEST_GICD_SIZE xen_mk_ullong(0x00001000) 409#define GUEST_GICC_BASE xen_mk_ullong(0x03002000) 410#define GUEST_GICC_SIZE xen_mk_ullong(0x00002000) 411 412/* vGIC v3 mappings */ 413#define GUEST_GICV3_GICD_BASE xen_mk_ullong(0x03001000) 414#define GUEST_GICV3_GICD_SIZE xen_mk_ullong(0x00010000) 415 416#define GUEST_GICV3_RDIST_REGIONS 1 417 418#define GUEST_GICV3_GICR0_BASE xen_mk_ullong(0x03020000) /* vCPU0..127 */ 419#define GUEST_GICV3_GICR0_SIZE xen_mk_ullong(0x01000000) 420 421/* 422 * 256 MB is reserved for VPCI configuration space based on calculation 423 * 256 buses x 32 devices x 8 functions x 4 KB = 256 MB 424 */ 425#define GUEST_VPCI_ECAM_BASE xen_mk_ullong(0x10000000) 426#define GUEST_VPCI_ECAM_SIZE xen_mk_ullong(0x10000000) 427 428/* ACPI tables physical address */ 429#define GUEST_ACPI_BASE xen_mk_ullong(0x20000000) 430#define GUEST_ACPI_SIZE xen_mk_ullong(0x02000000) 431 432/* PL011 mappings */ 433#define GUEST_PL011_BASE xen_mk_ullong(0x22000000) 434#define GUEST_PL011_SIZE xen_mk_ullong(0x00001000) 435 436/* Guest PCI-PCIe memory space where config space and BAR will be available.*/ 437#define GUEST_VPCI_ADDR_TYPE_MEM xen_mk_ullong(0x02000000) 438#define GUEST_VPCI_MEM_ADDR xen_mk_ullong(0x23000000) 439#define GUEST_VPCI_MEM_SIZE xen_mk_ullong(0x10000000) 440 441/* 442 * 16MB == 4096 pages reserved for guest to use as a region to map its 443 * grant table in. 444 */ 445#define GUEST_GNTTAB_BASE xen_mk_ullong(0x38000000) 446#define GUEST_GNTTAB_SIZE xen_mk_ullong(0x01000000) 447 448#define GUEST_MAGIC_BASE xen_mk_ullong(0x39000000) 449#define GUEST_MAGIC_SIZE xen_mk_ullong(0x01000000) 450 451#define GUEST_RAM_BANKS 2 452 453/* 454 * The way to find the extended regions (to be exposed to the guest as unused 455 * address space) relies on the fact that the regions reserved for the RAM 456 * below are big enough to also accommodate such regions. 457 */ 458#define GUEST_RAM0_BASE xen_mk_ullong(0x40000000) /* 3GB of low RAM @ 1GB */ 459#define GUEST_RAM0_SIZE xen_mk_ullong(0xc0000000) 460 461/* 4GB @ 4GB Prefetch Memory for VPCI */ 462#define GUEST_VPCI_ADDR_TYPE_PREFETCH_MEM xen_mk_ullong(0x42000000) 463#define GUEST_VPCI_PREFETCH_MEM_ADDR xen_mk_ullong(0x100000000) 464#define GUEST_VPCI_PREFETCH_MEM_SIZE xen_mk_ullong(0x100000000) 465 466#define GUEST_RAM1_BASE xen_mk_ullong(0x0200000000) /* 1016GB of RAM @ 8GB */ 467#define GUEST_RAM1_SIZE xen_mk_ullong(0xfe00000000) 468 469#define GUEST_RAM_BASE GUEST_RAM0_BASE /* Lowest RAM address */ 470/* Largest amount of actual RAM, not including holes */ 471#define GUEST_RAM_MAX (GUEST_RAM0_SIZE + GUEST_RAM1_SIZE) 472/* Suitable for e.g. const uint64_t ramfoo[] = GUEST_RAM_BANK_FOOS; */ 473#define GUEST_RAM_BANK_BASES { GUEST_RAM0_BASE, GUEST_RAM1_BASE } 474#define GUEST_RAM_BANK_SIZES { GUEST_RAM0_SIZE, GUEST_RAM1_SIZE } 475 476/* Current supported guest VCPUs */ 477#define GUEST_MAX_VCPUS 128 478 479/* Interrupts */ 480#define GUEST_TIMER_VIRT_PPI 27 481#define GUEST_TIMER_PHYS_S_PPI 29 482#define GUEST_TIMER_PHYS_NS_PPI 30 483#define GUEST_EVTCHN_PPI 31 484 485#define GUEST_VPL011_SPI 32 486 487/* PSCI functions */ 488#define PSCI_cpu_suspend 0 489#define PSCI_cpu_off 1 490#define PSCI_cpu_on 2 491#define PSCI_migrate 3 492 493#endif 494 495#ifndef __ASSEMBLY__ 496/* Stub definition of PMU structure */ 497typedef struct xen_pmu_arch { uint8_t dummy; } xen_pmu_arch_t; 498#endif 499 500#endif /* __XEN_PUBLIC_ARCH_ARM_H__ */ 501 502/* 503 * Local variables: 504 * mode: C 505 * c-file-style: "BSD" 506 * c-basic-offset: 4 507 * tab-width: 4 508 * indent-tabs-mode: nil 509 * End: 510 */ 511