1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19#include "qemu/osdep.h"
20#include "qemu/qemu-print.h"
21#include "qapi/error.h"
22#include "cpu.h"
23#include "migration/vmstate.h"
24#include "exec/exec-all.h"
25#include "hw/loader.h"
26#include "fpu/softfloat.h"
27
28static void rx_cpu_set_pc(CPUState *cs, vaddr value)
29{
30 RXCPU *cpu = RX_CPU(cs);
31
32 cpu->env.pc = value;
33}
34
35static vaddr rx_cpu_get_pc(CPUState *cs)
36{
37 RXCPU *cpu = RX_CPU(cs);
38
39 return cpu->env.pc;
40}
41
42static void rx_cpu_synchronize_from_tb(CPUState *cs,
43 const TranslationBlock *tb)
44{
45 RXCPU *cpu = RX_CPU(cs);
46
47 tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL));
48 cpu->env.pc = tb->pc;
49}
50
51static void rx_restore_state_to_opc(CPUState *cs,
52 const TranslationBlock *tb,
53 const uint64_t *data)
54{
55 RXCPU *cpu = RX_CPU(cs);
56
57 cpu->env.pc = data[0];
58}
59
60static bool rx_cpu_has_work(CPUState *cs)
61{
62 return cs->interrupt_request &
63 (CPU_INTERRUPT_HARD | CPU_INTERRUPT_FIR);
64}
65
66static void rx_cpu_reset_hold(Object *obj)
67{
68 RXCPU *cpu = RX_CPU(obj);
69 RXCPUClass *rcc = RX_CPU_GET_CLASS(cpu);
70 CPURXState *env = &cpu->env;
71 uint32_t *resetvec;
72
73 if (rcc->parent_phases.hold) {
74 rcc->parent_phases.hold(obj);
75 }
76
77 memset(env, 0, offsetof(CPURXState, end_reset_fields));
78
79 resetvec = rom_ptr(0xfffffffc, 4);
80 if (resetvec) {
81
82 env->pc = ldl_p(resetvec);
83 }
84 rx_cpu_unpack_psw(env, 0, 1);
85 env->regs[0] = env->isp = env->usp = 0;
86 env->fpsw = 0;
87 set_flush_to_zero(1, &env->fp_status);
88 set_flush_inputs_to_zero(1, &env->fp_status);
89}
90
91static void rx_cpu_list_entry(gpointer data, gpointer user_data)
92{
93 ObjectClass *oc = data;
94
95 qemu_printf(" %s\n", object_class_get_name(oc));
96}
97
98void rx_cpu_list(void)
99{
100 GSList *list;
101 list = object_class_get_list_sorted(TYPE_RX_CPU, false);
102 qemu_printf("Available CPUs:\n");
103 g_slist_foreach(list, rx_cpu_list_entry, NULL);
104 g_slist_free(list);
105}
106
107static ObjectClass *rx_cpu_class_by_name(const char *cpu_model)
108{
109 ObjectClass *oc;
110 char *typename;
111
112 oc = object_class_by_name(cpu_model);
113 if (oc != NULL && object_class_dynamic_cast(oc, TYPE_RX_CPU) != NULL &&
114 !object_class_is_abstract(oc)) {
115 return oc;
116 }
117 typename = g_strdup_printf(RX_CPU_TYPE_NAME("%s"), cpu_model);
118 oc = object_class_by_name(typename);
119 g_free(typename);
120 if (oc != NULL && object_class_is_abstract(oc)) {
121 oc = NULL;
122 }
123
124 return oc;
125}
126
127static void rx_cpu_realize(DeviceState *dev, Error **errp)
128{
129 CPUState *cs = CPU(dev);
130 RXCPUClass *rcc = RX_CPU_GET_CLASS(dev);
131 Error *local_err = NULL;
132
133 cpu_exec_realizefn(cs, &local_err);
134 if (local_err != NULL) {
135 error_propagate(errp, local_err);
136 return;
137 }
138
139 qemu_init_vcpu(cs);
140 cpu_reset(cs);
141
142 rcc->parent_realize(dev, errp);
143}
144
145static void rx_cpu_set_irq(void *opaque, int no, int request)
146{
147 RXCPU *cpu = opaque;
148 CPUState *cs = CPU(cpu);
149 int irq = request & 0xff;
150
151 static const int mask[] = {
152 [RX_CPU_IRQ] = CPU_INTERRUPT_HARD,
153 [RX_CPU_FIR] = CPU_INTERRUPT_FIR,
154 };
155 if (irq) {
156 cpu->env.req_irq = irq;
157 cpu->env.req_ipl = (request >> 8) & 0x0f;
158 cpu_interrupt(cs, mask[no]);
159 } else {
160 cpu_reset_interrupt(cs, mask[no]);
161 }
162}
163
164static void rx_cpu_disas_set_info(CPUState *cpu, disassemble_info *info)
165{
166 info->mach = bfd_mach_rx;
167 info->print_insn = print_insn_rx;
168}
169
170static bool rx_cpu_tlb_fill(CPUState *cs, vaddr addr, int size,
171 MMUAccessType access_type, int mmu_idx,
172 bool probe, uintptr_t retaddr)
173{
174 uint32_t address, physical, prot;
175
176
177 address = physical = addr & TARGET_PAGE_MASK;
178 prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
179 tlb_set_page(cs, address, physical, prot, mmu_idx, TARGET_PAGE_SIZE);
180 return true;
181}
182
183static void rx_cpu_init(Object *obj)
184{
185 CPUState *cs = CPU(obj);
186 RXCPU *cpu = RX_CPU(obj);
187 CPURXState *env = &cpu->env;
188
189 cpu_set_cpustate_pointers(cpu);
190 cs->env_ptr = env;
191 qdev_init_gpio_in(DEVICE(cpu), rx_cpu_set_irq, 2);
192}
193
194#ifndef CONFIG_USER_ONLY
195#include "hw/core/sysemu-cpu-ops.h"
196
197static const struct SysemuCPUOps rx_sysemu_ops = {
198 .get_phys_page_debug = rx_cpu_get_phys_page_debug,
199};
200#endif
201
202#include "hw/core/tcg-cpu-ops.h"
203
204static const struct TCGCPUOps rx_tcg_ops = {
205 .initialize = rx_translate_init,
206 .synchronize_from_tb = rx_cpu_synchronize_from_tb,
207 .restore_state_to_opc = rx_restore_state_to_opc,
208 .tlb_fill = rx_cpu_tlb_fill,
209
210#ifndef CONFIG_USER_ONLY
211 .cpu_exec_interrupt = rx_cpu_exec_interrupt,
212 .do_interrupt = rx_cpu_do_interrupt,
213#endif
214};
215
216static void rx_cpu_class_init(ObjectClass *klass, void *data)
217{
218 DeviceClass *dc = DEVICE_CLASS(klass);
219 CPUClass *cc = CPU_CLASS(klass);
220 RXCPUClass *rcc = RX_CPU_CLASS(klass);
221 ResettableClass *rc = RESETTABLE_CLASS(klass);
222
223 device_class_set_parent_realize(dc, rx_cpu_realize,
224 &rcc->parent_realize);
225 resettable_class_set_parent_phases(rc, NULL, rx_cpu_reset_hold, NULL,
226 &rcc->parent_phases);
227
228 cc->class_by_name = rx_cpu_class_by_name;
229 cc->has_work = rx_cpu_has_work;
230 cc->dump_state = rx_cpu_dump_state;
231 cc->set_pc = rx_cpu_set_pc;
232 cc->get_pc = rx_cpu_get_pc;
233
234#ifndef CONFIG_USER_ONLY
235 cc->sysemu_ops = &rx_sysemu_ops;
236#endif
237 cc->gdb_read_register = rx_cpu_gdb_read_register;
238 cc->gdb_write_register = rx_cpu_gdb_write_register;
239 cc->disas_set_info = rx_cpu_disas_set_info;
240
241 cc->gdb_num_core_regs = 26;
242 cc->gdb_core_xml_file = "rx-core.xml";
243 cc->tcg_ops = &rx_tcg_ops;
244}
245
246static const TypeInfo rx_cpu_info = {
247 .name = TYPE_RX_CPU,
248 .parent = TYPE_CPU,
249 .instance_size = sizeof(RXCPU),
250 .instance_init = rx_cpu_init,
251 .abstract = true,
252 .class_size = sizeof(RXCPUClass),
253 .class_init = rx_cpu_class_init,
254};
255
256static const TypeInfo rx62n_rx_cpu_info = {
257 .name = TYPE_RX62N_CPU,
258 .parent = TYPE_RX_CPU,
259};
260
261static void rx_cpu_register_types(void)
262{
263 type_register_static(&rx_cpu_info);
264 type_register_static(&rx62n_rx_cpu_info);
265}
266
267type_init(rx_cpu_register_types)
268
