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25#include "qemu/osdep.h"
26#include "qemu/units.h"
27#include "hw/net/mii.h"
28#include "hw/pci/pci_device.h"
29#include "net/eth.h"
30#include "net/net.h"
31
32#include "e1000_common.h"
33#include "e1000x_common.h"
34
35#include "trace.h"
36
37bool e1000x_rx_ready(PCIDevice *d, uint32_t *mac)
38{
39 bool link_up = mac[STATUS] & E1000_STATUS_LU;
40 bool rx_enabled = mac[RCTL] & E1000_RCTL_EN;
41 bool pci_master = d->config[PCI_COMMAND] & PCI_COMMAND_MASTER;
42
43 if (!link_up || !rx_enabled || !pci_master) {
44 trace_e1000x_rx_can_recv_disabled(link_up, rx_enabled, pci_master);
45 return false;
46 }
47
48 return true;
49}
50
51bool e1000x_is_vlan_packet(const void *buf, uint16_t vet)
52{
53 uint16_t eth_proto = lduw_be_p(&PKT_GET_ETH_HDR(buf)->h_proto);
54 bool res = (eth_proto == vet);
55
56 trace_e1000x_vlan_is_vlan_pkt(res, eth_proto, vet);
57
58 return res;
59}
60
61bool e1000x_rx_group_filter(uint32_t *mac, const uint8_t *buf)
62{
63 static const int mta_shift[] = { 4, 3, 2, 0 };
64 uint32_t f, ra[2], *rp, rctl = mac[RCTL];
65
66 for (rp = mac + RA; rp < mac + RA + 32; rp += 2) {
67 if (!(rp[1] & E1000_RAH_AV)) {
68 continue;
69 }
70 ra[0] = cpu_to_le32(rp[0]);
71 ra[1] = cpu_to_le32(rp[1]);
72 if (!memcmp(buf, (uint8_t *)ra, ETH_ALEN)) {
73 trace_e1000x_rx_flt_ucast_match((int)(rp - mac - RA) / 2,
74 MAC_ARG(buf));
75 return true;
76 }
77 }
78 trace_e1000x_rx_flt_ucast_mismatch(MAC_ARG(buf));
79
80 f = mta_shift[(rctl >> E1000_RCTL_MO_SHIFT) & 3];
81 f = (((buf[5] << 8) | buf[4]) >> f) & 0xfff;
82 if (mac[MTA + (f >> 5)] & (1 << (f & 0x1f))) {
83 return true;
84 }
85
86 trace_e1000x_rx_flt_inexact_mismatch(MAC_ARG(buf),
87 (rctl >> E1000_RCTL_MO_SHIFT) & 3,
88 f >> 5,
89 mac[MTA + (f >> 5)]);
90
91 return false;
92}
93
94bool e1000x_hw_rx_enabled(uint32_t *mac)
95{
96 if (!(mac[STATUS] & E1000_STATUS_LU)) {
97 trace_e1000x_rx_link_down(mac[STATUS]);
98 return false;
99 }
100
101 if (!(mac[RCTL] & E1000_RCTL_EN)) {
102 trace_e1000x_rx_disabled(mac[RCTL]);
103 return false;
104 }
105
106 return true;
107}
108
109bool e1000x_is_oversized(uint32_t *mac, size_t size)
110{
111
112
113 static const int maximum_ethernet_vlan_size = 1522;
114
115
116 static const int maximum_ethernet_lpe_size = 16 * KiB;
117
118 if ((size > maximum_ethernet_lpe_size ||
119 (size > maximum_ethernet_vlan_size
120 && !(mac[RCTL] & E1000_RCTL_LPE)))
121 && !(mac[RCTL] & E1000_RCTL_SBP)) {
122 e1000x_inc_reg_if_not_full(mac, ROC);
123 trace_e1000x_rx_oversized(size);
124 return true;
125 }
126
127 return false;
128}
129
130void e1000x_restart_autoneg(uint32_t *mac, uint16_t *phy, QEMUTimer *timer)
131{
132 e1000x_update_regs_on_link_down(mac, phy);
133 trace_e1000x_link_negotiation_start();
134 timer_mod(timer, qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + 500);
135}
136
137void e1000x_reset_mac_addr(NICState *nic, uint32_t *mac_regs,
138 uint8_t *mac_addr)
139{
140 int i;
141
142 mac_regs[RA] = 0;
143 mac_regs[RA + 1] = E1000_RAH_AV;
144 for (i = 0; i < 4; i++) {
145 mac_regs[RA] |= mac_addr[i] << (8 * i);
146 mac_regs[RA + 1] |=
147 (i < 2) ? mac_addr[i + 4] << (8 * i) : 0;
148 }
149
150 qemu_format_nic_info_str(qemu_get_queue(nic), mac_addr);
151 trace_e1000x_mac_indicate(MAC_ARG(mac_addr));
152}
153
154void e1000x_update_regs_on_autoneg_done(uint32_t *mac, uint16_t *phy)
155{
156 e1000x_update_regs_on_link_up(mac, phy);
157 phy[MII_ANLPAR] |= MII_ANLPAR_ACK;
158 phy[MII_BMSR] |= MII_BMSR_AN_COMP;
159 trace_e1000x_link_negotiation_done();
160}
161
162void
163e1000x_core_prepare_eeprom(uint16_t *eeprom,
164 const uint16_t *templ,
165 uint32_t templ_size,
166 uint16_t dev_id,
167 const uint8_t *macaddr)
168{
169 uint16_t checksum = 0;
170 int i;
171
172 memmove(eeprom, templ, templ_size);
173
174 for (i = 0; i < 3; i++) {
175 eeprom[i] = (macaddr[2 * i + 1] << 8) | macaddr[2 * i];
176 }
177
178 eeprom[11] = eeprom[13] = dev_id;
179
180 for (i = 0; i < EEPROM_CHECKSUM_REG; i++) {
181 checksum += eeprom[i];
182 }
183
184 checksum = (uint16_t) EEPROM_SUM - checksum;
185
186 eeprom[EEPROM_CHECKSUM_REG] = checksum;
187}
188
189uint32_t
190e1000x_rxbufsize(uint32_t rctl)
191{
192 rctl &= E1000_RCTL_BSEX | E1000_RCTL_SZ_16384 | E1000_RCTL_SZ_8192 |
193 E1000_RCTL_SZ_4096 | E1000_RCTL_SZ_2048 | E1000_RCTL_SZ_1024 |
194 E1000_RCTL_SZ_512 | E1000_RCTL_SZ_256;
195 switch (rctl) {
196 case E1000_RCTL_BSEX | E1000_RCTL_SZ_16384:
197 return 16384;
198 case E1000_RCTL_BSEX | E1000_RCTL_SZ_8192:
199 return 8192;
200 case E1000_RCTL_BSEX | E1000_RCTL_SZ_4096:
201 return 4096;
202 case E1000_RCTL_SZ_1024:
203 return 1024;
204 case E1000_RCTL_SZ_512:
205 return 512;
206 case E1000_RCTL_SZ_256:
207 return 256;
208 }
209 return 2048;
210}
211
212void
213e1000x_update_rx_total_stats(uint32_t *mac,
214 eth_pkt_types_e pkt_type,
215 size_t pkt_size,
216 size_t pkt_fcs_size)
217{
218 static const int PRCregs[6] = { PRC64, PRC127, PRC255, PRC511,
219 PRC1023, PRC1522 };
220
221 e1000x_increase_size_stats(mac, PRCregs, pkt_fcs_size);
222 e1000x_inc_reg_if_not_full(mac, TPR);
223 e1000x_inc_reg_if_not_full(mac, GPRC);
224
225
226
227
228
229 e1000x_grow_8reg_if_not_full(mac, TORL, pkt_size + 4);
230 e1000x_grow_8reg_if_not_full(mac, GORCL, pkt_size + 4);
231
232 switch (pkt_type) {
233 case ETH_PKT_BCAST:
234 e1000x_inc_reg_if_not_full(mac, BPRC);
235 break;
236
237 case ETH_PKT_MCAST:
238 e1000x_inc_reg_if_not_full(mac, MPRC);
239 break;
240
241 default:
242 break;
243 }
244}
245
246void
247e1000x_increase_size_stats(uint32_t *mac, const int *size_regs, int size)
248{
249 if (size > 1023) {
250 e1000x_inc_reg_if_not_full(mac, size_regs[5]);
251 } else if (size > 511) {
252 e1000x_inc_reg_if_not_full(mac, size_regs[4]);
253 } else if (size > 255) {
254 e1000x_inc_reg_if_not_full(mac, size_regs[3]);
255 } else if (size > 127) {
256 e1000x_inc_reg_if_not_full(mac, size_regs[2]);
257 } else if (size > 64) {
258 e1000x_inc_reg_if_not_full(mac, size_regs[1]);
259 } else if (size == 64) {
260 e1000x_inc_reg_if_not_full(mac, size_regs[0]);
261 }
262}
263
264void
265e1000x_read_tx_ctx_descr(struct e1000_context_desc *d,
266 e1000x_txd_props *props)
267{
268 uint32_t op = le32_to_cpu(d->cmd_and_length);
269
270 props->ipcss = d->lower_setup.ip_fields.ipcss;
271 props->ipcso = d->lower_setup.ip_fields.ipcso;
272 props->ipcse = le16_to_cpu(d->lower_setup.ip_fields.ipcse);
273 props->tucss = d->upper_setup.tcp_fields.tucss;
274 props->tucso = d->upper_setup.tcp_fields.tucso;
275 props->tucse = le16_to_cpu(d->upper_setup.tcp_fields.tucse);
276 props->paylen = op & 0xfffff;
277 props->hdr_len = d->tcp_seg_setup.fields.hdr_len;
278 props->mss = le16_to_cpu(d->tcp_seg_setup.fields.mss);
279 props->ip = (op & E1000_TXD_CMD_IP) ? 1 : 0;
280 props->tcp = (op & E1000_TXD_CMD_TCP) ? 1 : 0;
281 props->tse = (op & E1000_TXD_CMD_TSE) ? 1 : 0;
282}
283
284void e1000x_timestamp(uint32_t *mac, int64_t timadj, size_t lo, size_t hi)
285{
286 int64_t ns = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
287 uint32_t timinca = mac[TIMINCA];
288 uint32_t incvalue = timinca & E1000_TIMINCA_INCVALUE_MASK;
289 uint32_t incperiod = MAX(timinca >> E1000_TIMINCA_INCPERIOD_SHIFT, 1);
290 int64_t timestamp = timadj + muldiv64(ns, incvalue, incperiod * 16);
291
292 mac[lo] = timestamp & 0xffffffff;
293 mac[hi] = timestamp >> 32;
294}
295
296void e1000x_set_timinca(uint32_t *mac, int64_t *timadj, uint32_t val)
297{
298 int64_t ns = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
299 uint32_t old_val = mac[TIMINCA];
300 uint32_t old_incvalue = old_val & E1000_TIMINCA_INCVALUE_MASK;
301 uint32_t old_incperiod = MAX(old_val >> E1000_TIMINCA_INCPERIOD_SHIFT, 1);
302 uint32_t incvalue = val & E1000_TIMINCA_INCVALUE_MASK;
303 uint32_t incperiod = MAX(val >> E1000_TIMINCA_INCPERIOD_SHIFT, 1);
304
305 mac[TIMINCA] = val;
306 *timadj += (muldiv64(ns, incvalue, incperiod) - muldiv64(ns, old_incvalue, old_incperiod)) / 16;
307}
308
