LXR qemu/target/s390x/cpu.h

   1/*
   2 * S/390 virtual CPU header
   3 *
   4 * For details on the s390x architecture and used definitions (e.g.,
   5 * PSW, PER and DAT (Dynamic Address Translation)), please refer to
   6 * the "z/Architecture Principles of Operations" - a.k.a. PoP.
   7 *
   8 *  Copyright (c) 2009 Ulrich Hecht
   9 *  Copyright IBM Corp. 2012, 2018
  10 *
  11 * This program is free software; you can redistribute it and/or modify
  12 * it under the terms of the GNU General Public License as published by
  13 * the Free Software Foundation; either version 2 of the License, or
  14 * (at your option) any later version.
  15 *
  16 * This program is distributed in the hope that it will be useful,
  17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  19 * General Public License for more details.
  20 *
  21 * You should have received a copy of the GNU General Public License
  22 * along with this program; if not, see <http://www.gnu.org/licenses/>.
  23 */
  24
  25#ifndef S390X_CPU_H
  26#define S390X_CPU_H
  27
  28#include "cpu-qom.h"
  29#include "cpu_models.h"
  30#include "exec/cpu-defs.h"
  31#include "qemu/cpu-float.h"
  32#include "tcg/tcg_s390x.h"
  33
  34#define ELF_MACHINE_UNAME "S390X"
  35
  36/* The z/Architecture has a strong memory model with some store-after-load re-ordering */
  37#define TCG_GUEST_DEFAULT_MO      (TCG_MO_ALL & ~TCG_MO_ST_LD)
  38
  39#define TARGET_INSN_START_EXTRA_WORDS 2
  40
  41#define MMU_USER_IDX 0
  42
  43#define S390_MAX_CPUS 248
  44
  45#ifndef CONFIG_KVM
  46#define S390_ADAPTER_SUPPRESSIBLE 0x01
  47#else
  48#define S390_ADAPTER_SUPPRESSIBLE KVM_S390_ADAPTER_SUPPRESSIBLE
  49#endif
  50
  51typedef struct PSW {
  52    uint64_t mask;
  53    uint64_t addr;
  54} PSW;
  55
  56struct CPUArchState {
  57    uint64_t regs[16];     /* GP registers */
  58    /*
  59     * The floating point registers are part of the vector registers.
  60     * vregs[0][0] -> vregs[15][0] are 16 floating point registers
  61     */
  62    uint64_t vregs[32][2] QEMU_ALIGNED(16);  /* vector registers */
  63    uint32_t aregs[16];    /* access registers */
  64    uint64_t gscb[4];      /* guarded storage control */
  65    uint64_t etoken;       /* etoken */
  66    uint64_t etoken_extension; /* etoken extension */
  67
  68    uint64_t diag318_info;
  69
  70    /* Fields up to this point are not cleared by initial CPU reset */
  71    struct {} start_initial_reset_fields;
  72
  73    uint32_t fpc;          /* floating-point control register */
  74    uint32_t cc_op;
  75    bool bpbc;             /* branch prediction blocking */
  76
  77    float_status fpu_status; /* passed to softfloat lib */
  78
  79    /* The low part of a 128-bit return, or remainder of a divide.  */
  80    uint64_t retxl;
  81
  82    PSW psw;
  83
  84    S390CrashReason crash_reason;
  85
  86    uint64_t cc_src;
  87    uint64_t cc_dst;
  88    uint64_t cc_vr;
  89
  90    uint64_t ex_value;
  91    uint64_t ex_target;
  92
  93    uint64_t __excp_addr;
  94    uint64_t psa;
  95
  96    uint32_t int_pgm_code;
  97    uint32_t int_pgm_ilen;
  98
  99    uint32_t int_svc_code;
 100    uint32_t int_svc_ilen;
 101
 102    uint64_t per_address;
 103    uint16_t per_perc_atmid;
 104
 105    uint64_t cregs[16]; /* control registers */
 106
 107    uint64_t ckc;
 108    uint64_t cputm;
 109    uint32_t todpr;
 110
 111    uint64_t pfault_token;
 112    uint64_t pfault_compare;
 113    uint64_t pfault_select;
 114
 115    uint64_t gbea;
 116    uint64_t pp;
 117
 118    /* Fields up to this point are not cleared by normal CPU reset */
 119    struct {} start_normal_reset_fields;
 120    uint8_t riccb[64];     /* runtime instrumentation control */
 121
 122    int pending_int;
 123    uint16_t external_call_addr;
 124    DECLARE_BITMAP(emergency_signals, S390_MAX_CPUS);
 125
 126#if !defined(CONFIG_USER_ONLY)
 127    uint64_t tlb_fill_tec;   /* translation exception code during tlb_fill */
 128    int tlb_fill_exc;        /* exception number seen during tlb_fill */
 129#endif
 130
 131    /* Fields up to this point are cleared by a CPU reset */
 132    struct {} end_reset_fields;
 133
 134#if !defined(CONFIG_USER_ONLY)
 135    uint32_t core_id; /* PoP "CPU address", same as cpu_index */
 136    uint64_t cpuid;
 137#endif
 138
 139    QEMUTimer *tod_timer;
 140
 141    QEMUTimer *cpu_timer;
 142
 143    /*
 144     * The cpu state represents the logical state of a cpu. In contrast to other
 145     * architectures, there is a difference between a halt and a stop on s390.
 146     * If all cpus are either stopped (including check stop) or in the disabled
 147     * wait state, the vm can be shut down.
 148     * The acceptable cpu_state values are defined in the CpuInfoS390State
 149     * enum.
 150     */
 151    uint8_t cpu_state;
 152
 153    /* currently processed sigp order */
 154    uint8_t sigp_order;
 155
 156};
 157
 158static inline uint64_t *get_freg(CPUS390XState *cs, int nr)
 159{
 160    return &cs->vregs[nr][0];
 161}
 162
 163/**
 164 * S390CPU:
 165 * @env: #CPUS390XState.
 166 *
 167 * An S/390 CPU.
 168 */
 169struct ArchCPU {
 170    /*< private >*/
 171    CPUState parent_obj;
 172    /*< public >*/
 173
 174    CPUNegativeOffsetState neg;
 175    CPUS390XState env;
 176    S390CPUModel *model;
 177    /* needed for live migration */
 178    void *irqstate;
 179    uint32_t irqstate_saved_size;
 180};
 181
 182
 183#ifndef CONFIG_USER_ONLY
 184extern const VMStateDescription vmstate_s390_cpu;
 185#endif
 186
 187/* distinguish between 24 bit and 31 bit addressing */
 188#define HIGH_ORDER_BIT 0x80000000
 189
 190/* Interrupt Codes */
 191/* Program Interrupts */
 192#define PGM_OPERATION                   0x0001
 193#define PGM_PRIVILEGED                  0x0002
 194#define PGM_EXECUTE                     0x0003
 195#define PGM_PROTECTION                  0x0004
 196#define PGM_ADDRESSING                  0x0005
 197#define PGM_SPECIFICATION               0x0006
 198#define PGM_DATA                        0x0007
 199#define PGM_FIXPT_OVERFLOW              0x0008
 200#define PGM_FIXPT_DIVIDE                0x0009
 201#define PGM_DEC_OVERFLOW                0x000a
 202#define PGM_DEC_DIVIDE                  0x000b
 203#define PGM_HFP_EXP_OVERFLOW            0x000c
 204#define PGM_HFP_EXP_UNDERFLOW           0x000d
 205#define PGM_HFP_SIGNIFICANCE            0x000e
 206#define PGM_HFP_DIVIDE                  0x000f
 207#define PGM_SEGMENT_TRANS               0x0010
 208#define PGM_PAGE_TRANS                  0x0011
 209#define PGM_TRANS_SPEC                  0x0012
 210#define PGM_SPECIAL_OP                  0x0013
 211#define PGM_OPERAND                     0x0015
 212#define PGM_TRACE_TABLE                 0x0016
 213#define PGM_VECTOR_PROCESSING           0x001b
 214#define PGM_SPACE_SWITCH                0x001c
 215#define PGM_HFP_SQRT                    0x001d
 216#define PGM_PC_TRANS_SPEC               0x001f
 217#define PGM_AFX_TRANS                   0x0020
 218#define PGM_ASX_TRANS                   0x0021
 219#define PGM_LX_TRANS                    0x0022
 220#define PGM_EX_TRANS                    0x0023
 221#define PGM_PRIM_AUTH                   0x0024
 222#define PGM_SEC_AUTH                    0x0025
 223#define PGM_ALET_SPEC                   0x0028
 224#define PGM_ALEN_SPEC                   0x0029
 225#define PGM_ALE_SEQ                     0x002a
 226#define PGM_ASTE_VALID                  0x002b
 227#define PGM_ASTE_SEQ                    0x002c
 228#define PGM_EXT_AUTH                    0x002d
 229#define PGM_STACK_FULL                  0x0030
 230#define PGM_STACK_EMPTY                 0x0031
 231#define PGM_STACK_SPEC                  0x0032
 232#define PGM_STACK_TYPE                  0x0033
 233#define PGM_STACK_OP                    0x0034
 234#define PGM_ASCE_TYPE                   0x0038
 235#define PGM_REG_FIRST_TRANS             0x0039
 236#define PGM_REG_SEC_TRANS               0x003a
 237#define PGM_REG_THIRD_TRANS             0x003b
 238#define PGM_MONITOR                     0x0040
 239#define PGM_PER                         0x0080
 240#define PGM_CRYPTO                      0x0119
 241
 242/* External Interrupts */
 243#define EXT_INTERRUPT_KEY               0x0040
 244#define EXT_CLOCK_COMP                  0x1004
 245#define EXT_CPU_TIMER                   0x1005
 246#define EXT_MALFUNCTION                 0x1200
 247#define EXT_EMERGENCY                   0x1201
 248#define EXT_EXTERNAL_CALL               0x1202
 249#define EXT_ETR                         0x1406
 250#define EXT_SERVICE                     0x2401
 251#define EXT_VIRTIO                      0x2603
 252
 253/* PSW defines */
 254#undef PSW_MASK_PER
 255#undef PSW_MASK_UNUSED_2
 256#undef PSW_MASK_UNUSED_3
 257#undef PSW_MASK_DAT
 258#undef PSW_MASK_IO
 259#undef PSW_MASK_EXT
 260#undef PSW_MASK_KEY
 261#undef PSW_SHIFT_KEY
 262#undef PSW_MASK_MCHECK
 263#undef PSW_MASK_WAIT
 264#undef PSW_MASK_PSTATE
 265#undef PSW_MASK_ASC
 266#undef PSW_SHIFT_ASC
 267#undef PSW_MASK_CC
 268#undef PSW_MASK_PM
 269#undef PSW_MASK_RI
 270#undef PSW_SHIFT_MASK_PM
 271#undef PSW_MASK_64
 272#undef PSW_MASK_32
 273#undef PSW_MASK_ESA_ADDR
 274
 275#define PSW_MASK_PER            0x4000000000000000ULL
 276#define PSW_MASK_UNUSED_2       0x2000000000000000ULL
 277#define PSW_MASK_UNUSED_3       0x1000000000000000ULL
 278#define PSW_MASK_DAT            0x0400000000000000ULL
 279#define PSW_MASK_IO             0x0200000000000000ULL
 280#define PSW_MASK_EXT            0x0100000000000000ULL
 281#define PSW_MASK_KEY            0x00F0000000000000ULL
 282#define PSW_SHIFT_KEY           52
 283#define PSW_MASK_SHORTPSW       0x0008000000000000ULL
 284#define PSW_MASK_MCHECK         0x0004000000000000ULL
 285#define PSW_MASK_WAIT           0x0002000000000000ULL
 286#define PSW_MASK_PSTATE         0x0001000000000000ULL
 287#define PSW_MASK_ASC            0x0000C00000000000ULL
 288#define PSW_SHIFT_ASC           46
 289#define PSW_MASK_CC             0x0000300000000000ULL
 290#define PSW_MASK_PM             0x00000F0000000000ULL
 291#define PSW_SHIFT_MASK_PM       40
 292#define PSW_MASK_RI             0x0000008000000000ULL
 293#define PSW_MASK_64             0x0000000100000000ULL
 294#define PSW_MASK_32             0x0000000080000000ULL
 295#define PSW_MASK_SHORT_ADDR     0x000000007fffffffULL
 296#define PSW_MASK_SHORT_CTRL     0xffffffff80000000ULL
 297#define PSW_MASK_RESERVED       0xb80800fe7fffffffULL
 298
 299#undef PSW_ASC_PRIMARY
 300#undef PSW_ASC_ACCREG
 301#undef PSW_ASC_SECONDARY
 302#undef PSW_ASC_HOME
 303
 304#define PSW_ASC_PRIMARY         0x0000000000000000ULL
 305#define PSW_ASC_ACCREG          0x0000400000000000ULL
 306#define PSW_ASC_SECONDARY       0x0000800000000000ULL
 307#define PSW_ASC_HOME            0x0000C00000000000ULL
 308
 309/* the address space values shifted */
 310#define AS_PRIMARY              0
 311#define AS_ACCREG               1
 312#define AS_SECONDARY            2
 313#define AS_HOME                 3
 314
 315/* tb flags */
 316
 317#define FLAG_MASK_PSW_SHIFT     31
 318#define FLAG_MASK_PER           (PSW_MASK_PER    >> FLAG_MASK_PSW_SHIFT)
 319#define FLAG_MASK_DAT           (PSW_MASK_DAT    >> FLAG_MASK_PSW_SHIFT)
 320#define FLAG_MASK_PSTATE        (PSW_MASK_PSTATE >> FLAG_MASK_PSW_SHIFT)
 321#define FLAG_MASK_ASC           (PSW_MASK_ASC    >> FLAG_MASK_PSW_SHIFT)
 322#define FLAG_MASK_64            (PSW_MASK_64     >> FLAG_MASK_PSW_SHIFT)
 323#define FLAG_MASK_32            (PSW_MASK_32     >> FLAG_MASK_PSW_SHIFT)
 324#define FLAG_MASK_PSW           (FLAG_MASK_PER | FLAG_MASK_DAT | FLAG_MASK_PSTATE \
 325                                | FLAG_MASK_ASC | FLAG_MASK_64 | FLAG_MASK_32)
 326
 327/* we'll use some unused PSW positions to store CR flags in tb flags */
 328#define FLAG_MASK_AFP           (PSW_MASK_UNUSED_2 >> FLAG_MASK_PSW_SHIFT)
 329#define FLAG_MASK_VECTOR        (PSW_MASK_UNUSED_3 >> FLAG_MASK_PSW_SHIFT)
 330
 331/* Control register 0 bits */
 332#define CR0_LOWPROT             0x0000000010000000ULL
 333#define CR0_SECONDARY           0x0000000004000000ULL
 334#define CR0_EDAT                0x0000000000800000ULL
 335#define CR0_AFP                 0x0000000000040000ULL
 336#define CR0_VECTOR              0x0000000000020000ULL
 337#define CR0_IEP                 0x0000000000100000ULL
 338#define CR0_EMERGENCY_SIGNAL_SC 0x0000000000004000ULL
 339#define CR0_EXTERNAL_CALL_SC    0x0000000000002000ULL
 340#define CR0_CKC_SC              0x0000000000000800ULL
 341#define CR0_CPU_TIMER_SC        0x0000000000000400ULL
 342#define CR0_SERVICE_SC          0x0000000000000200ULL
 343
 344/* Control register 14 bits */
 345#define CR14_CHANNEL_REPORT_SC  0x0000000010000000ULL
 346
 347/* MMU */
 348#define MMU_PRIMARY_IDX         0
 349#define MMU_SECONDARY_IDX       1
 350#define MMU_HOME_IDX            2
 351#define MMU_REAL_IDX            3
 352
 353static inline int cpu_mmu_index(CPUS390XState *env, bool ifetch)
 354{
 355#ifdef CONFIG_USER_ONLY
 356    return MMU_USER_IDX;
 357#else
 358    if (!(env->psw.mask & PSW_MASK_DAT)) {
 359        return MMU_REAL_IDX;
 360    }
 361
 362    if (ifetch) {
 363        if ((env->psw.mask & PSW_MASK_ASC) == PSW_ASC_HOME) {
 364            return MMU_HOME_IDX;
 365        }
 366        return MMU_PRIMARY_IDX;
 367    }
 368
 369    switch (env->psw.mask & PSW_MASK_ASC) {
 370    case PSW_ASC_PRIMARY:
 371        return MMU_PRIMARY_IDX;
 372    case PSW_ASC_SECONDARY:
 373        return MMU_SECONDARY_IDX;
 374    case PSW_ASC_HOME:
 375        return MMU_HOME_IDX;
 376    case PSW_ASC_ACCREG:
 377        /* Fallthrough: access register mode is not yet supported */
 378    default:
 379        abort();
 380    }
 381#endif
 382}
 383
 384static inline void cpu_get_tb_cpu_state(CPUS390XState* env, target_ulong *pc,
 385                                        target_ulong *cs_base, uint32_t *flags)
 386{
 387    if (env->psw.addr & 1) {
 388        /*
 389         * Instructions must be at even addresses.
 390         * This needs to be checked before address translation.
 391         */
 392        env->int_pgm_ilen = 2; /* see s390_cpu_tlb_fill() */
 393        tcg_s390_program_interrupt(env, PGM_SPECIFICATION, 0);
 394    }
 395    *pc = env->psw.addr;
 396    *cs_base = env->ex_value;
 397    *flags = (env->psw.mask >> FLAG_MASK_PSW_SHIFT) & FLAG_MASK_PSW;
 398    if (env->cregs[0] & CR0_AFP) {
 399        *flags |= FLAG_MASK_AFP;
 400    }
 401    if (env->cregs[0] & CR0_VECTOR) {
 402        *flags |= FLAG_MASK_VECTOR;
 403    }
 404}
 405
 406/* PER bits from control register 9 */
 407#define PER_CR9_EVENT_BRANCH           0x80000000
 408#define PER_CR9_EVENT_IFETCH           0x40000000
 409#define PER_CR9_EVENT_STORE            0x20000000
 410#define PER_CR9_EVENT_STORE_REAL       0x08000000
 411#define PER_CR9_EVENT_NULLIFICATION    0x01000000
 412#define PER_CR9_CONTROL_BRANCH_ADDRESS 0x00800000
 413#define PER_CR9_CONTROL_ALTERATION     0x00200000
 414
 415/* PER bits from the PER CODE/ATMID/AI in lowcore */
 416#define PER_CODE_EVENT_BRANCH          0x8000
 417#define PER_CODE_EVENT_IFETCH          0x4000
 418#define PER_CODE_EVENT_STORE           0x2000
 419#define PER_CODE_EVENT_STORE_REAL      0x0800
 420#define PER_CODE_EVENT_NULLIFICATION   0x0100
 421
 422#define EXCP_EXT 1 /* external interrupt */
 423#define EXCP_SVC 2 /* supervisor call (syscall) */
 424#define EXCP_PGM 3 /* program interruption */
 425#define EXCP_RESTART 4 /* restart interrupt */
 426#define EXCP_STOP 5 /* stop interrupt */
 427#define EXCP_IO  7 /* I/O interrupt */
 428#define EXCP_MCHK 8 /* machine check */
 429
 430#define INTERRUPT_EXT_CPU_TIMER          (1 << 3)
 431#define INTERRUPT_EXT_CLOCK_COMPARATOR   (1 << 4)
 432#define INTERRUPT_EXTERNAL_CALL          (1 << 5)
 433#define INTERRUPT_EMERGENCY_SIGNAL       (1 << 6)
 434#define INTERRUPT_RESTART                (1 << 7)
 435#define INTERRUPT_STOP                   (1 << 8)
 436
 437/* Program Status Word.  */
 438#define S390_PSWM_REGNUM 0
 439#define S390_PSWA_REGNUM 1
 440/* General Purpose Registers.  */
 441#define S390_R0_REGNUM 2
 442#define S390_R1_REGNUM 3
 443#define S390_R2_REGNUM 4
 444#define S390_R3_REGNUM 5
 445#define S390_R4_REGNUM 6
 446#define S390_R5_REGNUM 7
 447#define S390_R6_REGNUM 8
 448#define S390_R7_REGNUM 9
 449#define S390_R8_REGNUM 10
 450#define S390_R9_REGNUM 11
 451#define S390_R10_REGNUM 12
 452#define S390_R11_REGNUM 13
 453#define S390_R12_REGNUM 14
 454#define S390_R13_REGNUM 15
 455#define S390_R14_REGNUM 16
 456#define S390_R15_REGNUM 17
 457/* Total Core Registers. */
 458#define S390_NUM_CORE_REGS 18
 459
 460static inline void setcc(S390CPU *cpu, uint64_t cc)
 461{
 462    CPUS390XState *env = &cpu->env;
 463
 464    env->psw.mask &= ~(3ull << 44);
 465    env->psw.mask |= (cc & 3) << 44;
 466    env->cc_op = cc;
 467}
 468
 469/* STSI */
 470#define STSI_R0_FC_MASK         0x00000000f0000000ULL
 471#define STSI_R0_FC_CURRENT      0x0000000000000000ULL
 472#define STSI_R0_FC_LEVEL_1      0x0000000010000000ULL
 473#define STSI_R0_FC_LEVEL_2      0x0000000020000000ULL
 474#define STSI_R0_FC_LEVEL_3      0x0000000030000000ULL
 475#define STSI_R0_RESERVED_MASK   0x000000000fffff00ULL
 476#define STSI_R0_SEL1_MASK       0x00000000000000ffULL
 477#define STSI_R1_RESERVED_MASK   0x00000000ffff0000ULL
 478#define STSI_R1_SEL2_MASK       0x000000000000ffffULL
 479
 480/* Basic Machine Configuration */
 481typedef struct SysIB_111 {
 482    uint8_t  res1[32];
 483    uint8_t  manuf[16];
 484    uint8_t  type[4];
 485    uint8_t  res2[12];
 486    uint8_t  model[16];
 487    uint8_t  sequence[16];
 488    uint8_t  plant[4];
 489    uint8_t  res3[3996];
 490} SysIB_111;
 491QEMU_BUILD_BUG_ON(sizeof(SysIB_111) != 4096);
 492
 493/* Basic Machine CPU */
 494typedef struct SysIB_121 {
 495    uint8_t  res1[80];
 496    uint8_t  sequence[16];
 497    uint8_t  plant[4];
 498    uint8_t  res2[2];
 499    uint16_t cpu_addr;
 500    uint8_t  res3[3992];
 501} SysIB_121;
 502QEMU_BUILD_BUG_ON(sizeof(SysIB_121) != 4096);
 503
 504/* Basic Machine CPUs */
 505typedef struct SysIB_122 {
 506    uint8_t res1[32];
 507    uint32_t capability;
 508    uint16_t total_cpus;
 509    uint16_t conf_cpus;
 510    uint16_t standby_cpus;
 511    uint16_t reserved_cpus;
 512    uint16_t adjustments[2026];
 513} SysIB_122;
 514QEMU_BUILD_BUG_ON(sizeof(SysIB_122) != 4096);
 515
 516/* LPAR CPU */
 517typedef struct SysIB_221 {
 518    uint8_t  res1[80];
 519    uint8_t  sequence[16];
 520    uint8_t  plant[4];
 521    uint16_t cpu_id;
 522    uint16_t cpu_addr;
 523    uint8_t  res3[3992];
 524} SysIB_221;
 525QEMU_BUILD_BUG_ON(sizeof(SysIB_221) != 4096);
 526
 527/* LPAR CPUs */
 528typedef struct SysIB_222 {
 529    uint8_t  res1[32];
 530    uint16_t lpar_num;
 531    uint8_t  res2;
 532    uint8_t  lcpuc;
 533    uint16_t total_cpus;
 534    uint16_t conf_cpus;
 535    uint16_t standby_cpus;
 536    uint16_t reserved_cpus;
 537    uint8_t  name[8];
 538    uint32_t caf;
 539    uint8_t  res3[16];
 540    uint16_t dedicated_cpus;
 541    uint16_t shared_cpus;
 542    uint8_t  res4[4020];
 543} SysIB_222;
 544QEMU_BUILD_BUG_ON(sizeof(SysIB_222) != 4096);
 545
 546/* VM CPUs */
 547typedef struct SysIB_322 {
 548    uint8_t  res1[31];
 549    uint8_t  count;
 550    struct {
 551        uint8_t  res2[4];
 552        uint16_t total_cpus;
 553        uint16_t conf_cpus;
 554        uint16_t standby_cpus;
 555        uint16_t reserved_cpus;
 556        uint8_t  name[8];
 557        uint32_t caf;
 558        uint8_t  cpi[16];
 559        uint8_t res5[3];
 560        uint8_t ext_name_encoding;
 561        uint32_t res3;
 562        uint8_t uuid[16];
 563    } vm[8];
 564    uint8_t res4[1504];
 565    uint8_t ext_names[8][256];
 566} SysIB_322;
 567QEMU_BUILD_BUG_ON(sizeof(SysIB_322) != 4096);
 568
 569typedef union SysIB {
 570    SysIB_111 sysib_111;
 571    SysIB_121 sysib_121;
 572    SysIB_122 sysib_122;
 573    SysIB_221 sysib_221;
 574    SysIB_222 sysib_222;
 575    SysIB_322 sysib_322;
 576} SysIB;
 577QEMU_BUILD_BUG_ON(sizeof(SysIB) != 4096);
 578
 579/* MMU defines */
 580#define ASCE_ORIGIN           (~0xfffULL) /* segment table origin             */
 581#define ASCE_SUBSPACE         0x200       /* subspace group control           */
 582#define ASCE_PRIVATE_SPACE    0x100       /* private space control            */
 583#define ASCE_ALT_EVENT        0x80        /* storage alteration event control */
 584#define ASCE_SPACE_SWITCH     0x40        /* space switch event               */
 585#define ASCE_REAL_SPACE       0x20        /* real space control               */
 586#define ASCE_TYPE_MASK        0x0c        /* asce table type mask             */
 587#define ASCE_TYPE_REGION1     0x0c        /* region first table type          */
 588#define ASCE_TYPE_REGION2     0x08        /* region second table type         */
 589#define ASCE_TYPE_REGION3     0x04        /* region third table type          */
 590#define ASCE_TYPE_SEGMENT     0x00        /* segment table type               */
 591#define ASCE_TABLE_LENGTH     0x03        /* region table length              */
 592
 593#define REGION_ENTRY_ORIGIN         0xfffffffffffff000ULL
 594#define REGION_ENTRY_P              0x0000000000000200ULL
 595#define REGION_ENTRY_TF             0x00000000000000c0ULL
 596#define REGION_ENTRY_I              0x0000000000000020ULL
 597#define REGION_ENTRY_TT             0x000000000000000cULL
 598#define REGION_ENTRY_TL             0x0000000000000003ULL
 599
 600#define REGION_ENTRY_TT_REGION1     0x000000000000000cULL
 601#define REGION_ENTRY_TT_REGION2     0x0000000000000008ULL
 602#define REGION_ENTRY_TT_REGION3     0x0000000000000004ULL
 603
 604#define REGION3_ENTRY_RFAA          0xffffffff80000000ULL
 605#define REGION3_ENTRY_AV            0x0000000000010000ULL
 606#define REGION3_ENTRY_ACC           0x000000000000f000ULL
 607#define REGION3_ENTRY_F             0x0000000000000800ULL
 608#define REGION3_ENTRY_FC            0x0000000000000400ULL
 609#define REGION3_ENTRY_IEP           0x0000000000000100ULL
 610#define REGION3_ENTRY_CR            0x0000000000000010ULL
 611
 612#define SEGMENT_ENTRY_ORIGIN        0xfffffffffffff800ULL
 613#define SEGMENT_ENTRY_SFAA          0xfffffffffff00000ULL
 614#define SEGMENT_ENTRY_AV            0x0000000000010000ULL
 615#define SEGMENT_ENTRY_ACC           0x000000000000f000ULL
 616#define SEGMENT_ENTRY_F             0x0000000000000800ULL
 617#define SEGMENT_ENTRY_FC            0x0000000000000400ULL
 618#define SEGMENT_ENTRY_P             0x0000000000000200ULL
 619#define SEGMENT_ENTRY_IEP           0x0000000000000100ULL
 620#define SEGMENT_ENTRY_I             0x0000000000000020ULL
 621#define SEGMENT_ENTRY_CS            0x0000000000000010ULL
 622#define SEGMENT_ENTRY_TT            0x000000000000000cULL
 623
 624#define SEGMENT_ENTRY_TT_SEGMENT    0x0000000000000000ULL
 625
 626#define PAGE_ENTRY_0                0x0000000000000800ULL
 627#define PAGE_ENTRY_I                0x0000000000000400ULL
 628#define PAGE_ENTRY_P                0x0000000000000200ULL
 629#define PAGE_ENTRY_IEP              0x0000000000000100ULL
 630
 631#define VADDR_REGION1_TX_MASK       0xffe0000000000000ULL
 632#define VADDR_REGION2_TX_MASK       0x001ffc0000000000ULL
 633#define VADDR_REGION3_TX_MASK       0x000003ff80000000ULL
 634#define VADDR_SEGMENT_TX_MASK       0x000000007ff00000ULL
 635#define VADDR_PAGE_TX_MASK          0x00000000000ff000ULL
 636
 637#define VADDR_REGION1_TX(vaddr)     (((vaddr) & VADDR_REGION1_TX_MASK) >> 53)
 638#define VADDR_REGION2_TX(vaddr)     (((vaddr) & VADDR_REGION2_TX_MASK) >> 42)
 639#define VADDR_REGION3_TX(vaddr)     (((vaddr) & VADDR_REGION3_TX_MASK) >> 31)
 640#define VADDR_SEGMENT_TX(vaddr)     (((vaddr) & VADDR_SEGMENT_TX_MASK) >> 20)
 641#define VADDR_PAGE_TX(vaddr)        (((vaddr) & VADDR_PAGE_TX_MASK) >> 12)
 642
 643#define VADDR_REGION1_TL(vaddr)     (((vaddr) & 0xc000000000000000ULL) >> 62)
 644#define VADDR_REGION2_TL(vaddr)     (((vaddr) & 0x0018000000000000ULL) >> 51)
 645#define VADDR_REGION3_TL(vaddr)     (((vaddr) & 0x0000030000000000ULL) >> 40)
 646#define VADDR_SEGMENT_TL(vaddr)     (((vaddr) & 0x0000000060000000ULL) >> 29)
 647
 648#define SK_C                    (0x1 << 1)
 649#define SK_R                    (0x1 << 2)
 650#define SK_F                    (0x1 << 3)
 651#define SK_ACC_MASK             (0xf << 4)
 652
 653/* SIGP order codes */
 654#define SIGP_SENSE             0x01
 655#define SIGP_EXTERNAL_CALL     0x02
 656#define SIGP_EMERGENCY         0x03
 657#define SIGP_START             0x04
 658#define SIGP_STOP              0x05
 659#define SIGP_RESTART           0x06
 660#define SIGP_STOP_STORE_STATUS 0x09
 661#define SIGP_INITIAL_CPU_RESET 0x0b
 662#define SIGP_CPU_RESET         0x0c
 663#define SIGP_SET_PREFIX        0x0d
 664#define SIGP_STORE_STATUS_ADDR 0x0e
 665#define SIGP_SET_ARCH          0x12
 666#define SIGP_COND_EMERGENCY    0x13
 667#define SIGP_SENSE_RUNNING     0x15
 668#define SIGP_STORE_ADTL_STATUS 0x17
 669
 670/* SIGP condition codes */
 671#define SIGP_CC_ORDER_CODE_ACCEPTED 0
 672#define SIGP_CC_STATUS_STORED       1
 673#define SIGP_CC_BUSY                2
 674#define SIGP_CC_NOT_OPERATIONAL     3
 675
 676/* SIGP status bits */
 677#define SIGP_STAT_EQUIPMENT_CHECK   0x80000000UL
 678#define SIGP_STAT_NOT_RUNNING       0x00000400UL
 679#define SIGP_STAT_INCORRECT_STATE   0x00000200UL
 680#define SIGP_STAT_INVALID_PARAMETER 0x00000100UL
 681#define SIGP_STAT_EXT_CALL_PENDING  0x00000080UL
 682#define SIGP_STAT_STOPPED           0x00000040UL
 683#define SIGP_STAT_OPERATOR_INTERV   0x00000020UL
 684#define SIGP_STAT_CHECK_STOP        0x00000010UL
 685#define SIGP_STAT_INOPERATIVE       0x00000004UL
 686#define SIGP_STAT_INVALID_ORDER     0x00000002UL
 687#define SIGP_STAT_RECEIVER_CHECK    0x00000001UL
 688
 689/* SIGP order code mask corresponding to bit positions 56-63 */
 690#define SIGP_ORDER_MASK 0x000000ff
 691
 692/* machine check interruption code */
 693
 694/* subclasses */
 695#define MCIC_SC_SD 0x8000000000000000ULL
 696#define MCIC_SC_PD 0x4000000000000000ULL
 697#define MCIC_SC_SR 0x2000000000000000ULL
 698#define MCIC_SC_CD 0x0800000000000000ULL
 699#define MCIC_SC_ED 0x0400000000000000ULL
 700#define MCIC_SC_DG 0x0100000000000000ULL
 701#define MCIC_SC_W  0x0080000000000000ULL
 702#define MCIC_SC_CP 0x0040000000000000ULL
 703#define MCIC_SC_SP 0x0020000000000000ULL
 704#define MCIC_SC_CK 0x0010000000000000ULL
 705
 706/* subclass modifiers */
 707#define MCIC_SCM_B  0x0002000000000000ULL
 708#define MCIC_SCM_DA 0x0000000020000000ULL
 709#define MCIC_SCM_AP 0x0000000000080000ULL
 710
 711/* storage errors */
 712#define MCIC_SE_SE 0x0000800000000000ULL
 713#define MCIC_SE_SC 0x0000400000000000ULL
 714#define MCIC_SE_KE 0x0000200000000000ULL
 715#define MCIC_SE_DS 0x0000100000000000ULL
 716#define MCIC_SE_IE 0x0000000080000000ULL
 717
 718/* validity bits */
 719#define MCIC_VB_WP 0x0000080000000000ULL
 720#define MCIC_VB_MS 0x0000040000000000ULL
 721#define MCIC_VB_PM 0x0000020000000000ULL
 722#define MCIC_VB_IA 0x0000010000000000ULL
 723#define MCIC_VB_FA 0x0000008000000000ULL
 724#define MCIC_VB_VR 0x0000004000000000ULL
 725#define MCIC_VB_EC 0x0000002000000000ULL
 726#define MCIC_VB_FP 0x0000001000000000ULL
 727#define MCIC_VB_GR 0x0000000800000000ULL
 728#define MCIC_VB_CR 0x0000000400000000ULL
 729#define MCIC_VB_ST 0x0000000100000000ULL
 730#define MCIC_VB_AR 0x0000000040000000ULL
 731#define MCIC_VB_GS 0x0000000008000000ULL
 732#define MCIC_VB_PR 0x0000000000200000ULL
 733#define MCIC_VB_FC 0x0000000000100000ULL
 734#define MCIC_VB_CT 0x0000000000020000ULL
 735#define MCIC_VB_CC 0x0000000000010000ULL
 736
 737static inline uint64_t s390_build_validity_mcic(void)
 738{
 739    uint64_t mcic;
 740
 741    /*
 742     * Indicate all validity bits (no damage) only. Other bits have to be
 743     * added by the caller. (storage errors, subclasses and subclass modifiers)
 744     */
 745    mcic = MCIC_VB_WP | MCIC_VB_MS | MCIC_VB_PM | MCIC_VB_IA | MCIC_VB_FP |
 746           MCIC_VB_GR | MCIC_VB_CR | MCIC_VB_ST | MCIC_VB_AR | MCIC_VB_PR |
 747           MCIC_VB_FC | MCIC_VB_CT | MCIC_VB_CC;
 748    if (s390_has_feat(S390_FEAT_VECTOR)) {
 749        mcic |= MCIC_VB_VR;
 750    }
 751    if (s390_has_feat(S390_FEAT_GUARDED_STORAGE)) {
 752        mcic |= MCIC_VB_GS;
 753    }
 754    return mcic;
 755}
 756
 757static inline void s390_do_cpu_full_reset(CPUState *cs, run_on_cpu_data arg)
 758{
 759    cpu_reset(cs);
 760}
 761
 762static inline void s390_do_cpu_reset(CPUState *cs, run_on_cpu_data arg)
 763{
 764    S390CPUClass *scc = S390_CPU_GET_CLASS(cs);
 765
 766    scc->reset(cs, S390_CPU_RESET_NORMAL);
 767}
 768
 769static inline void s390_do_cpu_initial_reset(CPUState *cs, run_on_cpu_data arg)
 770{
 771    S390CPUClass *scc = S390_CPU_GET_CLASS(cs);
 772
 773    scc->reset(cs, S390_CPU_RESET_INITIAL);
 774}
 775
 776static inline void s390_do_cpu_load_normal(CPUState *cs, run_on_cpu_data arg)
 777{
 778    S390CPUClass *scc = S390_CPU_GET_CLASS(cs);
 779
 780    scc->load_normal(cs);
 781}
 782
 783
 784/* cpu.c */
 785void s390_crypto_reset(void);
 786int s390_set_memory_limit(uint64_t new_limit, uint64_t *hw_limit);
 787void s390_set_max_pagesize(uint64_t pagesize, Error **errp);
 788void s390_cmma_reset(void);
 789void s390_enable_css_support(S390CPU *cpu);
 790void s390_do_cpu_set_diag318(CPUState *cs, run_on_cpu_data arg);
 791int s390_assign_subch_ioeventfd(EventNotifier *notifier, uint32_t sch_id,
 792                                int vq, bool assign);
 793#ifndef CONFIG_USER_ONLY
 794unsigned int s390_cpu_set_state(uint8_t cpu_state, S390CPU *cpu);
 795#else
 796static inline unsigned int s390_cpu_set_state(uint8_t cpu_state, S390CPU *cpu)
 797{
 798    return 0;
 799}
 800#endif /* CONFIG_USER_ONLY */
 801static inline uint8_t s390_cpu_get_state(S390CPU *cpu)
 802{
 803    return cpu->env.cpu_state;
 804}
 805
 806
 807/* cpu_models.c */
 808void s390_cpu_list(void);
 809#define cpu_list s390_cpu_list
 810void s390_set_qemu_cpu_model(uint16_t type, uint8_t gen, uint8_t ec_ga,
 811                             const S390FeatInit feat_init);
 812
 813
 814/* helper.c */
 815#define S390_CPU_TYPE_SUFFIX "-" TYPE_S390_CPU
 816#define S390_CPU_TYPE_NAME(name) (name S390_CPU_TYPE_SUFFIX)
 817#define CPU_RESOLVING_TYPE TYPE_S390_CPU
 818
 819/* interrupt.c */
 820#define RA_IGNORED                  0
 821void s390_program_interrupt(CPUS390XState *env, uint32_t code, uintptr_t ra);
 822/* service interrupts are floating therefore we must not pass an cpustate */
 823void s390_sclp_extint(uint32_t parm);
 824
 825/* mmu_helper.c */
 826int s390_cpu_virt_mem_rw(S390CPU *cpu, vaddr laddr, uint8_t ar, void *hostbuf,
 827                         int len, bool is_write);
 828#define s390_cpu_virt_mem_read(cpu, laddr, ar, dest, len)    \
 829        s390_cpu_virt_mem_rw(cpu, laddr, ar, dest, len, false)
 830#define s390_cpu_virt_mem_write(cpu, laddr, ar, dest, len)       \
 831        s390_cpu_virt_mem_rw(cpu, laddr, ar, dest, len, true)
 832#define s390_cpu_virt_mem_check_read(cpu, laddr, ar, len)   \
 833        s390_cpu_virt_mem_rw(cpu, laddr, ar, NULL, len, false)
 834#define s390_cpu_virt_mem_check_write(cpu, laddr, ar, len)   \
 835        s390_cpu_virt_mem_rw(cpu, laddr, ar, NULL, len, true)
 836void s390_cpu_virt_mem_handle_exc(S390CPU *cpu, uintptr_t ra);
 837int s390_cpu_pv_mem_rw(S390CPU *cpu, unsigned int offset, void *hostbuf,
 838                       int len, bool is_write);
 839#define s390_cpu_pv_mem_read(cpu, offset, dest, len)    \
 840        s390_cpu_pv_mem_rw(cpu, offset, dest, len, false)
 841#define s390_cpu_pv_mem_write(cpu, offset, dest, len)       \
 842        s390_cpu_pv_mem_rw(cpu, offset, dest, len, true)
 843
 844/* sigp.c */
 845int s390_cpu_restart(S390CPU *cpu);
 846void s390_init_sigp(void);
 847
 848/* helper.c */
 849void s390_cpu_set_psw(CPUS390XState *env, uint64_t mask, uint64_t addr);
 850uint64_t s390_cpu_get_psw_mask(CPUS390XState *env);
 851
 852/* outside of target/s390x/ */
 853S390CPU *s390_cpu_addr2state(uint16_t cpu_addr);
 854
 855#include "exec/cpu-all.h"
 856
 857#endif
 858