LXR qemu/target/riscv/cpu.h

   1/*
   2 * QEMU RISC-V CPU
   3 *
   4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
   5 * Copyright (c) 2017-2018 SiFive, Inc.
   6 *
   7 * This program is free software; you can redistribute it and/or modify it
   8 * under the terms and conditions of the GNU General Public License,
   9 * version 2 or later, as published by the Free Software Foundation.
  10 *
  11 * This program is distributed in the hope it will be useful, but WITHOUT
  12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14 * more details.
  15 *
  16 * You should have received a copy of the GNU General Public License along with
  17 * this program.  If not, see <http://www.gnu.org/licenses/>.
  18 */
  19
  20#ifndef RISCV_CPU_H
  21#define RISCV_CPU_H
  22
  23#include "hw/core/cpu.h"
  24#include "hw/registerfields.h"
  25#include "exec/cpu-defs.h"
  26#include "qemu/cpu-float.h"
  27#include "qom/object.h"
  28#include "qemu/int128.h"
  29#include "cpu_bits.h"
  30#include "qapi/qapi-types-common.h"
  31
  32#define TCG_GUEST_DEFAULT_MO 0
  33
  34/*
  35 * RISC-V-specific extra insn start words:
  36 * 1: Original instruction opcode
  37 */
  38#define TARGET_INSN_START_EXTRA_WORDS 1
  39
  40#define TYPE_RISCV_CPU "riscv-cpu"
  41
  42#define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU
  43#define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX)
  44#define CPU_RESOLVING_TYPE TYPE_RISCV_CPU
  45
  46#define TYPE_RISCV_CPU_ANY              RISCV_CPU_TYPE_NAME("any")
  47#define TYPE_RISCV_CPU_BASE32           RISCV_CPU_TYPE_NAME("rv32")
  48#define TYPE_RISCV_CPU_BASE64           RISCV_CPU_TYPE_NAME("rv64")
  49#define TYPE_RISCV_CPU_BASE128          RISCV_CPU_TYPE_NAME("x-rv128")
  50#define TYPE_RISCV_CPU_IBEX             RISCV_CPU_TYPE_NAME("lowrisc-ibex")
  51#define TYPE_RISCV_CPU_SHAKTI_C         RISCV_CPU_TYPE_NAME("shakti-c")
  52#define TYPE_RISCV_CPU_SIFIVE_E31       RISCV_CPU_TYPE_NAME("sifive-e31")
  53#define TYPE_RISCV_CPU_SIFIVE_E34       RISCV_CPU_TYPE_NAME("sifive-e34")
  54#define TYPE_RISCV_CPU_SIFIVE_E51       RISCV_CPU_TYPE_NAME("sifive-e51")
  55#define TYPE_RISCV_CPU_SIFIVE_U34       RISCV_CPU_TYPE_NAME("sifive-u34")
  56#define TYPE_RISCV_CPU_SIFIVE_U54       RISCV_CPU_TYPE_NAME("sifive-u54")
  57#define TYPE_RISCV_CPU_THEAD_C906       RISCV_CPU_TYPE_NAME("thead-c906")
  58#define TYPE_RISCV_CPU_HOST             RISCV_CPU_TYPE_NAME("host")
  59
  60#if defined(TARGET_RISCV32)
  61# define TYPE_RISCV_CPU_BASE            TYPE_RISCV_CPU_BASE32
  62#elif defined(TARGET_RISCV64)
  63# define TYPE_RISCV_CPU_BASE            TYPE_RISCV_CPU_BASE64
  64#endif
  65
  66#define RV(x) ((target_ulong)1 << (x - 'A'))
  67
  68/*
  69 * Consider updating register_cpu_props() when adding
  70 * new MISA bits here.
  71 */
  72#define RVI RV('I')
  73#define RVE RV('E') /* E and I are mutually exclusive */
  74#define RVM RV('M')
  75#define RVA RV('A')
  76#define RVF RV('F')
  77#define RVD RV('D')
  78#define RVV RV('V')
  79#define RVC RV('C')
  80#define RVS RV('S')
  81#define RVU RV('U')
  82#define RVH RV('H')
  83#define RVJ RV('J')
  84
  85
  86/* Privileged specification version */
  87enum {
  88    PRIV_VERSION_1_10_0 = 0,
  89    PRIV_VERSION_1_11_0,
  90    PRIV_VERSION_1_12_0,
  91};
  92
  93#define VEXT_VERSION_1_00_0 0x00010000
  94
  95enum {
  96    TRANSLATE_SUCCESS,
  97    TRANSLATE_FAIL,
  98    TRANSLATE_PMP_FAIL,
  99    TRANSLATE_G_STAGE_FAIL
 100};
 101
 102#define MMU_USER_IDX 3
 103
 104#define MAX_RISCV_PMPS (16)
 105
 106typedef struct CPUArchState CPURISCVState;
 107
 108#if !defined(CONFIG_USER_ONLY)
 109#include "pmp.h"
 110#include "debug.h"
 111#endif
 112
 113#define RV_VLEN_MAX 1024
 114#define RV_MAX_MHPMEVENTS 32
 115#define RV_MAX_MHPMCOUNTERS 32
 116
 117FIELD(VTYPE, VLMUL, 0, 3)
 118FIELD(VTYPE, VSEW, 3, 3)
 119FIELD(VTYPE, VTA, 6, 1)
 120FIELD(VTYPE, VMA, 7, 1)
 121FIELD(VTYPE, VEDIV, 8, 2)
 122FIELD(VTYPE, RESERVED, 10, sizeof(target_ulong) * 8 - 11)
 123
 124typedef struct PMUCTRState {
 125    /* Current value of a counter */
 126    target_ulong mhpmcounter_val;
 127    /* Current value of a counter in RV32*/
 128    target_ulong mhpmcounterh_val;
 129    /* Snapshot values of counter */
 130    target_ulong mhpmcounter_prev;
 131    /* Snapshort value of a counter in RV32 */
 132    target_ulong mhpmcounterh_prev;
 133    bool started;
 134    /* Value beyond UINT32_MAX/UINT64_MAX before overflow interrupt trigger */
 135    target_ulong irq_overflow_left;
 136} PMUCTRState;
 137
 138struct CPUArchState {
 139    target_ulong gpr[32];
 140    target_ulong gprh[32]; /* 64 top bits of the 128-bit registers */
 141
 142    /* vector coprocessor state. */
 143    uint64_t vreg[32 * RV_VLEN_MAX / 64] QEMU_ALIGNED(16);
 144    target_ulong vxrm;
 145    target_ulong vxsat;
 146    target_ulong vl;
 147    target_ulong vstart;
 148    target_ulong vtype;
 149    bool vill;
 150
 151    target_ulong pc;
 152    target_ulong load_res;
 153    target_ulong load_val;
 154
 155    /* Floating-Point state */
 156    uint64_t fpr[32]; /* assume both F and D extensions */
 157    target_ulong frm;
 158    float_status fp_status;
 159
 160    target_ulong badaddr;
 161    target_ulong bins;
 162
 163    target_ulong guest_phys_fault_addr;
 164
 165    target_ulong priv_ver;
 166    target_ulong bext_ver;
 167    target_ulong vext_ver;
 168
 169    /* RISCVMXL, but uint32_t for vmstate migration */
 170    uint32_t misa_mxl;      /* current mxl */
 171    uint32_t misa_mxl_max;  /* max mxl for this cpu */
 172    uint32_t misa_ext;      /* current extensions */
 173    uint32_t misa_ext_mask; /* max ext for this cpu */
 174    uint32_t xl;            /* current xlen */
 175
 176    /* 128-bit helpers upper part return value */
 177    target_ulong retxh;
 178
 179#ifdef CONFIG_USER_ONLY
 180    uint32_t elf_flags;
 181#endif
 182
 183#ifndef CONFIG_USER_ONLY
 184    target_ulong priv;
 185    /* This contains QEMU specific information about the virt state. */
 186    target_ulong virt;
 187    target_ulong geilen;
 188    uint64_t resetvec;
 189
 190    target_ulong mhartid;
 191    /*
 192     * For RV32 this is 32-bit mstatus and 32-bit mstatush.
 193     * For RV64 this is a 64-bit mstatus.
 194     */
 195    uint64_t mstatus;
 196
 197    uint64_t mip;
 198    /*
 199     * MIP contains the software writable version of SEIP ORed with the
 200     * external interrupt value. The MIP register is always up-to-date.
 201     * To keep track of the current source, we also save booleans of the values
 202     * here.
 203     */
 204    bool external_seip;
 205    bool software_seip;
 206
 207    uint64_t miclaim;
 208
 209    uint64_t mie;
 210    uint64_t mideleg;
 211
 212    target_ulong satp;   /* since: priv-1.10.0 */
 213    target_ulong stval;
 214    target_ulong medeleg;
 215
 216    target_ulong stvec;
 217    target_ulong sepc;
 218    target_ulong scause;
 219
 220    target_ulong mtvec;
 221    target_ulong mepc;
 222    target_ulong mcause;
 223    target_ulong mtval;  /* since: priv-1.10.0 */
 224
 225    /* Machine and Supervisor interrupt priorities */
 226    uint8_t miprio[64];
 227    uint8_t siprio[64];
 228
 229    /* AIA CSRs */
 230    target_ulong miselect;
 231    target_ulong siselect;
 232
 233    /* Hypervisor CSRs */
 234    target_ulong hstatus;
 235    target_ulong hedeleg;
 236    uint64_t hideleg;
 237    target_ulong hcounteren;
 238    target_ulong htval;
 239    target_ulong htinst;
 240    target_ulong hgatp;
 241    target_ulong hgeie;
 242    target_ulong hgeip;
 243    uint64_t htimedelta;
 244
 245    /* Hypervisor controlled virtual interrupt priorities */
 246    target_ulong hvictl;
 247    uint8_t hviprio[64];
 248
 249    /* Upper 64-bits of 128-bit CSRs */
 250    uint64_t mscratchh;
 251    uint64_t sscratchh;
 252
 253    /* Virtual CSRs */
 254    /*
 255     * For RV32 this is 32-bit vsstatus and 32-bit vsstatush.
 256     * For RV64 this is a 64-bit vsstatus.
 257     */
 258    uint64_t vsstatus;
 259    target_ulong vstvec;
 260    target_ulong vsscratch;
 261    target_ulong vsepc;
 262    target_ulong vscause;
 263    target_ulong vstval;
 264    target_ulong vsatp;
 265
 266    /* AIA VS-mode CSRs */
 267    target_ulong vsiselect;
 268
 269    target_ulong mtval2;
 270    target_ulong mtinst;
 271
 272    /* HS Backup CSRs */
 273    target_ulong stvec_hs;
 274    target_ulong sscratch_hs;
 275    target_ulong sepc_hs;
 276    target_ulong scause_hs;
 277    target_ulong stval_hs;
 278    target_ulong satp_hs;
 279    uint64_t mstatus_hs;
 280
 281    /* Signals whether the current exception occurred with two-stage address
 282       translation active. */
 283    bool two_stage_lookup;
 284    /*
 285     * Signals whether the current exception occurred while doing two-stage
 286     * address translation for the VS-stage page table walk.
 287     */
 288    bool two_stage_indirect_lookup;
 289
 290    target_ulong scounteren;
 291    target_ulong mcounteren;
 292
 293    target_ulong mcountinhibit;
 294
 295    /* PMU counter state */
 296    PMUCTRState pmu_ctrs[RV_MAX_MHPMCOUNTERS];
 297
 298    /* PMU event selector configured values. First three are unused*/
 299    target_ulong mhpmevent_val[RV_MAX_MHPMEVENTS];
 300
 301    /* PMU event selector configured values for RV32*/
 302    target_ulong mhpmeventh_val[RV_MAX_MHPMEVENTS];
 303
 304    target_ulong sscratch;
 305    target_ulong mscratch;
 306
 307    /* Sstc CSRs */
 308    uint64_t stimecmp;
 309
 310    uint64_t vstimecmp;
 311
 312    /* physical memory protection */
 313    pmp_table_t pmp_state;
 314    target_ulong mseccfg;
 315
 316    /* trigger module */
 317    target_ulong trigger_cur;
 318    target_ulong tdata1[RV_MAX_TRIGGERS];
 319    target_ulong tdata2[RV_MAX_TRIGGERS];
 320    target_ulong tdata3[RV_MAX_TRIGGERS];
 321    struct CPUBreakpoint *cpu_breakpoint[RV_MAX_TRIGGERS];
 322    struct CPUWatchpoint *cpu_watchpoint[RV_MAX_TRIGGERS];
 323    QEMUTimer *itrigger_timer[RV_MAX_TRIGGERS];
 324    int64_t last_icount;
 325    bool itrigger_enabled;
 326
 327    /* machine specific rdtime callback */
 328    uint64_t (*rdtime_fn)(void *);
 329    void *rdtime_fn_arg;
 330
 331    /* machine specific AIA ireg read-modify-write callback */
 332#define AIA_MAKE_IREG(__isel, __priv, __virt, __vgein, __xlen) \
 333    ((((__xlen) & 0xff) << 24) | \
 334     (((__vgein) & 0x3f) << 20) | \
 335     (((__virt) & 0x1) << 18) | \
 336     (((__priv) & 0x3) << 16) | \
 337     (__isel & 0xffff))
 338#define AIA_IREG_ISEL(__ireg)                  ((__ireg) & 0xffff)
 339#define AIA_IREG_PRIV(__ireg)                  (((__ireg) >> 16) & 0x3)
 340#define AIA_IREG_VIRT(__ireg)                  (((__ireg) >> 18) & 0x1)
 341#define AIA_IREG_VGEIN(__ireg)                 (((__ireg) >> 20) & 0x3f)
 342#define AIA_IREG_XLEN(__ireg)                  (((__ireg) >> 24) & 0xff)
 343    int (*aia_ireg_rmw_fn[4])(void *arg, target_ulong reg,
 344        target_ulong *val, target_ulong new_val, target_ulong write_mask);
 345    void *aia_ireg_rmw_fn_arg[4];
 346
 347    /* True if in debugger mode.  */
 348    bool debugger;
 349
 350    /*
 351     * CSRs for PointerMasking extension
 352     */
 353    target_ulong mmte;
 354    target_ulong mpmmask;
 355    target_ulong mpmbase;
 356    target_ulong spmmask;
 357    target_ulong spmbase;
 358    target_ulong upmmask;
 359    target_ulong upmbase;
 360
 361    /* CSRs for execution enviornment configuration */
 362    uint64_t menvcfg;
 363    uint64_t mstateen[SMSTATEEN_MAX_COUNT];
 364    uint64_t hstateen[SMSTATEEN_MAX_COUNT];
 365    uint64_t sstateen[SMSTATEEN_MAX_COUNT];
 366    target_ulong senvcfg;
 367    uint64_t henvcfg;
 368#endif
 369    target_ulong cur_pmmask;
 370    target_ulong cur_pmbase;
 371
 372    /* Fields from here on are preserved across CPU reset. */
 373    QEMUTimer *stimer; /* Internal timer for S-mode interrupt */
 374    QEMUTimer *vstimer; /* Internal timer for VS-mode interrupt */
 375    bool vstime_irq;
 376
 377    hwaddr kernel_addr;
 378    hwaddr fdt_addr;
 379
 380    /* kvm timer */
 381    bool kvm_timer_dirty;
 382    uint64_t kvm_timer_time;
 383    uint64_t kvm_timer_compare;
 384    uint64_t kvm_timer_state;
 385    uint64_t kvm_timer_frequency;
 386};
 387
 388OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass, RISCV_CPU)
 389
 390/**
 391 * RISCVCPUClass:
 392 * @parent_realize: The parent class' realize handler.
 393 * @parent_phases: The parent class' reset phase handlers.
 394 *
 395 * A RISCV CPU model.
 396 */
 397struct RISCVCPUClass {
 398    /*< private >*/
 399    CPUClass parent_class;
 400    /*< public >*/
 401    DeviceRealize parent_realize;
 402    ResettablePhases parent_phases;
 403};
 404
 405/*
 406 * map is a 16-bit bitmap: the most significant set bit in map is the maximum
 407 * satp mode that is supported. It may be chosen by the user and must respect
 408 * what qemu implements (valid_1_10_32/64) and what the hw is capable of
 409 * (supported bitmap below).
 410 *
 411 * init is a 16-bit bitmap used to make sure the user selected a correct
 412 * configuration as per the specification.
 413 *
 414 * supported is a 16-bit bitmap used to reflect the hw capabilities.
 415 */
 416typedef struct {
 417    uint16_t map, init, supported;
 418} RISCVSATPMap;
 419
 420struct RISCVCPUConfig {
 421    bool ext_i;
 422    bool ext_e;
 423    bool ext_g;
 424    bool ext_m;
 425    bool ext_a;
 426    bool ext_f;
 427    bool ext_d;
 428    bool ext_c;
 429    bool ext_s;
 430    bool ext_u;
 431    bool ext_h;
 432    bool ext_j;
 433    bool ext_v;
 434    bool ext_zba;
 435    bool ext_zbb;
 436    bool ext_zbc;
 437    bool ext_zbkb;
 438    bool ext_zbkc;
 439    bool ext_zbkx;
 440    bool ext_zbs;
 441    bool ext_zk;
 442    bool ext_zkn;
 443    bool ext_zknd;
 444    bool ext_zkne;
 445    bool ext_zknh;
 446    bool ext_zkr;
 447    bool ext_zks;
 448    bool ext_zksed;
 449    bool ext_zksh;
 450    bool ext_zkt;
 451    bool ext_ifencei;
 452    bool ext_icsr;
 453    bool ext_icbom;
 454    bool ext_icboz;
 455    bool ext_zicond;
 456    bool ext_zihintpause;
 457    bool ext_smstateen;
 458    bool ext_sstc;
 459    bool ext_svadu;
 460    bool ext_svinval;
 461    bool ext_svnapot;
 462    bool ext_svpbmt;
 463    bool ext_zdinx;
 464    bool ext_zawrs;
 465    bool ext_zfh;
 466    bool ext_zfhmin;
 467    bool ext_zfinx;
 468    bool ext_zhinx;
 469    bool ext_zhinxmin;
 470    bool ext_zve32f;
 471    bool ext_zve64f;
 472    bool ext_zve64d;
 473    bool ext_zmmul;
 474    bool ext_zvfh;
 475    bool ext_zvfhmin;
 476    bool ext_smaia;
 477    bool ext_ssaia;
 478    bool ext_sscofpmf;
 479    bool rvv_ta_all_1s;
 480    bool rvv_ma_all_1s;
 481
 482    uint32_t mvendorid;
 483    uint64_t marchid;
 484    uint64_t mimpid;
 485
 486    /* Vendor-specific custom extensions */
 487    bool ext_xtheadba;
 488    bool ext_xtheadbb;
 489    bool ext_xtheadbs;
 490    bool ext_xtheadcmo;
 491    bool ext_xtheadcondmov;
 492    bool ext_xtheadfmemidx;
 493    bool ext_xtheadfmv;
 494    bool ext_xtheadmac;
 495    bool ext_xtheadmemidx;
 496    bool ext_xtheadmempair;
 497    bool ext_xtheadsync;
 498    bool ext_XVentanaCondOps;
 499
 500    uint8_t pmu_num;
 501    char *priv_spec;
 502    char *user_spec;
 503    char *bext_spec;
 504    char *vext_spec;
 505    uint16_t vlen;
 506    uint16_t elen;
 507    uint16_t cbom_blocksize;
 508    uint16_t cboz_blocksize;
 509    bool mmu;
 510    bool pmp;
 511    bool epmp;
 512    bool debug;
 513    bool misa_w;
 514
 515    bool short_isa_string;
 516
 517#ifndef CONFIG_USER_ONLY
 518    RISCVSATPMap satp_mode;
 519#endif
 520};
 521
 522typedef struct RISCVCPUConfig RISCVCPUConfig;
 523
 524/**
 525 * RISCVCPU:
 526 * @env: #CPURISCVState
 527 *
 528 * A RISCV CPU.
 529 */
 530struct ArchCPU {
 531    /*< private >*/
 532    CPUState parent_obj;
 533    /*< public >*/
 534    CPUNegativeOffsetState neg;
 535    CPURISCVState env;
 536
 537    char *dyn_csr_xml;
 538    char *dyn_vreg_xml;
 539
 540    /* Configuration Settings */
 541    RISCVCPUConfig cfg;
 542
 543    QEMUTimer *pmu_timer;
 544    /* A bitmask of Available programmable counters */
 545    uint32_t pmu_avail_ctrs;
 546    /* Mapping of events to counters */
 547    GHashTable *pmu_event_ctr_map;
 548};
 549
 550static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext)
 551{
 552    return (env->misa_ext & ext) != 0;
 553}
 554
 555#include "cpu_user.h"
 556
 557extern const char * const riscv_int_regnames[];
 558extern const char * const riscv_int_regnamesh[];
 559extern const char * const riscv_fpr_regnames[];
 560
 561const char *riscv_cpu_get_trap_name(target_ulong cause, bool async);
 562void riscv_cpu_do_interrupt(CPUState *cpu);
 563int riscv_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs,
 564                               int cpuid, DumpState *s);
 565int riscv_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs,
 566                               int cpuid, DumpState *s);
 567int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
 568int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
 569int riscv_cpu_hviprio_index2irq(int index, int *out_irq, int *out_rdzero);
 570uint8_t riscv_cpu_default_priority(int irq);
 571uint64_t riscv_cpu_all_pending(CPURISCVState *env);
 572int riscv_cpu_mirq_pending(CPURISCVState *env);
 573int riscv_cpu_sirq_pending(CPURISCVState *env);
 574int riscv_cpu_vsirq_pending(CPURISCVState *env);
 575bool riscv_cpu_fp_enabled(CPURISCVState *env);
 576target_ulong riscv_cpu_get_geilen(CPURISCVState *env);
 577void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen);
 578bool riscv_cpu_vector_enabled(CPURISCVState *env);
 579bool riscv_cpu_virt_enabled(CPURISCVState *env);
 580void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable);
 581bool riscv_cpu_two_stage_lookup(int mmu_idx);
 582int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch);
 583G_NORETURN void  riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
 584                                               MMUAccessType access_type, int mmu_idx,
 585                                               uintptr_t retaddr);
 586bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
 587                        MMUAccessType access_type, int mmu_idx,
 588                        bool probe, uintptr_t retaddr);
 589char *riscv_isa_string(RISCVCPU *cpu);
 590void riscv_cpu_list(void);
 591
 592#define cpu_list riscv_cpu_list
 593#define cpu_mmu_index riscv_cpu_mmu_index
 594
 595#ifndef CONFIG_USER_ONLY
 596void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
 597                                     vaddr addr, unsigned size,
 598                                     MMUAccessType access_type,
 599                                     int mmu_idx, MemTxAttrs attrs,
 600                                     MemTxResult response, uintptr_t retaddr);
 601hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
 602bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request);
 603void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env);
 604int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts);
 605uint64_t riscv_cpu_update_mip(RISCVCPU *cpu, uint64_t mask, uint64_t value);
 606#define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */
 607void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void *),
 608                             void *arg);
 609void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, uint32_t priv,
 610                                   int (*rmw_fn)(void *arg,
 611                                                 target_ulong reg,
 612                                                 target_ulong *val,
 613                                                 target_ulong new_val,
 614                                                 target_ulong write_mask),
 615                                   void *rmw_fn_arg);
 616#endif
 617void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv);
 618
 619void riscv_translate_init(void);
 620G_NORETURN void riscv_raise_exception(CPURISCVState *env,
 621                                      uint32_t exception, uintptr_t pc);
 622
 623target_ulong riscv_cpu_get_fflags(CPURISCVState *env);
 624void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong);
 625
 626#define TB_FLAGS_PRIV_MMU_MASK                3
 627#define TB_FLAGS_PRIV_HYP_ACCESS_MASK   (1 << 2)
 628#define TB_FLAGS_MSTATUS_FS MSTATUS_FS
 629#define TB_FLAGS_MSTATUS_VS MSTATUS_VS
 630
 631#include "exec/cpu-all.h"
 632
 633FIELD(TB_FLAGS, MEM_IDX, 0, 3)
 634FIELD(TB_FLAGS, LMUL, 3, 3)
 635FIELD(TB_FLAGS, SEW, 6, 3)
 636/* Skip MSTATUS_VS (0x600) bits */
 637FIELD(TB_FLAGS, VL_EQ_VLMAX, 11, 1)
 638FIELD(TB_FLAGS, VILL, 12, 1)
 639/* Skip MSTATUS_FS (0x6000) bits */
 640/* Is a Hypervisor instruction load/store allowed? */
 641FIELD(TB_FLAGS, HLSX, 15, 1)
 642FIELD(TB_FLAGS, MSTATUS_HS_FS, 16, 2)
 643FIELD(TB_FLAGS, MSTATUS_HS_VS, 18, 2)
 644/* The combination of MXL/SXL/UXL that applies to the current cpu mode. */
 645FIELD(TB_FLAGS, XL, 20, 2)
 646/* If PointerMasking should be applied */
 647FIELD(TB_FLAGS, PM_MASK_ENABLED, 22, 1)
 648FIELD(TB_FLAGS, PM_BASE_ENABLED, 23, 1)
 649FIELD(TB_FLAGS, VTA, 24, 1)
 650FIELD(TB_FLAGS, VMA, 25, 1)
 651/* Native debug itrigger */
 652FIELD(TB_FLAGS, ITRIGGER, 26, 1)
 653
 654#ifdef TARGET_RISCV32
 655#define riscv_cpu_mxl(env)  ((void)(env), MXL_RV32)
 656#else
 657static inline RISCVMXL riscv_cpu_mxl(CPURISCVState *env)
 658{
 659    return env->misa_mxl;
 660}
 661#endif
 662#define riscv_cpu_mxl_bits(env) (1UL << (4 + riscv_cpu_mxl(env)))
 663
 664static inline const RISCVCPUConfig *riscv_cpu_cfg(CPURISCVState *env)
 665{
 666    return &env_archcpu(env)->cfg;
 667}
 668
 669#if defined(TARGET_RISCV32)
 670#define cpu_recompute_xl(env)  ((void)(env), MXL_RV32)
 671#else
 672static inline RISCVMXL cpu_recompute_xl(CPURISCVState *env)
 673{
 674    RISCVMXL xl = env->misa_mxl;
 675#if !defined(CONFIG_USER_ONLY)
 676    /*
 677     * When emulating a 32-bit-only cpu, use RV32.
 678     * When emulating a 64-bit cpu, and MXL has been reduced to RV32,
 679     * MSTATUSH doesn't have UXL/SXL, therefore XLEN cannot be widened
 680     * back to RV64 for lower privs.
 681     */
 682    if (xl != MXL_RV32) {
 683        switch (env->priv) {
 684        case PRV_M:
 685            break;
 686        case PRV_U:
 687            xl = get_field(env->mstatus, MSTATUS64_UXL);
 688            break;
 689        default: /* PRV_S | PRV_H */
 690            xl = get_field(env->mstatus, MSTATUS64_SXL);
 691            break;
 692        }
 693    }
 694#endif
 695    return xl;
 696}
 697#endif
 698
 699static inline int riscv_cpu_xlen(CPURISCVState *env)
 700{
 701    return 16 << env->xl;
 702}
 703
 704#ifdef TARGET_RISCV32
 705#define riscv_cpu_sxl(env)  ((void)(env), MXL_RV32)
 706#else
 707static inline RISCVMXL riscv_cpu_sxl(CPURISCVState *env)
 708{
 709#ifdef CONFIG_USER_ONLY
 710    return env->misa_mxl;
 711#else
 712    return get_field(env->mstatus, MSTATUS64_SXL);
 713#endif
 714}
 715#endif
 716
 717/*
 718 * Encode LMUL to lmul as follows:
 719 *     LMUL    vlmul    lmul
 720 *      1       000       0
 721 *      2       001       1
 722 *      4       010       2
 723 *      8       011       3
 724 *      -       100       -
 725 *     1/8      101      -3
 726 *     1/4      110      -2
 727 *     1/2      111      -1
 728 *
 729 * then, we can calculate VLMAX = vlen >> (vsew + 3 - lmul)
 730 * e.g. vlen = 256 bits, SEW = 16, LMUL = 1/8
 731 *      => VLMAX = vlen >> (1 + 3 - (-3))
 732 *               = 256 >> 7
 733 *               = 2
 734 */
 735static inline uint32_t vext_get_vlmax(RISCVCPU *cpu, target_ulong vtype)
 736{
 737    uint8_t sew = FIELD_EX64(vtype, VTYPE, VSEW);
 738    int8_t lmul = sextract32(FIELD_EX64(vtype, VTYPE, VLMUL), 0, 3);
 739    return cpu->cfg.vlen >> (sew + 3 - lmul);
 740}
 741
 742void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
 743                          target_ulong *cs_base, uint32_t *pflags);
 744
 745void riscv_cpu_update_mask(CPURISCVState *env);
 746
 747RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
 748                           target_ulong *ret_value,
 749                           target_ulong new_value, target_ulong write_mask);
 750RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno,
 751                                 target_ulong *ret_value,
 752                                 target_ulong new_value,
 753                                 target_ulong write_mask);
 754
 755static inline void riscv_csr_write(CPURISCVState *env, int csrno,
 756                                   target_ulong val)
 757{
 758    riscv_csrrw(env, csrno, NULL, val, MAKE_64BIT_MASK(0, TARGET_LONG_BITS));
 759}
 760
 761static inline target_ulong riscv_csr_read(CPURISCVState *env, int csrno)
 762{
 763    target_ulong val = 0;
 764    riscv_csrrw(env, csrno, &val, 0, 0);
 765    return val;
 766}
 767
 768typedef RISCVException (*riscv_csr_predicate_fn)(CPURISCVState *env,
 769                                                 int csrno);
 770typedef RISCVException (*riscv_csr_read_fn)(CPURISCVState *env, int csrno,
 771                                            target_ulong *ret_value);
 772typedef RISCVException (*riscv_csr_write_fn)(CPURISCVState *env, int csrno,
 773                                             target_ulong new_value);
 774typedef RISCVException (*riscv_csr_op_fn)(CPURISCVState *env, int csrno,
 775                                          target_ulong *ret_value,
 776                                          target_ulong new_value,
 777                                          target_ulong write_mask);
 778
 779RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno,
 780                                Int128 *ret_value,
 781                                Int128 new_value, Int128 write_mask);
 782
 783typedef RISCVException (*riscv_csr_read128_fn)(CPURISCVState *env, int csrno,
 784                                               Int128 *ret_value);
 785typedef RISCVException (*riscv_csr_write128_fn)(CPURISCVState *env, int csrno,
 786                                             Int128 new_value);
 787
 788typedef struct {
 789    const char *name;
 790    riscv_csr_predicate_fn predicate;
 791    riscv_csr_read_fn read;
 792    riscv_csr_write_fn write;
 793    riscv_csr_op_fn op;
 794    riscv_csr_read128_fn read128;
 795    riscv_csr_write128_fn write128;
 796    /* The default priv spec version should be PRIV_VERSION_1_10_0 (i.e 0) */
 797    uint32_t min_priv_ver;
 798} riscv_csr_operations;
 799
 800/* CSR function table constants */
 801enum {
 802    CSR_TABLE_SIZE = 0x1000
 803};
 804
 805/**
 806 * The event id are encoded based on the encoding specified in the
 807 * SBI specification v0.3
 808 */
 809
 810enum riscv_pmu_event_idx {
 811    RISCV_PMU_EVENT_HW_CPU_CYCLES = 0x01,
 812    RISCV_PMU_EVENT_HW_INSTRUCTIONS = 0x02,
 813    RISCV_PMU_EVENT_CACHE_DTLB_READ_MISS = 0x10019,
 814    RISCV_PMU_EVENT_CACHE_DTLB_WRITE_MISS = 0x1001B,
 815    RISCV_PMU_EVENT_CACHE_ITLB_PREFETCH_MISS = 0x10021,
 816};
 817
 818/* CSR function table */
 819extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE];
 820
 821extern const bool valid_vm_1_10_32[], valid_vm_1_10_64[];
 822
 823void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops);
 824void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops);
 825
 826void riscv_cpu_register_gdb_regs_for_features(CPUState *cs);
 827
 828uint8_t satp_mode_max_from_map(uint32_t map);
 829const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit);
 830
 831#endif /* RISCV_CPU_H */
 832