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20#include "qemu/osdep.h"
21#include "qemu/datadir.h"
22#include "qemu/units.h"
23#include "qemu/cutils.h"
24#include "qapi/error.h"
25#include "sysemu/qtest.h"
26#include "sysemu/sysemu.h"
27#include "sysemu/numa.h"
28#include "sysemu/reset.h"
29#include "sysemu/runstate.h"
30#include "sysemu/cpus.h"
31#include "sysemu/device_tree.h"
32#include "sysemu/hw_accel.h"
33#include "target/ppc/cpu.h"
34#include "hw/ppc/fdt.h"
35#include "hw/ppc/ppc.h"
36#include "hw/ppc/pnv.h"
37#include "hw/ppc/pnv_core.h"
38#include "hw/loader.h"
39#include "hw/nmi.h"
40#include "qapi/visitor.h"
41#include "monitor/monitor.h"
42#include "hw/intc/intc.h"
43#include "hw/ipmi/ipmi.h"
44#include "target/ppc/mmu-hash64.h"
45#include "hw/pci/msi.h"
46#include "hw/pci-host/pnv_phb.h"
47#include "hw/pci-host/pnv_phb3.h"
48#include "hw/pci-host/pnv_phb4.h"
49
50#include "hw/ppc/xics.h"
51#include "hw/qdev-properties.h"
52#include "hw/ppc/pnv_chip.h"
53#include "hw/ppc/pnv_xscom.h"
54#include "hw/ppc/pnv_pnor.h"
55
56#include "hw/isa/isa.h"
57#include "hw/char/serial.h"
58#include "hw/rtc/mc146818rtc.h"
59
60#include <libfdt.h>
61
62#define FDT_MAX_SIZE (1 * MiB)
63
64#define FW_FILE_NAME "skiboot.lid"
65#define FW_LOAD_ADDR 0x0
66#define FW_MAX_SIZE (16 * MiB)
67
68#define KERNEL_LOAD_ADDR 0x20000000
69#define KERNEL_MAX_SIZE (128 * MiB)
70#define INITRD_LOAD_ADDR 0x28000000
71#define INITRD_MAX_SIZE (128 * MiB)
72
73static const char *pnv_chip_core_typename(const PnvChip *o)
74{
75 const char *chip_type = object_class_get_name(object_get_class(OBJECT(o)));
76 int len = strlen(chip_type) - strlen(PNV_CHIP_TYPE_SUFFIX);
77 char *s = g_strdup_printf(PNV_CORE_TYPE_NAME("%.*s"), len, chip_type);
78 const char *core_type = object_class_get_name(object_class_by_name(s));
79 g_free(s);
80 return core_type;
81}
82
83
84
85
86
87
88#define MAX_CPUS 2048
89
90
91
92
93
94
95static void pnv_dt_memory(void *fdt, int chip_id, hwaddr start, hwaddr size)
96{
97 char *mem_name;
98 uint64_t mem_reg_property[2];
99 int off;
100
101 mem_reg_property[0] = cpu_to_be64(start);
102 mem_reg_property[1] = cpu_to_be64(size);
103
104 mem_name = g_strdup_printf("memory@%"HWADDR_PRIx, start);
105 off = fdt_add_subnode(fdt, 0, mem_name);
106 g_free(mem_name);
107
108 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory")));
109 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property,
110 sizeof(mem_reg_property))));
111 _FDT((fdt_setprop_cell(fdt, off, "ibm,chip-id", chip_id)));
112}
113
114static int get_cpus_node(void *fdt)
115{
116 int cpus_offset = fdt_path_offset(fdt, "/cpus");
117
118 if (cpus_offset < 0) {
119 cpus_offset = fdt_add_subnode(fdt, 0, "cpus");
120 if (cpus_offset) {
121 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1)));
122 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0)));
123 }
124 }
125 _FDT(cpus_offset);
126 return cpus_offset;
127}
128
129
130
131
132
133
134
135
136static void pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt)
137{
138 PowerPCCPU *cpu = pc->threads[0];
139 CPUState *cs = CPU(cpu);
140 DeviceClass *dc = DEVICE_GET_CLASS(cs);
141 int smt_threads = CPU_CORE(pc)->nr_threads;
142 CPUPPCState *env = &cpu->env;
143 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs);
144 g_autofree uint32_t *servers_prop = g_new(uint32_t, smt_threads);
145 int i;
146 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40),
147 0xffffffff, 0xffffffff};
148 uint32_t tbfreq = PNV_TIMEBASE_FREQ;
149 uint32_t cpufreq = 1000000000;
150 uint32_t page_sizes_prop[64];
151 size_t page_sizes_prop_size;
152 const uint8_t pa_features[] = { 24, 0,
153 0xf6, 0x3f, 0xc7, 0xc0, 0x80, 0xf0,
154 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
155 0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
156 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 };
157 int offset;
158 char *nodename;
159 int cpus_offset = get_cpus_node(fdt);
160
161 nodename = g_strdup_printf("%s@%x", dc->fw_name, pc->pir);
162 offset = fdt_add_subnode(fdt, cpus_offset, nodename);
163 _FDT(offset);
164 g_free(nodename);
165
166 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", chip->chip_id)));
167
168 _FDT((fdt_setprop_cell(fdt, offset, "reg", pc->pir)));
169 _FDT((fdt_setprop_cell(fdt, offset, "ibm,pir", pc->pir)));
170 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu")));
171
172 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR])));
173 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size",
174 env->dcache_line_size)));
175 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size",
176 env->dcache_line_size)));
177 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size",
178 env->icache_line_size)));
179 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size",
180 env->icache_line_size)));
181
182 if (pcc->l1_dcache_size) {
183 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size",
184 pcc->l1_dcache_size)));
185 } else {
186 warn_report("Unknown L1 dcache size for cpu");
187 }
188 if (pcc->l1_icache_size) {
189 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size",
190 pcc->l1_icache_size)));
191 } else {
192 warn_report("Unknown L1 icache size for cpu");
193 }
194
195 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq)));
196 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq)));
197 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size",
198 cpu->hash64_opts->slb_size)));
199 _FDT((fdt_setprop_string(fdt, offset, "status", "okay")));
200 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0)));
201
202 if (ppc_has_spr(cpu, SPR_PURR)) {
203 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0)));
204 }
205
206 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) {
207 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes",
208 segs, sizeof(segs))));
209 }
210
211
212
213
214
215
216
217 if (env->insns_flags & PPC_ALTIVEC) {
218 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1;
219
220 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx)));
221 }
222
223
224
225
226
227
228 if (env->insns_flags2 & PPC2_DFP) {
229 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1)));
230 }
231
232 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop,
233 sizeof(page_sizes_prop));
234 if (page_sizes_prop_size) {
235 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes",
236 page_sizes_prop, page_sizes_prop_size)));
237 }
238
239 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features",
240 pa_features, sizeof(pa_features))));
241
242
243 for (i = 0; i < smt_threads; i++) {
244 servers_prop[i] = cpu_to_be32(pc->pir + i);
245 }
246 _FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s",
247 servers_prop, sizeof(*servers_prop) * smt_threads)));
248}
249
250static void pnv_dt_icp(PnvChip *chip, void *fdt, uint32_t pir,
251 uint32_t nr_threads)
252{
253 uint64_t addr = PNV_ICP_BASE(chip) | (pir << 12);
254 char *name;
255 const char compat[] = "IBM,power8-icp\0IBM,ppc-xicp";
256 uint32_t irange[2], i, rsize;
257 uint64_t *reg;
258 int offset;
259
260 irange[0] = cpu_to_be32(pir);
261 irange[1] = cpu_to_be32(nr_threads);
262
263 rsize = sizeof(uint64_t) * 2 * nr_threads;
264 reg = g_malloc(rsize);
265 for (i = 0; i < nr_threads; i++) {
266 reg[i * 2] = cpu_to_be64(addr | ((pir + i) * 0x1000));
267 reg[i * 2 + 1] = cpu_to_be64(0x1000);
268 }
269
270 name = g_strdup_printf("interrupt-controller@%"PRIX64, addr);
271 offset = fdt_add_subnode(fdt, 0, name);
272 _FDT(offset);
273 g_free(name);
274
275 _FDT((fdt_setprop(fdt, offset, "compatible", compat, sizeof(compat))));
276 _FDT((fdt_setprop(fdt, offset, "reg", reg, rsize)));
277 _FDT((fdt_setprop_string(fdt, offset, "device_type",
278 "PowerPC-External-Interrupt-Presentation")));
279 _FDT((fdt_setprop(fdt, offset, "interrupt-controller", NULL, 0)));
280 _FDT((fdt_setprop(fdt, offset, "ibm,interrupt-server-ranges",
281 irange, sizeof(irange))));
282 _FDT((fdt_setprop_cell(fdt, offset, "#interrupt-cells", 1)));
283 _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 0)));
284 g_free(reg);
285}
286
287
288
289
290
291PnvChip *pnv_chip_add_phb(PnvChip *chip, PnvPHB *phb)
292{
293 Pnv8Chip *chip8 = PNV8_CHIP(chip);
294
295 phb->chip = chip;
296
297 chip8->phbs[chip8->num_phbs] = phb;
298 chip8->num_phbs++;
299 return chip;
300}
301
302static void pnv_chip_power8_dt_populate(PnvChip *chip, void *fdt)
303{
304 static const char compat[] = "ibm,power8-xscom\0ibm,xscom";
305 int i;
306
307 pnv_dt_xscom(chip, fdt, 0,
308 cpu_to_be64(PNV_XSCOM_BASE(chip)),
309 cpu_to_be64(PNV_XSCOM_SIZE),
310 compat, sizeof(compat));
311
312 for (i = 0; i < chip->nr_cores; i++) {
313 PnvCore *pnv_core = chip->cores[i];
314
315 pnv_dt_core(chip, pnv_core, fdt);
316
317
318 pnv_dt_icp(chip, fdt, pnv_core->pir, CPU_CORE(pnv_core)->nr_threads);
319 }
320
321 if (chip->ram_size) {
322 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size);
323 }
324}
325
326static void pnv_chip_power9_dt_populate(PnvChip *chip, void *fdt)
327{
328 static const char compat[] = "ibm,power9-xscom\0ibm,xscom";
329 int i;
330
331 pnv_dt_xscom(chip, fdt, 0,
332 cpu_to_be64(PNV9_XSCOM_BASE(chip)),
333 cpu_to_be64(PNV9_XSCOM_SIZE),
334 compat, sizeof(compat));
335
336 for (i = 0; i < chip->nr_cores; i++) {
337 PnvCore *pnv_core = chip->cores[i];
338
339 pnv_dt_core(chip, pnv_core, fdt);
340 }
341
342 if (chip->ram_size) {
343 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size);
344 }
345
346 pnv_dt_lpc(chip, fdt, 0, PNV9_LPCM_BASE(chip), PNV9_LPCM_SIZE);
347}
348
349static void pnv_chip_power10_dt_populate(PnvChip *chip, void *fdt)
350{
351 static const char compat[] = "ibm,power10-xscom\0ibm,xscom";
352 int i;
353
354 pnv_dt_xscom(chip, fdt, 0,
355 cpu_to_be64(PNV10_XSCOM_BASE(chip)),
356 cpu_to_be64(PNV10_XSCOM_SIZE),
357 compat, sizeof(compat));
358
359 for (i = 0; i < chip->nr_cores; i++) {
360 PnvCore *pnv_core = chip->cores[i];
361
362 pnv_dt_core(chip, pnv_core, fdt);
363 }
364
365 if (chip->ram_size) {
366 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size);
367 }
368
369 pnv_dt_lpc(chip, fdt, 0, PNV10_LPCM_BASE(chip), PNV10_LPCM_SIZE);
370}
371
372static void pnv_dt_rtc(ISADevice *d, void *fdt, int lpc_off)
373{
374 uint32_t io_base = d->ioport_id;
375 uint32_t io_regs[] = {
376 cpu_to_be32(1),
377 cpu_to_be32(io_base),
378 cpu_to_be32(2)
379 };
380 char *name;
381 int node;
382
383 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base);
384 node = fdt_add_subnode(fdt, lpc_off, name);
385 _FDT(node);
386 g_free(name);
387
388 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs))));
389 _FDT((fdt_setprop_string(fdt, node, "compatible", "pnpPNP,b00")));
390}
391
392static void pnv_dt_serial(ISADevice *d, void *fdt, int lpc_off)
393{
394 const char compatible[] = "ns16550\0pnpPNP,501";
395 uint32_t io_base = d->ioport_id;
396 uint32_t io_regs[] = {
397 cpu_to_be32(1),
398 cpu_to_be32(io_base),
399 cpu_to_be32(8)
400 };
401 uint32_t irq;
402 char *name;
403 int node;
404
405 irq = object_property_get_uint(OBJECT(d), "irq", &error_fatal);
406
407 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base);
408 node = fdt_add_subnode(fdt, lpc_off, name);
409 _FDT(node);
410 g_free(name);
411
412 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs))));
413 _FDT((fdt_setprop(fdt, node, "compatible", compatible,
414 sizeof(compatible))));
415
416 _FDT((fdt_setprop_cell(fdt, node, "clock-frequency", 1843200)));
417 _FDT((fdt_setprop_cell(fdt, node, "current-speed", 115200)));
418 _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq)));
419 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent",
420 fdt_get_phandle(fdt, lpc_off))));
421
422
423 _FDT((fdt_setprop_string(fdt, node, "device_type", "serial")));
424}
425
426static void pnv_dt_ipmi_bt(ISADevice *d, void *fdt, int lpc_off)
427{
428 const char compatible[] = "bt\0ipmi-bt";
429 uint32_t io_base;
430 uint32_t io_regs[] = {
431 cpu_to_be32(1),
432 0,
433 cpu_to_be32(3)
434 };
435 uint32_t irq;
436 char *name;
437 int node;
438
439 io_base = object_property_get_int(OBJECT(d), "ioport", &error_fatal);
440 io_regs[1] = cpu_to_be32(io_base);
441
442 irq = object_property_get_int(OBJECT(d), "irq", &error_fatal);
443
444 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base);
445 node = fdt_add_subnode(fdt, lpc_off, name);
446 _FDT(node);
447 g_free(name);
448
449 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs))));
450 _FDT((fdt_setprop(fdt, node, "compatible", compatible,
451 sizeof(compatible))));
452
453
454 _FDT((fdt_setprop_string(fdt, node, "status", "reserved")));
455 _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq)));
456 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent",
457 fdt_get_phandle(fdt, lpc_off))));
458}
459
460typedef struct ForeachPopulateArgs {
461 void *fdt;
462 int offset;
463} ForeachPopulateArgs;
464
465static int pnv_dt_isa_device(DeviceState *dev, void *opaque)
466{
467 ForeachPopulateArgs *args = opaque;
468 ISADevice *d = ISA_DEVICE(dev);
469
470 if (object_dynamic_cast(OBJECT(dev), TYPE_MC146818_RTC)) {
471 pnv_dt_rtc(d, args->fdt, args->offset);
472 } else if (object_dynamic_cast(OBJECT(dev), TYPE_ISA_SERIAL)) {
473 pnv_dt_serial(d, args->fdt, args->offset);
474 } else if (object_dynamic_cast(OBJECT(dev), "isa-ipmi-bt")) {
475 pnv_dt_ipmi_bt(d, args->fdt, args->offset);
476 } else {
477 error_report("unknown isa device %s@i%x", qdev_fw_name(dev),
478 d->ioport_id);
479 }
480
481 return 0;
482}
483
484
485
486
487
488static void pnv_dt_isa(PnvMachineState *pnv, void *fdt)
489{
490 int isa_offset = fdt_path_offset(fdt, pnv->chips[0]->dt_isa_nodename);
491 ForeachPopulateArgs args = {
492 .fdt = fdt,
493 .offset = isa_offset,
494 };
495 uint32_t phandle;
496
497 _FDT((fdt_setprop(fdt, isa_offset, "primary", NULL, 0)));
498
499 phandle = qemu_fdt_alloc_phandle(fdt);
500 assert(phandle > 0);
501 _FDT((fdt_setprop_cell(fdt, isa_offset, "phandle", phandle)));
502
503
504
505
506
507 qbus_walk_children(BUS(pnv->isa_bus), pnv_dt_isa_device, NULL, NULL, NULL,
508 &args);
509}
510
511static void pnv_dt_power_mgt(PnvMachineState *pnv, void *fdt)
512{
513 int off;
514
515 off = fdt_add_subnode(fdt, 0, "ibm,opal");
516 off = fdt_add_subnode(fdt, off, "power-mgt");
517
518 _FDT(fdt_setprop_cell(fdt, off, "ibm,enabled-stop-levels", 0xc0000000));
519}
520
521static void *pnv_dt_create(MachineState *machine)
522{
523 PnvMachineClass *pmc = PNV_MACHINE_GET_CLASS(machine);
524 PnvMachineState *pnv = PNV_MACHINE(machine);
525 void *fdt;
526 char *buf;
527 int off;
528 int i;
529
530 fdt = g_malloc0(FDT_MAX_SIZE);
531 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE)));
532
533
534 _FDT((fdt_add_subnode(fdt, 0, "qemu")));
535
536
537 _FDT((fdt_setprop_cell(fdt, 0, "#address-cells", 0x2)));
538 _FDT((fdt_setprop_cell(fdt, 0, "#size-cells", 0x2)));
539 _FDT((fdt_setprop_string(fdt, 0, "model",
540 "IBM PowerNV (emulated by qemu)")));
541 _FDT((fdt_setprop(fdt, 0, "compatible", pmc->compat, pmc->compat_size)));
542
543 buf = qemu_uuid_unparse_strdup(&qemu_uuid);
544 _FDT((fdt_setprop_string(fdt, 0, "vm,uuid", buf)));
545 if (qemu_uuid_set) {
546 _FDT((fdt_setprop_string(fdt, 0, "system-id", buf)));
547 }
548 g_free(buf);
549
550 off = fdt_add_subnode(fdt, 0, "chosen");
551 if (machine->kernel_cmdline) {
552 _FDT((fdt_setprop_string(fdt, off, "bootargs",
553 machine->kernel_cmdline)));
554 }
555
556 if (pnv->initrd_size) {
557 uint32_t start_prop = cpu_to_be32(pnv->initrd_base);
558 uint32_t end_prop = cpu_to_be32(pnv->initrd_base + pnv->initrd_size);
559
560 _FDT((fdt_setprop(fdt, off, "linux,initrd-start",
561 &start_prop, sizeof(start_prop))));
562 _FDT((fdt_setprop(fdt, off, "linux,initrd-end",
563 &end_prop, sizeof(end_prop))));
564 }
565
566
567 for (i = 0; i < pnv->num_chips; i++) {
568 PNV_CHIP_GET_CLASS(pnv->chips[i])->dt_populate(pnv->chips[i], fdt);
569 }
570
571
572 pnv_dt_isa(pnv, fdt);
573
574 if (pnv->bmc) {
575 pnv_dt_bmc_sensors(pnv->bmc, fdt);
576 }
577
578
579 if (pmc->dt_power_mgt) {
580 pmc->dt_power_mgt(pnv, fdt);
581 }
582
583 return fdt;
584}
585
586static void pnv_powerdown_notify(Notifier *n, void *opaque)
587{
588 PnvMachineState *pnv = container_of(n, PnvMachineState, powerdown_notifier);
589
590 if (pnv->bmc) {
591 pnv_bmc_powerdown(pnv->bmc);
592 }
593}
594
595static void pnv_reset(MachineState *machine, ShutdownCause reason)
596{
597 PnvMachineState *pnv = PNV_MACHINE(machine);
598 IPMIBmc *bmc;
599 void *fdt;
600
601 qemu_devices_reset(reason);
602
603
604
605
606
607
608 bmc = pnv_bmc_find(&error_fatal);
609 if (!pnv->bmc) {
610 if (!bmc) {
611 if (!qtest_enabled()) {
612 warn_report("machine has no BMC device. Use '-device "
613 "ipmi-bmc-sim,id=bmc0 -device isa-ipmi-bt,bmc=bmc0,irq=10' "
614 "to define one");
615 }
616 } else {
617 pnv_bmc_set_pnor(bmc, pnv->pnor);
618 pnv->bmc = bmc;
619 }
620 }
621
622 fdt = pnv_dt_create(machine);
623
624
625 _FDT((fdt_pack(fdt)));
626
627 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt));
628 cpu_physical_memory_write(PNV_FDT_ADDR, fdt, fdt_totalsize(fdt));
629
630
631
632
633
634
635 g_free(machine->fdt);
636 machine->fdt = fdt;
637}
638
639static ISABus *pnv_chip_power8_isa_create(PnvChip *chip, Error **errp)
640{
641 Pnv8Chip *chip8 = PNV8_CHIP(chip);
642 qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip8->psi), PSIHB_IRQ_EXTERNAL);
643
644 qdev_connect_gpio_out(DEVICE(&chip8->lpc), 0, irq);
645 return pnv_lpc_isa_create(&chip8->lpc, true, errp);
646}
647
648static ISABus *pnv_chip_power8nvl_isa_create(PnvChip *chip, Error **errp)
649{
650 Pnv8Chip *chip8 = PNV8_CHIP(chip);
651 qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip8->psi), PSIHB_IRQ_LPC_I2C);
652
653 qdev_connect_gpio_out(DEVICE(&chip8->lpc), 0, irq);
654 return pnv_lpc_isa_create(&chip8->lpc, false, errp);
655}
656
657static ISABus *pnv_chip_power9_isa_create(PnvChip *chip, Error **errp)
658{
659 Pnv9Chip *chip9 = PNV9_CHIP(chip);
660 qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip9->psi), PSIHB9_IRQ_LPCHC);
661
662 qdev_connect_gpio_out(DEVICE(&chip9->lpc), 0, irq);
663 return pnv_lpc_isa_create(&chip9->lpc, false, errp);
664}
665
666static ISABus *pnv_chip_power10_isa_create(PnvChip *chip, Error **errp)
667{
668 Pnv10Chip *chip10 = PNV10_CHIP(chip);
669 qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip10->psi), PSIHB9_IRQ_LPCHC);
670
671 qdev_connect_gpio_out(DEVICE(&chip10->lpc), 0, irq);
672 return pnv_lpc_isa_create(&chip10->lpc, false, errp);
673}
674
675static ISABus *pnv_isa_create(PnvChip *chip, Error **errp)
676{
677 return PNV_CHIP_GET_CLASS(chip)->isa_create(chip, errp);
678}
679
680static void pnv_chip_power8_pic_print_info(PnvChip *chip, Monitor *mon)
681{
682 Pnv8Chip *chip8 = PNV8_CHIP(chip);
683 int i;
684
685 ics_pic_print_info(&chip8->psi.ics, mon);
686
687 for (i = 0; i < chip8->num_phbs; i++) {
688 PnvPHB *phb = chip8->phbs[i];
689 PnvPHB3 *phb3 = PNV_PHB3(phb->backend);
690
691 pnv_phb3_msi_pic_print_info(&phb3->msis, mon);
692 ics_pic_print_info(&phb3->lsis, mon);
693 }
694}
695
696static int pnv_chip_power9_pic_print_info_child(Object *child, void *opaque)
697{
698 Monitor *mon = opaque;
699 PnvPHB *phb = (PnvPHB *) object_dynamic_cast(child, TYPE_PNV_PHB);
700
701 if (!phb) {
702 return 0;
703 }
704
705 pnv_phb4_pic_print_info(PNV_PHB4(phb->backend), mon);
706
707 return 0;
708}
709
710static void pnv_chip_power9_pic_print_info(PnvChip *chip, Monitor *mon)
711{
712 Pnv9Chip *chip9 = PNV9_CHIP(chip);
713
714 pnv_xive_pic_print_info(&chip9->xive, mon);
715 pnv_psi_pic_print_info(&chip9->psi, mon);
716
717 object_child_foreach_recursive(OBJECT(chip),
718 pnv_chip_power9_pic_print_info_child, mon);
719}
720
721static uint64_t pnv_chip_power8_xscom_core_base(PnvChip *chip,
722 uint32_t core_id)
723{
724 return PNV_XSCOM_EX_BASE(core_id);
725}
726
727static uint64_t pnv_chip_power9_xscom_core_base(PnvChip *chip,
728 uint32_t core_id)
729{
730 return PNV9_XSCOM_EC_BASE(core_id);
731}
732
733static uint64_t pnv_chip_power10_xscom_core_base(PnvChip *chip,
734 uint32_t core_id)
735{
736 return PNV10_XSCOM_EC_BASE(core_id);
737}
738
739static bool pnv_match_cpu(const char *default_type, const char *cpu_type)
740{
741 PowerPCCPUClass *ppc_default =
742 POWERPC_CPU_CLASS(object_class_by_name(default_type));
743 PowerPCCPUClass *ppc =
744 POWERPC_CPU_CLASS(object_class_by_name(cpu_type));
745
746 return ppc_default->pvr_match(ppc_default, ppc->pvr, false);
747}
748
749static void pnv_ipmi_bt_init(ISABus *bus, IPMIBmc *bmc, uint32_t irq)
750{
751 ISADevice *dev = isa_new("isa-ipmi-bt");
752
753 object_property_set_link(OBJECT(dev), "bmc", OBJECT(bmc), &error_fatal);
754 object_property_set_int(OBJECT(dev), "irq", irq, &error_fatal);
755 isa_realize_and_unref(dev, bus, &error_fatal);
756}
757
758static void pnv_chip_power10_pic_print_info(PnvChip *chip, Monitor *mon)
759{
760 Pnv10Chip *chip10 = PNV10_CHIP(chip);
761
762 pnv_xive2_pic_print_info(&chip10->xive, mon);
763 pnv_psi_pic_print_info(&chip10->psi, mon);
764
765 object_child_foreach_recursive(OBJECT(chip),
766 pnv_chip_power9_pic_print_info_child, mon);
767}
768
769
770static uint64_t pnv_chip_get_ram_size(PnvMachineState *pnv, int chip_id)
771{
772 MachineState *machine = MACHINE(pnv);
773 uint64_t ram_per_chip;
774
775 assert(machine->ram_size >= 1 * GiB);
776
777 ram_per_chip = machine->ram_size / pnv->num_chips;
778 if (ram_per_chip >= 1 * GiB) {
779 return QEMU_ALIGN_DOWN(ram_per_chip, 1 * MiB);
780 }
781
782 assert(pnv->num_chips > 1);
783
784 ram_per_chip = (machine->ram_size - 1 * GiB) / (pnv->num_chips - 1);
785 return chip_id == 0 ? 1 * GiB : QEMU_ALIGN_DOWN(ram_per_chip, 1 * MiB);
786}
787
788static void pnv_init(MachineState *machine)
789{
790 const char *bios_name = machine->firmware ?: FW_FILE_NAME;
791 PnvMachineState *pnv = PNV_MACHINE(machine);
792 MachineClass *mc = MACHINE_GET_CLASS(machine);
793 char *fw_filename;
794 long fw_size;
795 uint64_t chip_ram_start = 0;
796 int i;
797 char *chip_typename;
798 DriveInfo *pnor = drive_get(IF_MTD, 0, 0);
799 DeviceState *dev;
800
801 if (kvm_enabled()) {
802 error_report("The powernv machine does not work with KVM acceleration");
803 exit(EXIT_FAILURE);
804 }
805
806
807 if (machine->ram_size < mc->default_ram_size) {
808 char *sz = size_to_str(mc->default_ram_size);
809 error_report("Invalid RAM size, should be bigger than %s", sz);
810 g_free(sz);
811 exit(EXIT_FAILURE);
812 }
813 memory_region_add_subregion(get_system_memory(), 0, machine->ram);
814
815
816
817
818 dev = qdev_new(TYPE_PNV_PNOR);
819 if (pnor) {
820 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(pnor));
821 }
822 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
823 pnv->pnor = PNV_PNOR(dev);
824
825
826 fw_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
827 if (!fw_filename) {
828 error_report("Could not find OPAL firmware '%s'", bios_name);
829 exit(1);
830 }
831
832 fw_size = load_image_targphys(fw_filename, pnv->fw_load_addr, FW_MAX_SIZE);
833 if (fw_size < 0) {
834 error_report("Could not load OPAL firmware '%s'", fw_filename);
835 exit(1);
836 }
837 g_free(fw_filename);
838
839
840 if (machine->kernel_filename) {
841 long kernel_size;
842
843 kernel_size = load_image_targphys(machine->kernel_filename,
844 KERNEL_LOAD_ADDR, KERNEL_MAX_SIZE);
845 if (kernel_size < 0) {
846 error_report("Could not load kernel '%s'",
847 machine->kernel_filename);
848 exit(1);
849 }
850 }
851
852
853 if (machine->initrd_filename) {
854 pnv->initrd_base = INITRD_LOAD_ADDR;
855 pnv->initrd_size = load_image_targphys(machine->initrd_filename,
856 pnv->initrd_base, INITRD_MAX_SIZE);
857 if (pnv->initrd_size < 0) {
858 error_report("Could not load initial ram disk '%s'",
859 machine->initrd_filename);
860 exit(1);
861 }
862 }
863
864
865 msi_nonbroken = true;
866
867
868
869
870
871 if (!pnv_match_cpu(mc->default_cpu_type, machine->cpu_type)) {
872 error_report("invalid CPU model '%s' for %s machine",
873 machine->cpu_type, mc->name);
874 exit(1);
875 }
876
877
878 i = strlen(machine->cpu_type) - strlen(POWERPC_CPU_TYPE_SUFFIX);
879 chip_typename = g_strdup_printf(PNV_CHIP_TYPE_NAME("%.*s"),
880 i, machine->cpu_type);
881 if (!object_class_by_name(chip_typename)) {
882 error_report("invalid chip model '%.*s' for %s machine",
883 i, machine->cpu_type, mc->name);
884 exit(1);
885 }
886
887 pnv->num_chips =
888 machine->smp.max_cpus / (machine->smp.cores * machine->smp.threads);
889
890
891
892
893 if (!is_power_of_2(pnv->num_chips) || pnv->num_chips > 16) {
894 error_report("invalid number of chips: '%d'", pnv->num_chips);
895 error_printf(
896 "Try '-smp sockets=N'. Valid values are : 1, 2, 4, 8 and 16.\n");
897 exit(1);
898 }
899
900 pnv->chips = g_new0(PnvChip *, pnv->num_chips);
901 for (i = 0; i < pnv->num_chips; i++) {
902 char chip_name[32];
903 Object *chip = OBJECT(qdev_new(chip_typename));
904 uint64_t chip_ram_size = pnv_chip_get_ram_size(pnv, i);
905
906 pnv->chips[i] = PNV_CHIP(chip);
907
908
909 object_property_set_int(chip, "ram-start", chip_ram_start,
910 &error_fatal);
911 object_property_set_int(chip, "ram-size", chip_ram_size,
912 &error_fatal);
913 chip_ram_start += chip_ram_size;
914
915 snprintf(chip_name, sizeof(chip_name), "chip[%d]", i);
916 object_property_add_child(OBJECT(pnv), chip_name, chip);
917 object_property_set_int(chip, "chip-id", i, &error_fatal);
918 object_property_set_int(chip, "nr-cores", machine->smp.cores,
919 &error_fatal);
920 object_property_set_int(chip, "nr-threads", machine->smp.threads,
921 &error_fatal);
922
923
924
925
926 if (object_dynamic_cast(OBJECT(pnv), TYPE_XICS_FABRIC)) {
927 object_property_set_link(chip, "xics", OBJECT(pnv), &error_abort);
928 }
929 if (object_dynamic_cast(OBJECT(pnv), TYPE_XIVE_FABRIC)) {
930 object_property_set_link(chip, "xive-fabric", OBJECT(pnv),
931 &error_abort);
932 }
933 sysbus_realize_and_unref(SYS_BUS_DEVICE(chip), &error_fatal);
934 }
935 g_free(chip_typename);
936
937
938 pnv->isa_bus = pnv_isa_create(pnv->chips[0], &error_fatal);
939
940
941 serial_hds_isa_init(pnv->isa_bus, 0, MAX_ISA_SERIAL_PORTS);
942
943
944 mc146818_rtc_init(pnv->isa_bus, 2000, NULL);
945
946
947
948
949
950 if (defaults_enabled()) {
951 pnv->bmc = pnv_bmc_create(pnv->pnor);
952 pnv_ipmi_bt_init(pnv->isa_bus, pnv->bmc, 10);
953 }
954
955
956
957
958
959
960 memory_region_add_subregion(pnv->chips[0]->fw_mr, PNOR_SPI_OFFSET,
961 &pnv->pnor->mmio);
962
963
964
965
966
967 pnv->powerdown_notifier.notify = pnv_powerdown_notify;
968 qemu_register_powerdown_notifier(&pnv->powerdown_notifier);
969}
970
971
972
973
974
975
976
977static uint32_t pnv_chip_core_pir_p8(PnvChip *chip, uint32_t core_id)
978{
979 return (chip->chip_id << 7) | (core_id << 3);
980}
981
982static void pnv_chip_power8_intc_create(PnvChip *chip, PowerPCCPU *cpu,
983 Error **errp)
984{
985 Pnv8Chip *chip8 = PNV8_CHIP(chip);
986 Error *local_err = NULL;
987 Object *obj;
988 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
989
990 obj = icp_create(OBJECT(cpu), TYPE_PNV_ICP, chip8->xics, &local_err);
991 if (local_err) {
992 error_propagate(errp, local_err);
993 return;
994 }
995
996 pnv_cpu->intc = obj;
997}
998
999
1000static void pnv_chip_power8_intc_reset(PnvChip *chip, PowerPCCPU *cpu)
1001{
1002 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
1003
1004 icp_reset(ICP(pnv_cpu->intc));
1005}
1006
1007static void pnv_chip_power8_intc_destroy(PnvChip *chip, PowerPCCPU *cpu)
1008{
1009 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
1010
1011 icp_destroy(ICP(pnv_cpu->intc));
1012 pnv_cpu->intc = NULL;
1013}
1014
1015static void pnv_chip_power8_intc_print_info(PnvChip *chip, PowerPCCPU *cpu,
1016 Monitor *mon)
1017{
1018 icp_pic_print_info(ICP(pnv_cpu_state(cpu)->intc), mon);
1019}
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031static uint32_t pnv_chip_core_pir_p9(PnvChip *chip, uint32_t core_id)
1032{
1033 return (chip->chip_id << 8) | (core_id << 2);
1034}
1035
1036static uint32_t pnv_chip_core_pir_p10(PnvChip *chip, uint32_t core_id)
1037{
1038 return (chip->chip_id << 8) | (core_id << 2);
1039}
1040
1041static void pnv_chip_power9_intc_create(PnvChip *chip, PowerPCCPU *cpu,
1042 Error **errp)
1043{
1044 Pnv9Chip *chip9 = PNV9_CHIP(chip);
1045 Error *local_err = NULL;
1046 Object *obj;
1047 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
1048
1049
1050
1051
1052
1053
1054 obj = xive_tctx_create(OBJECT(cpu), XIVE_PRESENTER(&chip9->xive),
1055 &local_err);
1056 if (local_err) {
1057 error_propagate(errp, local_err);
1058 return;
1059 }
1060
1061 pnv_cpu->intc = obj;
1062}
1063
1064static void pnv_chip_power9_intc_reset(PnvChip *chip, PowerPCCPU *cpu)
1065{
1066 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
1067
1068 xive_tctx_reset(XIVE_TCTX(pnv_cpu->intc));
1069}
1070
1071static void pnv_chip_power9_intc_destroy(PnvChip *chip, PowerPCCPU *cpu)
1072{
1073 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
1074
1075 xive_tctx_destroy(XIVE_TCTX(pnv_cpu->intc));
1076 pnv_cpu->intc = NULL;
1077}
1078
1079static void pnv_chip_power9_intc_print_info(PnvChip *chip, PowerPCCPU *cpu,
1080 Monitor *mon)
1081{
1082 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), mon);
1083}
1084
1085static void pnv_chip_power10_intc_create(PnvChip *chip, PowerPCCPU *cpu,
1086 Error **errp)
1087{
1088 Pnv10Chip *chip10 = PNV10_CHIP(chip);
1089 Error *local_err = NULL;
1090 Object *obj;
1091 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
1092
1093
1094
1095
1096
1097
1098 obj = xive_tctx_create(OBJECT(cpu), XIVE_PRESENTER(&chip10->xive),
1099 &local_err);
1100 if (local_err) {
1101 error_propagate(errp, local_err);
1102 return;
1103 }
1104
1105 pnv_cpu->intc = obj;
1106}
1107
1108static void pnv_chip_power10_intc_reset(PnvChip *chip, PowerPCCPU *cpu)
1109{
1110 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
1111
1112 xive_tctx_reset(XIVE_TCTX(pnv_cpu->intc));
1113}
1114
1115static void pnv_chip_power10_intc_destroy(PnvChip *chip, PowerPCCPU *cpu)
1116{
1117 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
1118
1119 xive_tctx_destroy(XIVE_TCTX(pnv_cpu->intc));
1120 pnv_cpu->intc = NULL;
1121}
1122
1123static void pnv_chip_power10_intc_print_info(PnvChip *chip, PowerPCCPU *cpu,
1124 Monitor *mon)
1125{
1126 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), mon);
1127}
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148#define POWER8E_CORE_MASK (0x7070ull)
1149#define POWER8_CORE_MASK (0x7e7eull)
1150
1151
1152
1153
1154#define POWER9_CORE_MASK (0xffffffffffffffull)
1155
1156
1157#define POWER10_CORE_MASK (0xffffffffffffffull)
1158
1159static void pnv_chip_power8_instance_init(Object *obj)
1160{
1161 Pnv8Chip *chip8 = PNV8_CHIP(obj);
1162 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj);
1163 int i;
1164
1165 object_property_add_link(obj, "xics", TYPE_XICS_FABRIC,
1166 (Object **)&chip8->xics,
1167 object_property_allow_set_link,
1168 OBJ_PROP_LINK_STRONG);
1169
1170 object_initialize_child(obj, "psi", &chip8->psi, TYPE_PNV8_PSI);
1171
1172 object_initialize_child(obj, "lpc", &chip8->lpc, TYPE_PNV8_LPC);
1173
1174 object_initialize_child(obj, "occ", &chip8->occ, TYPE_PNV8_OCC);
1175
1176 object_initialize_child(obj, "homer", &chip8->homer, TYPE_PNV8_HOMER);
1177
1178 if (defaults_enabled()) {
1179 chip8->num_phbs = pcc->num_phbs;
1180
1181 for (i = 0; i < chip8->num_phbs; i++) {
1182 Object *phb = object_new(TYPE_PNV_PHB);
1183
1184
1185
1186
1187
1188
1189
1190
1191 object_property_add_child(obj, "phb[*]", phb);
1192 chip8->phbs[i] = PNV_PHB(phb);
1193 }
1194 }
1195
1196}
1197
1198static void pnv_chip_icp_realize(Pnv8Chip *chip8, Error **errp)
1199 {
1200 PnvChip *chip = PNV_CHIP(chip8);
1201 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
1202 int i, j;
1203 char *name;
1204
1205 name = g_strdup_printf("icp-%x", chip->chip_id);
1206 memory_region_init(&chip8->icp_mmio, OBJECT(chip), name, PNV_ICP_SIZE);
1207 sysbus_init_mmio(SYS_BUS_DEVICE(chip), &chip8->icp_mmio);
1208 g_free(name);
1209
1210 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 1, PNV_ICP_BASE(chip));
1211
1212
1213 for (i = 0; i < chip->nr_cores; i++) {
1214 PnvCore *pnv_core = chip->cores[i];
1215 int core_hwid = CPU_CORE(pnv_core)->core_id;
1216
1217 for (j = 0; j < CPU_CORE(pnv_core)->nr_threads; j++) {
1218 uint32_t pir = pcc->core_pir(chip, core_hwid) + j;
1219 PnvICPState *icp = PNV_ICP(xics_icp_get(chip8->xics, pir));
1220
1221 memory_region_add_subregion(&chip8->icp_mmio, pir << 12,
1222 &icp->mmio);
1223 }
1224 }
1225}
1226
1227static void pnv_chip_power8_realize(DeviceState *dev, Error **errp)
1228{
1229 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev);
1230 PnvChip *chip = PNV_CHIP(dev);
1231 Pnv8Chip *chip8 = PNV8_CHIP(dev);
1232 Pnv8Psi *psi8 = &chip8->psi;
1233 Error *local_err = NULL;
1234 int i;
1235
1236 assert(chip8->xics);
1237
1238
1239 pnv_xscom_realize(chip, PNV_XSCOM_SIZE, &local_err);
1240 if (local_err) {
1241 error_propagate(errp, local_err);
1242 return;
1243 }
1244 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV_XSCOM_BASE(chip));
1245
1246 pcc->parent_realize(dev, &local_err);
1247 if (local_err) {
1248 error_propagate(errp, local_err);
1249 return;
1250 }
1251
1252
1253 object_property_set_int(OBJECT(&chip8->psi), "bar", PNV_PSIHB_BASE(chip),
1254 &error_fatal);
1255 object_property_set_link(OBJECT(&chip8->psi), ICS_PROP_XICS,
1256 OBJECT(chip8->xics), &error_abort);
1257 if (!qdev_realize(DEVICE(&chip8->psi), NULL, errp)) {
1258 return;
1259 }
1260 pnv_xscom_add_subregion(chip, PNV_XSCOM_PSIHB_BASE,
1261 &PNV_PSI(psi8)->xscom_regs);
1262
1263
1264 qdev_realize(DEVICE(&chip8->lpc), NULL, &error_fatal);
1265 pnv_xscom_add_subregion(chip, PNV_XSCOM_LPC_BASE, &chip8->lpc.xscom_regs);
1266
1267 chip->fw_mr = &chip8->lpc.isa_fw;
1268 chip->dt_isa_nodename = g_strdup_printf("/xscom@%" PRIx64 "/isa@%x",
1269 (uint64_t) PNV_XSCOM_BASE(chip),
1270 PNV_XSCOM_LPC_BASE);
1271
1272
1273
1274
1275
1276 pnv_chip_icp_realize(chip8, &local_err);
1277 if (local_err) {
1278 error_propagate(errp, local_err);
1279 return;
1280 }
1281
1282
1283 if (!qdev_realize(DEVICE(&chip8->occ), NULL, errp)) {
1284 return;
1285 }
1286 pnv_xscom_add_subregion(chip, PNV_XSCOM_OCC_BASE, &chip8->occ.xscom_regs);
1287 qdev_connect_gpio_out(DEVICE(&chip8->occ), 0,
1288 qdev_get_gpio_in(DEVICE(&chip8->psi), PSIHB_IRQ_OCC));
1289
1290
1291 memory_region_add_subregion(get_system_memory(), PNV_OCC_SENSOR_BASE(chip),
1292 &chip8->occ.sram_regs);
1293
1294
1295 object_property_set_link(OBJECT(&chip8->homer), "chip", OBJECT(chip),
1296 &error_abort);
1297 if (!qdev_realize(DEVICE(&chip8->homer), NULL, errp)) {
1298 return;
1299 }
1300
1301 pnv_xscom_add_subregion(chip, PNV_XSCOM_PBA_BASE, &chip8->homer.pba_regs);
1302
1303
1304 memory_region_add_subregion(get_system_memory(), PNV_HOMER_BASE(chip),
1305 &chip8->homer.regs);
1306
1307
1308 for (i = 0; i < chip8->num_phbs; i++) {
1309 PnvPHB *phb = chip8->phbs[i];
1310
1311 object_property_set_int(OBJECT(phb), "index", i, &error_fatal);
1312 object_property_set_int(OBJECT(phb), "chip-id", chip->chip_id,
1313 &error_fatal);
1314 object_property_set_link(OBJECT(phb), "chip", OBJECT(chip),
1315 &error_fatal);
1316 if (!sysbus_realize(SYS_BUS_DEVICE(phb), errp)) {
1317 return;
1318 }
1319 }
1320}
1321
1322static uint32_t pnv_chip_power8_xscom_pcba(PnvChip *chip, uint64_t addr)
1323{
1324 addr &= (PNV_XSCOM_SIZE - 1);
1325 return ((addr >> 4) & ~0xfull) | ((addr >> 3) & 0xf);
1326}
1327
1328static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data)
1329{
1330 DeviceClass *dc = DEVICE_CLASS(klass);
1331 PnvChipClass *k = PNV_CHIP_CLASS(klass);
1332
1333 k->chip_cfam_id = 0x221ef04980000000ull;
1334 k->cores_mask = POWER8E_CORE_MASK;
1335 k->num_phbs = 3;
1336 k->core_pir = pnv_chip_core_pir_p8;
1337 k->intc_create = pnv_chip_power8_intc_create;
1338 k->intc_reset = pnv_chip_power8_intc_reset;
1339 k->intc_destroy = pnv_chip_power8_intc_destroy;
1340 k->intc_print_info = pnv_chip_power8_intc_print_info;
1341 k->isa_create = pnv_chip_power8_isa_create;
1342 k->dt_populate = pnv_chip_power8_dt_populate;
1343 k->pic_print_info = pnv_chip_power8_pic_print_info;
1344 k->xscom_core_base = pnv_chip_power8_xscom_core_base;
1345 k->xscom_pcba = pnv_chip_power8_xscom_pcba;
1346 dc->desc = "PowerNV Chip POWER8E";
1347
1348 device_class_set_parent_realize(dc, pnv_chip_power8_realize,
1349 &k->parent_realize);
1350}
1351
1352static void pnv_chip_power8_class_init(ObjectClass *klass, void *data)
1353{
1354 DeviceClass *dc = DEVICE_CLASS(klass);
1355 PnvChipClass *k = PNV_CHIP_CLASS(klass);
1356
1357 k->chip_cfam_id = 0x220ea04980000000ull;
1358 k->cores_mask = POWER8_CORE_MASK;
1359 k->num_phbs = 3;
1360 k->core_pir = pnv_chip_core_pir_p8;
1361 k->intc_create = pnv_chip_power8_intc_create;
1362 k->intc_reset = pnv_chip_power8_intc_reset;
1363 k->intc_destroy = pnv_chip_power8_intc_destroy;
1364 k->intc_print_info = pnv_chip_power8_intc_print_info;
1365 k->isa_create = pnv_chip_power8_isa_create;
1366 k->dt_populate = pnv_chip_power8_dt_populate;
1367 k->pic_print_info = pnv_chip_power8_pic_print_info;
1368 k->xscom_core_base = pnv_chip_power8_xscom_core_base;
1369 k->xscom_pcba = pnv_chip_power8_xscom_pcba;
1370 dc->desc = "PowerNV Chip POWER8";
1371
1372 device_class_set_parent_realize(dc, pnv_chip_power8_realize,
1373 &k->parent_realize);
1374}
1375
1376static void pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data)
1377{
1378 DeviceClass *dc = DEVICE_CLASS(klass);
1379 PnvChipClass *k = PNV_CHIP_CLASS(klass);
1380
1381 k->chip_cfam_id = 0x120d304980000000ull;
1382 k->cores_mask = POWER8_CORE_MASK;
1383 k->num_phbs = 4;
1384 k->core_pir = pnv_chip_core_pir_p8;
1385 k->intc_create = pnv_chip_power8_intc_create;
1386 k->intc_reset = pnv_chip_power8_intc_reset;
1387 k->intc_destroy = pnv_chip_power8_intc_destroy;
1388 k->intc_print_info = pnv_chip_power8_intc_print_info;
1389 k->isa_create = pnv_chip_power8nvl_isa_create;
1390 k->dt_populate = pnv_chip_power8_dt_populate;
1391 k->pic_print_info = pnv_chip_power8_pic_print_info;
1392 k->xscom_core_base = pnv_chip_power8_xscom_core_base;
1393 k->xscom_pcba = pnv_chip_power8_xscom_pcba;
1394 dc->desc = "PowerNV Chip POWER8NVL";
1395
1396 device_class_set_parent_realize(dc, pnv_chip_power8_realize,
1397 &k->parent_realize);
1398}
1399
1400static void pnv_chip_power9_instance_init(Object *obj)
1401{
1402 PnvChip *chip = PNV_CHIP(obj);
1403 Pnv9Chip *chip9 = PNV9_CHIP(obj);
1404 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj);
1405 int i;
1406
1407 object_initialize_child(obj, "xive", &chip9->xive, TYPE_PNV_XIVE);
1408 object_property_add_alias(obj, "xive-fabric", OBJECT(&chip9->xive),
1409 "xive-fabric");
1410
1411 object_initialize_child(obj, "psi", &chip9->psi, TYPE_PNV9_PSI);
1412
1413 object_initialize_child(obj, "lpc", &chip9->lpc, TYPE_PNV9_LPC);
1414
1415 object_initialize_child(obj, "occ", &chip9->occ, TYPE_PNV9_OCC);
1416
1417 object_initialize_child(obj, "sbe", &chip9->sbe, TYPE_PNV9_SBE);
1418
1419 object_initialize_child(obj, "homer", &chip9->homer, TYPE_PNV9_HOMER);
1420
1421
1422 chip->num_pecs = pcc->num_pecs;
1423
1424 for (i = 0; i < chip->num_pecs; i++) {
1425 object_initialize_child(obj, "pec[*]", &chip9->pecs[i],
1426 TYPE_PNV_PHB4_PEC);
1427 }
1428}
1429
1430static void pnv_chip_quad_realize_one(PnvChip *chip, PnvQuad *eq,
1431 PnvCore *pnv_core)
1432{
1433 char eq_name[32];
1434 int core_id = CPU_CORE(pnv_core)->core_id;
1435
1436 snprintf(eq_name, sizeof(eq_name), "eq[%d]", core_id);
1437 object_initialize_child_with_props(OBJECT(chip), eq_name, eq,
1438 sizeof(*eq), TYPE_PNV_QUAD,
1439 &error_fatal, NULL);
1440
1441 object_property_set_int(OBJECT(eq), "quad-id", core_id, &error_fatal);
1442 qdev_realize(DEVICE(eq), NULL, &error_fatal);
1443}
1444
1445static void pnv_chip_quad_realize(Pnv9Chip *chip9, Error **errp)
1446{
1447 PnvChip *chip = PNV_CHIP(chip9);
1448 int i;
1449
1450 chip9->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4);
1451 chip9->quads = g_new0(PnvQuad, chip9->nr_quads);
1452
1453 for (i = 0; i < chip9->nr_quads; i++) {
1454 PnvQuad *eq = &chip9->quads[i];
1455
1456 pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4]);
1457
1458 pnv_xscom_add_subregion(chip, PNV9_XSCOM_EQ_BASE(eq->quad_id),
1459 &eq->xscom_regs);
1460 }
1461}
1462
1463static void pnv_chip_power9_pec_realize(PnvChip *chip, Error **errp)
1464{
1465 Pnv9Chip *chip9 = PNV9_CHIP(chip);
1466 int i;
1467
1468 for (i = 0; i < chip->num_pecs; i++) {
1469 PnvPhb4PecState *pec = &chip9->pecs[i];
1470 PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec);
1471 uint32_t pec_nest_base;
1472 uint32_t pec_pci_base;
1473
1474 object_property_set_int(OBJECT(pec), "index", i, &error_fatal);
1475 object_property_set_int(OBJECT(pec), "chip-id", chip->chip_id,
1476 &error_fatal);
1477 object_property_set_link(OBJECT(pec), "chip", OBJECT(chip),
1478 &error_fatal);
1479 if (!qdev_realize(DEVICE(pec), NULL, errp)) {
1480 return;
1481 }
1482
1483 pec_nest_base = pecc->xscom_nest_base(pec);
1484 pec_pci_base = pecc->xscom_pci_base(pec);
1485
1486 pnv_xscom_add_subregion(chip, pec_nest_base, &pec->nest_regs_mr);
1487 pnv_xscom_add_subregion(chip, pec_pci_base, &pec->pci_regs_mr);
1488 }
1489}
1490
1491static void pnv_chip_power9_realize(DeviceState *dev, Error **errp)
1492{
1493 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev);
1494 Pnv9Chip *chip9 = PNV9_CHIP(dev);
1495 PnvChip *chip = PNV_CHIP(dev);
1496 Pnv9Psi *psi9 = &chip9->psi;
1497 Error *local_err = NULL;
1498
1499
1500 pnv_xscom_realize(chip, PNV9_XSCOM_SIZE, &local_err);
1501 if (local_err) {
1502 error_propagate(errp, local_err);
1503 return;
1504 }
1505 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV9_XSCOM_BASE(chip));
1506
1507 pcc->parent_realize(dev, &local_err);
1508 if (local_err) {
1509 error_propagate(errp, local_err);
1510 return;
1511 }
1512
1513 pnv_chip_quad_realize(chip9, &local_err);
1514 if (local_err) {
1515 error_propagate(errp, local_err);
1516 return;
1517 }
1518
1519
1520 object_property_set_int(OBJECT(&chip9->xive), "ic-bar",
1521 PNV9_XIVE_IC_BASE(chip), &error_fatal);
1522 object_property_set_int(OBJECT(&chip9->xive), "vc-bar",
1523 PNV9_XIVE_VC_BASE(chip), &error_fatal);
1524 object_property_set_int(OBJECT(&chip9->xive), "pc-bar",
1525 PNV9_XIVE_PC_BASE(chip), &error_fatal);
1526 object_property_set_int(OBJECT(&chip9->xive), "tm-bar",
1527 PNV9_XIVE_TM_BASE(chip), &error_fatal);
1528 object_property_set_link(OBJECT(&chip9->xive), "chip", OBJECT(chip),
1529 &error_abort);
1530 if (!sysbus_realize(SYS_BUS_DEVICE(&chip9->xive), errp)) {
1531 return;
1532 }
1533 pnv_xscom_add_subregion(chip, PNV9_XSCOM_XIVE_BASE,
1534 &chip9->xive.xscom_regs);
1535
1536
1537 object_property_set_int(OBJECT(&chip9->psi), "bar", PNV9_PSIHB_BASE(chip),
1538 &error_fatal);
1539
1540 object_property_set_int(OBJECT(&chip9->psi), "shift", XIVE_ESB_4K,
1541 &error_fatal);
1542 if (!qdev_realize(DEVICE(&chip9->psi), NULL, errp)) {
1543 return;
1544 }
1545 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PSIHB_BASE,
1546 &PNV_PSI(psi9)->xscom_regs);
1547
1548
1549 if (!qdev_realize(DEVICE(&chip9->lpc), NULL, errp)) {
1550 return;
1551 }
1552 memory_region_add_subregion(get_system_memory(), PNV9_LPCM_BASE(chip),
1553 &chip9->lpc.xscom_regs);
1554
1555 chip->fw_mr = &chip9->lpc.isa_fw;
1556 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0",
1557 (uint64_t) PNV9_LPCM_BASE(chip));
1558
1559
1560 if (!qdev_realize(DEVICE(&chip9->occ), NULL, errp)) {
1561 return;
1562 }
1563 pnv_xscom_add_subregion(chip, PNV9_XSCOM_OCC_BASE, &chip9->occ.xscom_regs);
1564 qdev_connect_gpio_out(DEVICE(&chip9->occ), 0, qdev_get_gpio_in(
1565 DEVICE(&chip9->psi), PSIHB9_IRQ_OCC));
1566
1567
1568 memory_region_add_subregion(get_system_memory(), PNV9_OCC_SENSOR_BASE(chip),
1569 &chip9->occ.sram_regs);
1570
1571
1572 if (!qdev_realize(DEVICE(&chip9->sbe), NULL, errp)) {
1573 return;
1574 }
1575 pnv_xscom_add_subregion(chip, PNV9_XSCOM_SBE_CTRL_BASE,
1576 &chip9->sbe.xscom_ctrl_regs);
1577 pnv_xscom_add_subregion(chip, PNV9_XSCOM_SBE_MBOX_BASE,
1578 &chip9->sbe.xscom_mbox_regs);
1579 qdev_connect_gpio_out(DEVICE(&chip9->sbe), 0, qdev_get_gpio_in(
1580 DEVICE(&chip9->psi), PSIHB9_IRQ_PSU));
1581
1582
1583 object_property_set_link(OBJECT(&chip9->homer), "chip", OBJECT(chip),
1584 &error_abort);
1585 if (!qdev_realize(DEVICE(&chip9->homer), NULL, errp)) {
1586 return;
1587 }
1588
1589 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PBA_BASE, &chip9->homer.pba_regs);
1590
1591
1592 memory_region_add_subregion(get_system_memory(), PNV9_HOMER_BASE(chip),
1593 &chip9->homer.regs);
1594
1595
1596 pnv_chip_power9_pec_realize(chip, &local_err);
1597 if (local_err) {
1598 error_propagate(errp, local_err);
1599 return;
1600 }
1601}
1602
1603static uint32_t pnv_chip_power9_xscom_pcba(PnvChip *chip, uint64_t addr)
1604{
1605 addr &= (PNV9_XSCOM_SIZE - 1);
1606 return addr >> 3;
1607}
1608
1609static void pnv_chip_power9_class_init(ObjectClass *klass, void *data)
1610{
1611 DeviceClass *dc = DEVICE_CLASS(klass);
1612 PnvChipClass *k = PNV_CHIP_CLASS(klass);
1613
1614 k->chip_cfam_id = 0x220d104900008000ull;
1615 k->cores_mask = POWER9_CORE_MASK;
1616 k->core_pir = pnv_chip_core_pir_p9;
1617 k->intc_create = pnv_chip_power9_intc_create;
1618 k->intc_reset = pnv_chip_power9_intc_reset;
1619 k->intc_destroy = pnv_chip_power9_intc_destroy;
1620 k->intc_print_info = pnv_chip_power9_intc_print_info;
1621 k->isa_create = pnv_chip_power9_isa_create;
1622 k->dt_populate = pnv_chip_power9_dt_populate;
1623 k->pic_print_info = pnv_chip_power9_pic_print_info;
1624 k->xscom_core_base = pnv_chip_power9_xscom_core_base;
1625 k->xscom_pcba = pnv_chip_power9_xscom_pcba;
1626 dc->desc = "PowerNV Chip POWER9";
1627 k->num_pecs = PNV9_CHIP_MAX_PEC;
1628
1629 device_class_set_parent_realize(dc, pnv_chip_power9_realize,
1630 &k->parent_realize);
1631}
1632
1633static void pnv_chip_power10_instance_init(Object *obj)
1634{
1635 PnvChip *chip = PNV_CHIP(obj);
1636 Pnv10Chip *chip10 = PNV10_CHIP(obj);
1637 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj);
1638 int i;
1639
1640 object_initialize_child(obj, "xive", &chip10->xive, TYPE_PNV_XIVE2);
1641 object_property_add_alias(obj, "xive-fabric", OBJECT(&chip10->xive),
1642 "xive-fabric");
1643 object_initialize_child(obj, "psi", &chip10->psi, TYPE_PNV10_PSI);
1644 object_initialize_child(obj, "lpc", &chip10->lpc, TYPE_PNV10_LPC);
1645 object_initialize_child(obj, "occ", &chip10->occ, TYPE_PNV10_OCC);
1646 object_initialize_child(obj, "sbe", &chip10->sbe, TYPE_PNV10_SBE);
1647 object_initialize_child(obj, "homer", &chip10->homer, TYPE_PNV10_HOMER);
1648
1649 chip->num_pecs = pcc->num_pecs;
1650
1651 for (i = 0; i < chip->num_pecs; i++) {
1652 object_initialize_child(obj, "pec[*]", &chip10->pecs[i],
1653 TYPE_PNV_PHB5_PEC);
1654 }
1655}
1656
1657static void pnv_chip_power10_quad_realize(Pnv10Chip *chip10, Error **errp)
1658{
1659 PnvChip *chip = PNV_CHIP(chip10);
1660 int i;
1661
1662 chip10->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4);
1663 chip10->quads = g_new0(PnvQuad, chip10->nr_quads);
1664
1665 for (i = 0; i < chip10->nr_quads; i++) {
1666 PnvQuad *eq = &chip10->quads[i];
1667
1668 pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4]);
1669
1670 pnv_xscom_add_subregion(chip, PNV10_XSCOM_EQ_BASE(eq->quad_id),
1671 &eq->xscom_regs);
1672 }
1673}
1674
1675static void pnv_chip_power10_phb_realize(PnvChip *chip, Error **errp)
1676{
1677 Pnv10Chip *chip10 = PNV10_CHIP(chip);
1678 int i;
1679
1680 for (i = 0; i < chip->num_pecs; i++) {
1681 PnvPhb4PecState *pec = &chip10->pecs[i];
1682 PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec);
1683 uint32_t pec_nest_base;
1684 uint32_t pec_pci_base;
1685
1686 object_property_set_int(OBJECT(pec), "index", i, &error_fatal);
1687 object_property_set_int(OBJECT(pec), "chip-id", chip->chip_id,
1688 &error_fatal);
1689 object_property_set_link(OBJECT(pec), "chip", OBJECT(chip),
1690 &error_fatal);
1691 if (!qdev_realize(DEVICE(pec), NULL, errp)) {
1692 return;
1693 }
1694
1695 pec_nest_base = pecc->xscom_nest_base(pec);
1696 pec_pci_base = pecc->xscom_pci_base(pec);
1697
1698 pnv_xscom_add_subregion(chip, pec_nest_base, &pec->nest_regs_mr);
1699 pnv_xscom_add_subregion(chip, pec_pci_base, &pec->pci_regs_mr);
1700 }
1701}
1702
1703static void pnv_chip_power10_realize(DeviceState *dev, Error **errp)
1704{
1705 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev);
1706 PnvChip *chip = PNV_CHIP(dev);
1707 Pnv10Chip *chip10 = PNV10_CHIP(dev);
1708 Error *local_err = NULL;
1709
1710
1711 pnv_xscom_realize(chip, PNV10_XSCOM_SIZE, &local_err);
1712 if (local_err) {
1713 error_propagate(errp, local_err);
1714 return;
1715 }
1716 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV10_XSCOM_BASE(chip));
1717
1718 pcc->parent_realize(dev, &local_err);
1719 if (local_err) {
1720 error_propagate(errp, local_err);
1721 return;
1722 }
1723
1724 pnv_chip_power10_quad_realize(chip10, &local_err);
1725 if (local_err) {
1726 error_propagate(errp, local_err);
1727 return;
1728 }
1729
1730
1731 object_property_set_int(OBJECT(&chip10->xive), "ic-bar",
1732 PNV10_XIVE2_IC_BASE(chip), &error_fatal);
1733 object_property_set_int(OBJECT(&chip10->xive), "esb-bar",
1734 PNV10_XIVE2_ESB_BASE(chip), &error_fatal);
1735 object_property_set_int(OBJECT(&chip10->xive), "end-bar",
1736 PNV10_XIVE2_END_BASE(chip), &error_fatal);
1737 object_property_set_int(OBJECT(&chip10->xive), "nvpg-bar",
1738 PNV10_XIVE2_NVPG_BASE(chip), &error_fatal);
1739 object_property_set_int(OBJECT(&chip10->xive), "nvc-bar",
1740 PNV10_XIVE2_NVC_BASE(chip), &error_fatal);
1741 object_property_set_int(OBJECT(&chip10->xive), "tm-bar",
1742 PNV10_XIVE2_TM_BASE(chip), &error_fatal);
1743 object_property_set_link(OBJECT(&chip10->xive), "chip", OBJECT(chip),
1744 &error_abort);
1745 if (!sysbus_realize(SYS_BUS_DEVICE(&chip10->xive), errp)) {
1746 return;
1747 }
1748 pnv_xscom_add_subregion(chip, PNV10_XSCOM_XIVE2_BASE,
1749 &chip10->xive.xscom_regs);
1750
1751
1752 object_property_set_int(OBJECT(&chip10->psi), "bar",
1753 PNV10_PSIHB_BASE(chip), &error_fatal);
1754
1755 object_property_set_int(OBJECT(&chip10->psi), "shift", XIVE_ESB_64K,
1756 &error_fatal);
1757 if (!qdev_realize(DEVICE(&chip10->psi), NULL, errp)) {
1758 return;
1759 }
1760 pnv_xscom_add_subregion(chip, PNV10_XSCOM_PSIHB_BASE,
1761 &PNV_PSI(&chip10->psi)->xscom_regs);
1762
1763
1764 if (!qdev_realize(DEVICE(&chip10->lpc), NULL, errp)) {
1765 return;
1766 }
1767 memory_region_add_subregion(get_system_memory(), PNV10_LPCM_BASE(chip),
1768 &chip10->lpc.xscom_regs);
1769
1770 chip->fw_mr = &chip10->lpc.isa_fw;
1771 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0",
1772 (uint64_t) PNV10_LPCM_BASE(chip));
1773
1774
1775 if (!qdev_realize(DEVICE(&chip10->occ), NULL, errp)) {
1776 return;
1777 }
1778 pnv_xscom_add_subregion(chip, PNV10_XSCOM_OCC_BASE,
1779 &chip10->occ.xscom_regs);
1780 qdev_connect_gpio_out(DEVICE(&chip10->occ), 0, qdev_get_gpio_in(
1781 DEVICE(&chip10->psi), PSIHB9_IRQ_OCC));
1782
1783
1784 memory_region_add_subregion(get_system_memory(),
1785 PNV10_OCC_SENSOR_BASE(chip),
1786 &chip10->occ.sram_regs);
1787
1788
1789 if (!qdev_realize(DEVICE(&chip10->sbe), NULL, errp)) {
1790 return;
1791 }
1792 pnv_xscom_add_subregion(chip, PNV10_XSCOM_SBE_CTRL_BASE,
1793 &chip10->sbe.xscom_ctrl_regs);
1794 pnv_xscom_add_subregion(chip, PNV10_XSCOM_SBE_MBOX_BASE,
1795 &chip10->sbe.xscom_mbox_regs);
1796 qdev_connect_gpio_out(DEVICE(&chip10->sbe), 0, qdev_get_gpio_in(
1797 DEVICE(&chip10->psi), PSIHB9_IRQ_PSU));
1798
1799
1800 object_property_set_link(OBJECT(&chip10->homer), "chip", OBJECT(chip),
1801 &error_abort);
1802 if (!qdev_realize(DEVICE(&chip10->homer), NULL, errp)) {
1803 return;
1804 }
1805
1806 pnv_xscom_add_subregion(chip, PNV10_XSCOM_PBA_BASE,
1807 &chip10->homer.pba_regs);
1808
1809
1810 memory_region_add_subregion(get_system_memory(), PNV10_HOMER_BASE(chip),
1811 &chip10->homer.regs);
1812
1813
1814 pnv_chip_power10_phb_realize(chip, &local_err);
1815 if (local_err) {
1816 error_propagate(errp, local_err);
1817 return;
1818 }
1819}
1820
1821static uint32_t pnv_chip_power10_xscom_pcba(PnvChip *chip, uint64_t addr)
1822{
1823 addr &= (PNV10_XSCOM_SIZE - 1);
1824 return addr >> 3;
1825}
1826
1827static void pnv_chip_power10_class_init(ObjectClass *klass, void *data)
1828{
1829 DeviceClass *dc = DEVICE_CLASS(klass);
1830 PnvChipClass *k = PNV_CHIP_CLASS(klass);
1831
1832 k->chip_cfam_id = 0x120da04900008000ull;
1833 k->cores_mask = POWER10_CORE_MASK;
1834 k->core_pir = pnv_chip_core_pir_p10;
1835 k->intc_create = pnv_chip_power10_intc_create;
1836 k->intc_reset = pnv_chip_power10_intc_reset;
1837 k->intc_destroy = pnv_chip_power10_intc_destroy;
1838 k->intc_print_info = pnv_chip_power10_intc_print_info;
1839 k->isa_create = pnv_chip_power10_isa_create;
1840 k->dt_populate = pnv_chip_power10_dt_populate;
1841 k->pic_print_info = pnv_chip_power10_pic_print_info;
1842 k->xscom_core_base = pnv_chip_power10_xscom_core_base;
1843 k->xscom_pcba = pnv_chip_power10_xscom_pcba;
1844 dc->desc = "PowerNV Chip POWER10";
1845 k->num_pecs = PNV10_CHIP_MAX_PEC;
1846
1847 device_class_set_parent_realize(dc, pnv_chip_power10_realize,
1848 &k->parent_realize);
1849}
1850
1851static void pnv_chip_core_sanitize(PnvChip *chip, Error **errp)
1852{
1853 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
1854 int cores_max;
1855
1856
1857
1858
1859
1860 if (!chip->cores_mask) {
1861 chip->cores_mask = pcc->cores_mask;
1862 }
1863
1864
1865 if ((chip->cores_mask & pcc->cores_mask) != chip->cores_mask) {
1866 error_setg(errp, "warning: invalid core mask for chip Ox%"PRIx64" !",
1867 chip->cores_mask);
1868 return;
1869 }
1870 chip->cores_mask &= pcc->cores_mask;
1871
1872
1873 cores_max = ctpop64(chip->cores_mask);
1874 if (chip->nr_cores > cores_max) {
1875 error_setg(errp, "warning: too many cores for chip ! Limit is %d",
1876 cores_max);
1877 return;
1878 }
1879}
1880
1881static void pnv_chip_core_realize(PnvChip *chip, Error **errp)
1882{
1883 Error *error = NULL;
1884 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
1885 const char *typename = pnv_chip_core_typename(chip);
1886 int i, core_hwid;
1887 PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine());
1888
1889 if (!object_class_by_name(typename)) {
1890 error_setg(errp, "Unable to find PowerNV CPU Core '%s'", typename);
1891 return;
1892 }
1893
1894
1895 pnv_chip_core_sanitize(chip, &error);
1896 if (error) {
1897 error_propagate(errp, error);
1898 return;
1899 }
1900
1901 chip->cores = g_new0(PnvCore *, chip->nr_cores);
1902
1903 for (i = 0, core_hwid = 0; (core_hwid < sizeof(chip->cores_mask) * 8)
1904 && (i < chip->nr_cores); core_hwid++) {
1905 char core_name[32];
1906 PnvCore *pnv_core;
1907 uint64_t xscom_core_base;
1908
1909 if (!(chip->cores_mask & (1ull << core_hwid))) {
1910 continue;
1911 }
1912
1913 pnv_core = PNV_CORE(object_new(typename));
1914
1915 snprintf(core_name, sizeof(core_name), "core[%d]", core_hwid);
1916 object_property_add_child(OBJECT(chip), core_name, OBJECT(pnv_core));
1917 chip->cores[i] = pnv_core;
1918 object_property_set_int(OBJECT(pnv_core), "nr-threads",
1919 chip->nr_threads, &error_fatal);
1920 object_property_set_int(OBJECT(pnv_core), CPU_CORE_PROP_CORE_ID,
1921 core_hwid, &error_fatal);
1922 object_property_set_int(OBJECT(pnv_core), "pir",
1923 pcc->core_pir(chip, core_hwid), &error_fatal);
1924 object_property_set_int(OBJECT(pnv_core), "hrmor", pnv->fw_load_addr,
1925 &error_fatal);
1926 object_property_set_link(OBJECT(pnv_core), "chip", OBJECT(chip),
1927 &error_abort);
1928 qdev_realize(DEVICE(pnv_core), NULL, &error_fatal);
1929
1930
1931 xscom_core_base = pcc->xscom_core_base(chip, core_hwid);
1932
1933 pnv_xscom_add_subregion(chip, xscom_core_base,
1934 &pnv_core->xscom_regs);
1935 i++;
1936 }
1937}
1938
1939static void pnv_chip_realize(DeviceState *dev, Error **errp)
1940{
1941 PnvChip *chip = PNV_CHIP(dev);
1942 Error *error = NULL;
1943
1944
1945 pnv_chip_core_realize(chip, &error);
1946 if (error) {
1947 error_propagate(errp, error);
1948 return;
1949 }
1950}
1951
1952static Property pnv_chip_properties[] = {
1953 DEFINE_PROP_UINT32("chip-id", PnvChip, chip_id, 0),
1954 DEFINE_PROP_UINT64("ram-start", PnvChip, ram_start, 0),
1955 DEFINE_PROP_UINT64("ram-size", PnvChip, ram_size, 0),
1956 DEFINE_PROP_UINT32("nr-cores", PnvChip, nr_cores, 1),
1957 DEFINE_PROP_UINT64("cores-mask", PnvChip, cores_mask, 0x0),
1958 DEFINE_PROP_UINT32("nr-threads", PnvChip, nr_threads, 1),
1959 DEFINE_PROP_END_OF_LIST(),
1960};
1961
1962static void pnv_chip_class_init(ObjectClass *klass, void *data)
1963{
1964 DeviceClass *dc = DEVICE_CLASS(klass);
1965
1966 set_bit(DEVICE_CATEGORY_CPU, dc->categories);
1967 dc->realize = pnv_chip_realize;
1968 device_class_set_props(dc, pnv_chip_properties);
1969 dc->desc = "PowerNV Chip";
1970}
1971
1972PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir)
1973{
1974 int i, j;
1975
1976 for (i = 0; i < chip->nr_cores; i++) {
1977 PnvCore *pc = chip->cores[i];
1978 CPUCore *cc = CPU_CORE(pc);
1979
1980 for (j = 0; j < cc->nr_threads; j++) {
1981 if (ppc_cpu_pir(pc->threads[j]) == pir) {
1982 return pc->threads[j];
1983 }
1984 }
1985 }
1986 return NULL;
1987}
1988
1989static ICSState *pnv_ics_get(XICSFabric *xi, int irq)
1990{
1991 PnvMachineState *pnv = PNV_MACHINE(xi);
1992 int i, j;
1993
1994 for (i = 0; i < pnv->num_chips; i++) {
1995 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]);
1996
1997 if (ics_valid_irq(&chip8->psi.ics, irq)) {
1998 return &chip8->psi.ics;
1999 }
2000
2001 for (j = 0; j < chip8->num_phbs; j++) {
2002 PnvPHB *phb = chip8->phbs[j];
2003 PnvPHB3 *phb3 = PNV_PHB3(phb->backend);
2004
2005 if (ics_valid_irq(&phb3->lsis, irq)) {
2006 return &phb3->lsis;
2007 }
2008
2009 if (ics_valid_irq(ICS(&phb3->msis), irq)) {
2010 return ICS(&phb3->msis);
2011 }
2012 }
2013 }
2014 return NULL;
2015}
2016
2017PnvChip *pnv_get_chip(PnvMachineState *pnv, uint32_t chip_id)
2018{
2019 int i;
2020
2021 for (i = 0; i < pnv->num_chips; i++) {
2022 PnvChip *chip = pnv->chips[i];
2023 if (chip->chip_id == chip_id) {
2024 return chip;
2025 }
2026 }
2027 return NULL;
2028}
2029
2030static void pnv_ics_resend(XICSFabric *xi)
2031{
2032 PnvMachineState *pnv = PNV_MACHINE(xi);
2033 int i, j;
2034
2035 for (i = 0; i < pnv->num_chips; i++) {
2036 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]);
2037
2038 ics_resend(&chip8->psi.ics);
2039
2040 for (j = 0; j < chip8->num_phbs; j++) {
2041 PnvPHB *phb = chip8->phbs[j];
2042 PnvPHB3 *phb3 = PNV_PHB3(phb->backend);
2043
2044 ics_resend(&phb3->lsis);
2045 ics_resend(ICS(&phb3->msis));
2046 }
2047 }
2048}
2049
2050static ICPState *pnv_icp_get(XICSFabric *xi, int pir)
2051{
2052 PowerPCCPU *cpu = ppc_get_vcpu_by_pir(pir);
2053
2054 return cpu ? ICP(pnv_cpu_state(cpu)->intc) : NULL;
2055}
2056
2057static void pnv_pic_print_info(InterruptStatsProvider *obj,
2058 Monitor *mon)
2059{
2060 PnvMachineState *pnv = PNV_MACHINE(obj);
2061 int i;
2062 CPUState *cs;
2063
2064 CPU_FOREACH(cs) {
2065 PowerPCCPU *cpu = POWERPC_CPU(cs);
2066
2067
2068 PNV_CHIP_GET_CLASS(pnv->chips[0])->intc_print_info(pnv->chips[0], cpu,
2069 mon);
2070 }
2071
2072 for (i = 0; i < pnv->num_chips; i++) {
2073 PNV_CHIP_GET_CLASS(pnv->chips[i])->pic_print_info(pnv->chips[i], mon);
2074 }
2075}
2076
2077static int pnv_match_nvt(XiveFabric *xfb, uint8_t format,
2078 uint8_t nvt_blk, uint32_t nvt_idx,
2079 bool cam_ignore, uint8_t priority,
2080 uint32_t logic_serv,
2081 XiveTCTXMatch *match)
2082{
2083 PnvMachineState *pnv = PNV_MACHINE(xfb);
2084 int total_count = 0;
2085 int i;
2086
2087 for (i = 0; i < pnv->num_chips; i++) {
2088 Pnv9Chip *chip9 = PNV9_CHIP(pnv->chips[i]);
2089 XivePresenter *xptr = XIVE_PRESENTER(&chip9->xive);
2090 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr);
2091 int count;
2092
2093 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore,
2094 priority, logic_serv, match);
2095
2096 if (count < 0) {
2097 return count;
2098 }
2099
2100 total_count += count;
2101 }
2102
2103 return total_count;
2104}
2105
2106static int pnv10_xive_match_nvt(XiveFabric *xfb, uint8_t format,
2107 uint8_t nvt_blk, uint32_t nvt_idx,
2108 bool cam_ignore, uint8_t priority,
2109 uint32_t logic_serv,
2110 XiveTCTXMatch *match)
2111{
2112 PnvMachineState *pnv = PNV_MACHINE(xfb);
2113 int total_count = 0;
2114 int i;
2115
2116 for (i = 0; i < pnv->num_chips; i++) {
2117 Pnv10Chip *chip10 = PNV10_CHIP(pnv->chips[i]);
2118 XivePresenter *xptr = XIVE_PRESENTER(&chip10->xive);
2119 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr);
2120 int count;
2121
2122 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore,
2123 priority, logic_serv, match);
2124
2125 if (count < 0) {
2126 return count;
2127 }
2128
2129 total_count += count;
2130 }
2131
2132 return total_count;
2133}
2134
2135static void pnv_machine_power8_class_init(ObjectClass *oc, void *data)
2136{
2137 MachineClass *mc = MACHINE_CLASS(oc);
2138 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc);
2139 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc);
2140 static const char compat[] = "qemu,powernv8\0qemu,powernv\0ibm,powernv";
2141
2142 static GlobalProperty phb_compat[] = {
2143 { TYPE_PNV_PHB, "version", "3" },
2144 { TYPE_PNV_PHB_ROOT_PORT, "version", "3" },
2145 };
2146
2147 mc->desc = "IBM PowerNV (Non-Virtualized) POWER8";
2148 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0");
2149 compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat));
2150
2151 xic->icp_get = pnv_icp_get;
2152 xic->ics_get = pnv_ics_get;
2153 xic->ics_resend = pnv_ics_resend;
2154
2155 pmc->compat = compat;
2156 pmc->compat_size = sizeof(compat);
2157
2158 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_PNV_PHB);
2159}
2160
2161static void pnv_machine_power9_class_init(ObjectClass *oc, void *data)
2162{
2163 MachineClass *mc = MACHINE_CLASS(oc);
2164 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc);
2165 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc);
2166 static const char compat[] = "qemu,powernv9\0ibm,powernv";
2167
2168 static GlobalProperty phb_compat[] = {
2169 { TYPE_PNV_PHB, "version", "4" },
2170 { TYPE_PNV_PHB_ROOT_PORT, "version", "4" },
2171 };
2172
2173 mc->desc = "IBM PowerNV (Non-Virtualized) POWER9";
2174 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0");
2175 compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat));
2176
2177 xfc->match_nvt = pnv_match_nvt;
2178
2179 mc->alias = "powernv";
2180
2181 pmc->compat = compat;
2182 pmc->compat_size = sizeof(compat);
2183 pmc->dt_power_mgt = pnv_dt_power_mgt;
2184
2185 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_PNV_PHB);
2186}
2187
2188static void pnv_machine_power10_class_init(ObjectClass *oc, void *data)
2189{
2190 MachineClass *mc = MACHINE_CLASS(oc);
2191 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc);
2192 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc);
2193 static const char compat[] = "qemu,powernv10\0ibm,powernv";
2194
2195 static GlobalProperty phb_compat[] = {
2196 { TYPE_PNV_PHB, "version", "5" },
2197 { TYPE_PNV_PHB_ROOT_PORT, "version", "5" },
2198 };
2199
2200 mc->desc = "IBM PowerNV (Non-Virtualized) POWER10";
2201 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power10_v2.0");
2202 compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat));
2203
2204 pmc->compat = compat;
2205 pmc->compat_size = sizeof(compat);
2206 pmc->dt_power_mgt = pnv_dt_power_mgt;
2207
2208 xfc->match_nvt = pnv10_xive_match_nvt;
2209
2210 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_PNV_PHB);
2211}
2212
2213static bool pnv_machine_get_hb(Object *obj, Error **errp)
2214{
2215 PnvMachineState *pnv = PNV_MACHINE(obj);
2216
2217 return !!pnv->fw_load_addr;
2218}
2219
2220static void pnv_machine_set_hb(Object *obj, bool value, Error **errp)
2221{
2222 PnvMachineState *pnv = PNV_MACHINE(obj);
2223
2224 if (value) {
2225 pnv->fw_load_addr = 0x8000000;
2226 }
2227}
2228
2229static void pnv_cpu_do_nmi_on_cpu(CPUState *cs, run_on_cpu_data arg)
2230{
2231 PowerPCCPU *cpu = POWERPC_CPU(cs);
2232 CPUPPCState *env = &cpu->env;
2233
2234 cpu_synchronize_state(cs);
2235 ppc_cpu_do_system_reset(cs);
2236 if (env->spr[SPR_SRR1] & SRR1_WAKESTATE) {
2237
2238
2239
2240
2241
2242 if (!(env->spr[SPR_SRR1] & SRR1_WAKERESET)) {
2243 warn_report("ppc_cpu_do_system_reset does not set system reset wakeup reason");
2244 env->spr[SPR_SRR1] |= SRR1_WAKERESET;
2245 }
2246 } else {
2247
2248
2249
2250
2251
2252
2253
2254 env->spr[SPR_SRR1] |= SRR1_WAKESCOM;
2255 }
2256}
2257
2258static void pnv_nmi(NMIState *n, int cpu_index, Error **errp)
2259{
2260 CPUState *cs;
2261
2262 CPU_FOREACH(cs) {
2263 async_run_on_cpu(cs, pnv_cpu_do_nmi_on_cpu, RUN_ON_CPU_NULL);
2264 }
2265}
2266
2267static void pnv_machine_class_init(ObjectClass *oc, void *data)
2268{
2269 MachineClass *mc = MACHINE_CLASS(oc);
2270 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc);
2271 NMIClass *nc = NMI_CLASS(oc);
2272
2273 mc->desc = "IBM PowerNV (Non-Virtualized)";
2274 mc->init = pnv_init;
2275 mc->reset = pnv_reset;
2276 mc->max_cpus = MAX_CPUS;
2277
2278 mc->block_default_type = IF_IDE;
2279 mc->no_parallel = 1;
2280 mc->default_boot_order = NULL;
2281
2282
2283
2284
2285 mc->default_ram_size = 1 * GiB;
2286 mc->default_ram_id = "pnv.ram";
2287 ispc->print_info = pnv_pic_print_info;
2288 nc->nmi_monitor_handler = pnv_nmi;
2289
2290 object_class_property_add_bool(oc, "hb-mode",
2291 pnv_machine_get_hb, pnv_machine_set_hb);
2292 object_class_property_set_description(oc, "hb-mode",
2293 "Use a hostboot like boot loader");
2294}
2295
2296#define DEFINE_PNV8_CHIP_TYPE(type, class_initfn) \
2297 { \
2298 .name = type, \
2299 .class_init = class_initfn, \
2300 .parent = TYPE_PNV8_CHIP, \
2301 }
2302
2303#define DEFINE_PNV9_CHIP_TYPE(type, class_initfn) \
2304 { \
2305 .name = type, \
2306 .class_init = class_initfn, \
2307 .parent = TYPE_PNV9_CHIP, \
2308 }
2309
2310#define DEFINE_PNV10_CHIP_TYPE(type, class_initfn) \
2311 { \
2312 .name = type, \
2313 .class_init = class_initfn, \
2314 .parent = TYPE_PNV10_CHIP, \
2315 }
2316
2317static const TypeInfo types[] = {
2318 {
2319 .name = MACHINE_TYPE_NAME("powernv10"),
2320 .parent = TYPE_PNV_MACHINE,
2321 .class_init = pnv_machine_power10_class_init,
2322 .interfaces = (InterfaceInfo[]) {
2323 { TYPE_XIVE_FABRIC },
2324 { },
2325 },
2326 },
2327 {
2328 .name = MACHINE_TYPE_NAME("powernv9"),
2329 .parent = TYPE_PNV_MACHINE,
2330 .class_init = pnv_machine_power9_class_init,
2331 .interfaces = (InterfaceInfo[]) {
2332 { TYPE_XIVE_FABRIC },
2333 { },
2334 },
2335 },
2336 {
2337 .name = MACHINE_TYPE_NAME("powernv8"),
2338 .parent = TYPE_PNV_MACHINE,
2339 .class_init = pnv_machine_power8_class_init,
2340 .interfaces = (InterfaceInfo[]) {
2341 { TYPE_XICS_FABRIC },
2342 { },
2343 },
2344 },
2345 {
2346 .name = TYPE_PNV_MACHINE,
2347 .parent = TYPE_MACHINE,
2348 .abstract = true,
2349 .instance_size = sizeof(PnvMachineState),
2350 .class_init = pnv_machine_class_init,
2351 .class_size = sizeof(PnvMachineClass),
2352 .interfaces = (InterfaceInfo[]) {
2353 { TYPE_INTERRUPT_STATS_PROVIDER },
2354 { TYPE_NMI },
2355 { },
2356 },
2357 },
2358 {
2359 .name = TYPE_PNV_CHIP,
2360 .parent = TYPE_SYS_BUS_DEVICE,
2361 .class_init = pnv_chip_class_init,
2362 .instance_size = sizeof(PnvChip),
2363 .class_size = sizeof(PnvChipClass),
2364 .abstract = true,
2365 },
2366
2367
2368
2369
2370 {
2371 .name = TYPE_PNV10_CHIP,
2372 .parent = TYPE_PNV_CHIP,
2373 .instance_init = pnv_chip_power10_instance_init,
2374 .instance_size = sizeof(Pnv10Chip),
2375 },
2376 DEFINE_PNV10_CHIP_TYPE(TYPE_PNV_CHIP_POWER10, pnv_chip_power10_class_init),
2377
2378
2379
2380
2381 {
2382 .name = TYPE_PNV9_CHIP,
2383 .parent = TYPE_PNV_CHIP,
2384 .instance_init = pnv_chip_power9_instance_init,
2385 .instance_size = sizeof(Pnv9Chip),
2386 },
2387 DEFINE_PNV9_CHIP_TYPE(TYPE_PNV_CHIP_POWER9, pnv_chip_power9_class_init),
2388
2389
2390
2391
2392 {
2393 .name = TYPE_PNV8_CHIP,
2394 .parent = TYPE_PNV_CHIP,
2395 .instance_init = pnv_chip_power8_instance_init,
2396 .instance_size = sizeof(Pnv8Chip),
2397 },
2398 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8, pnv_chip_power8_class_init),
2399 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8E, pnv_chip_power8e_class_init),
2400 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8NVL,
2401 pnv_chip_power8nvl_class_init),
2402};
2403
2404DEFINE_TYPES(types)
2405
