1#ifndef QEMU_PCI_H
2#define QEMU_PCI_H
3
4#include "exec/memory.h"
5#include "sysemu/dma.h"
6
7
8#include "hw/isa/isa.h"
9
10extern bool pci_available;
11
12
13
14#define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07))
15#define PCI_BUS_NUM(x) (((x) >> 8) & 0xff)
16#define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f)
17#define PCI_FUNC(devfn) ((devfn) & 0x07)
18#define PCI_BUILD_BDF(bus, devfn) ((bus << 8) | (devfn))
19#define PCI_BDF_TO_DEVFN(x) ((x) & 0xff)
20#define PCI_BUS_MAX 256
21#define PCI_DEVFN_MAX 256
22#define PCI_SLOT_MAX 32
23#define PCI_FUNC_MAX 8
24
25
26#include "hw/pci/pci_ids.h"
27
28
29
30
31#define PCI_DEVICE_ID_IBM_440GX 0x027f
32#define PCI_DEVICE_ID_IBM_OPENPIC2 0xffff
33
34
35#define PCI_VENDOR_ID_HITACHI 0x1054
36#define PCI_DEVICE_ID_HITACHI_SH7751R 0x350e
37
38
39#define PCI_DEVICE_ID_APPLE_343S1201 0x0010
40#define PCI_DEVICE_ID_APPLE_UNI_N_I_PCI 0x001e
41#define PCI_DEVICE_ID_APPLE_UNI_N_PCI 0x001f
42#define PCI_DEVICE_ID_APPLE_UNI_N_KEYL 0x0022
43#define PCI_DEVICE_ID_APPLE_IPID_USB 0x003f
44
45
46#define PCI_DEVICE_ID_REALTEK_8029 0x8029
47
48
49#define PCI_DEVICE_ID_XILINX_XC2VP30 0x0300
50
51
52#define PCI_DEVICE_ID_MARVELL_GT6412X 0x4620
53
54
55#define PCI_VENDOR_ID_QEMU 0x1234
56#define PCI_DEVICE_ID_QEMU_VGA 0x1111
57#define PCI_DEVICE_ID_QEMU_IPMI 0x1112
58
59
60#define PCI_VENDOR_ID_VMWARE 0x15ad
61#define PCI_DEVICE_ID_VMWARE_SVGA2 0x0405
62#define PCI_DEVICE_ID_VMWARE_SVGA 0x0710
63#define PCI_DEVICE_ID_VMWARE_NET 0x0720
64#define PCI_DEVICE_ID_VMWARE_SCSI 0x0730
65#define PCI_DEVICE_ID_VMWARE_PVSCSI 0x07C0
66#define PCI_DEVICE_ID_VMWARE_IDE 0x1729
67#define PCI_DEVICE_ID_VMWARE_VMXNET3 0x07B0
68
69
70#define PCI_DEVICE_ID_INTEL_82551IT 0x1209
71#define PCI_DEVICE_ID_INTEL_82557 0x1229
72#define PCI_DEVICE_ID_INTEL_82801IR 0x2922
73
74
75#define PCI_VENDOR_ID_REDHAT_QUMRANET 0x1af4
76#define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4
77#define PCI_SUBDEVICE_ID_QEMU 0x1100
78
79
80#define PCI_DEVICE_ID_VIRTIO_NET 0x1000
81#define PCI_DEVICE_ID_VIRTIO_BLOCK 0x1001
82#define PCI_DEVICE_ID_VIRTIO_BALLOON 0x1002
83#define PCI_DEVICE_ID_VIRTIO_CONSOLE 0x1003
84#define PCI_DEVICE_ID_VIRTIO_SCSI 0x1004
85#define PCI_DEVICE_ID_VIRTIO_RNG 0x1005
86#define PCI_DEVICE_ID_VIRTIO_9P 0x1009
87#define PCI_DEVICE_ID_VIRTIO_VSOCK 0x1012
88
89
90
91
92
93
94
95
96#define PCI_DEVICE_ID_VIRTIO_10_BASE 0x1040
97
98#define PCI_VENDOR_ID_REDHAT 0x1b36
99#define PCI_DEVICE_ID_REDHAT_BRIDGE 0x0001
100#define PCI_DEVICE_ID_REDHAT_SERIAL 0x0002
101#define PCI_DEVICE_ID_REDHAT_SERIAL2 0x0003
102#define PCI_DEVICE_ID_REDHAT_SERIAL4 0x0004
103#define PCI_DEVICE_ID_REDHAT_TEST 0x0005
104#define PCI_DEVICE_ID_REDHAT_ROCKER 0x0006
105#define PCI_DEVICE_ID_REDHAT_SDHCI 0x0007
106#define PCI_DEVICE_ID_REDHAT_PCIE_HOST 0x0008
107#define PCI_DEVICE_ID_REDHAT_PXB 0x0009
108#define PCI_DEVICE_ID_REDHAT_BRIDGE_SEAT 0x000a
109#define PCI_DEVICE_ID_REDHAT_PXB_PCIE 0x000b
110#define PCI_DEVICE_ID_REDHAT_PCIE_RP 0x000c
111#define PCI_DEVICE_ID_REDHAT_XHCI 0x000d
112#define PCI_DEVICE_ID_REDHAT_PCIE_BRIDGE 0x000e
113#define PCI_DEVICE_ID_REDHAT_MDPY 0x000f
114#define PCI_DEVICE_ID_REDHAT_NVME 0x0010
115#define PCI_DEVICE_ID_REDHAT_PVPANIC 0x0011
116#define PCI_DEVICE_ID_REDHAT_ACPI_ERST 0x0012
117#define PCI_DEVICE_ID_REDHAT_QXL 0x0100
118
119#define FMT_PCIBUS PRIx64
120
121typedef uint64_t pcibus_t;
122
123struct PCIHostDeviceAddress {
124 unsigned int domain;
125 unsigned int bus;
126 unsigned int slot;
127 unsigned int function;
128};
129
130typedef void PCIConfigWriteFunc(PCIDevice *pci_dev,
131 uint32_t address, uint32_t data, int len);
132typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev,
133 uint32_t address, int len);
134typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num,
135 pcibus_t addr, pcibus_t size, int type);
136typedef void PCIUnregisterFunc(PCIDevice *pci_dev);
137
138typedef void MSITriggerFunc(PCIDevice *dev, MSIMessage msg);
139typedef MSIMessage MSIPrepareMessageFunc(PCIDevice *dev, unsigned vector);
140typedef MSIMessage MSIxPrepareMessageFunc(PCIDevice *dev, unsigned vector);
141
142typedef struct PCIIORegion {
143 pcibus_t addr;
144#define PCI_BAR_UNMAPPED (~(pcibus_t)0)
145 pcibus_t size;
146 uint8_t type;
147 MemoryRegion *memory;
148 MemoryRegion *address_space;
149} PCIIORegion;
150
151#define PCI_ROM_SLOT 6
152#define PCI_NUM_REGIONS 7
153
154enum {
155 QEMU_PCI_VGA_MEM,
156 QEMU_PCI_VGA_IO_LO,
157 QEMU_PCI_VGA_IO_HI,
158 QEMU_PCI_VGA_NUM_REGIONS,
159};
160
161#define QEMU_PCI_VGA_MEM_BASE 0xa0000
162#define QEMU_PCI_VGA_MEM_SIZE 0x20000
163#define QEMU_PCI_VGA_IO_LO_BASE 0x3b0
164#define QEMU_PCI_VGA_IO_LO_SIZE 0xc
165#define QEMU_PCI_VGA_IO_HI_BASE 0x3c0
166#define QEMU_PCI_VGA_IO_HI_SIZE 0x20
167
168#include "hw/pci/pci_regs.h"
169
170
171#define PCI_HEADER_TYPE_MULTI_FUNCTION 0x80
172
173
174#define PCI_CONFIG_HEADER_SIZE 0x40
175
176#define PCI_CONFIG_SPACE_SIZE 0x100
177
178#define PCIE_CONFIG_SPACE_SIZE 0x1000
179
180#define PCI_NUM_PINS 4
181
182
183enum {
184 QEMU_PCI_CAP_MSI = 0x1,
185 QEMU_PCI_CAP_MSIX = 0x2,
186 QEMU_PCI_CAP_EXPRESS = 0x4,
187
188
189#define QEMU_PCI_CAP_MULTIFUNCTION_BITNR 3
190 QEMU_PCI_CAP_MULTIFUNCTION = (1 << QEMU_PCI_CAP_MULTIFUNCTION_BITNR),
191
192
193#define QEMU_PCI_CAP_SERR_BITNR 4
194 QEMU_PCI_CAP_SERR = (1 << QEMU_PCI_CAP_SERR_BITNR),
195
196#define QEMU_PCI_SHPC_BITNR 5
197 QEMU_PCI_CAP_SHPC = (1 << QEMU_PCI_SHPC_BITNR),
198#define QEMU_PCI_SLOTID_BITNR 6
199 QEMU_PCI_CAP_SLOTID = (1 << QEMU_PCI_SLOTID_BITNR),
200
201#define QEMU_PCIE_SLTCAP_PCP_BITNR 7
202 QEMU_PCIE_SLTCAP_PCP = (1 << QEMU_PCIE_SLTCAP_PCP_BITNR),
203
204#define QEMU_PCIE_LNKSTA_DLLLA_BITNR 8
205 QEMU_PCIE_LNKSTA_DLLLA = (1 << QEMU_PCIE_LNKSTA_DLLLA_BITNR),
206#define QEMU_PCIE_EXTCAP_INIT_BITNR 9
207 QEMU_PCIE_EXTCAP_INIT = (1 << QEMU_PCIE_EXTCAP_INIT_BITNR),
208#define QEMU_PCIE_CXL_BITNR 10
209 QEMU_PCIE_CAP_CXL = (1 << QEMU_PCIE_CXL_BITNR),
210#define QEMU_PCIE_ERR_UNC_MASK_BITNR 11
211 QEMU_PCIE_ERR_UNC_MASK = (1 << QEMU_PCIE_ERR_UNC_MASK_BITNR),
212};
213
214typedef struct PCIINTxRoute {
215 enum {
216 PCI_INTX_ENABLED,
217 PCI_INTX_INVERTED,
218 PCI_INTX_DISABLED,
219 } mode;
220 int irq;
221} PCIINTxRoute;
222
223typedef void (*PCIINTxRoutingNotifier)(PCIDevice *dev);
224typedef int (*MSIVectorUseNotifier)(PCIDevice *dev, unsigned int vector,
225 MSIMessage msg);
226typedef void (*MSIVectorReleaseNotifier)(PCIDevice *dev, unsigned int vector);
227typedef void (*MSIVectorPollNotifier)(PCIDevice *dev,
228 unsigned int vector_start,
229 unsigned int vector_end);
230
231void pci_register_bar(PCIDevice *pci_dev, int region_num,
232 uint8_t attr, MemoryRegion *memory);
233void pci_register_vga(PCIDevice *pci_dev, MemoryRegion *mem,
234 MemoryRegion *io_lo, MemoryRegion *io_hi);
235void pci_unregister_vga(PCIDevice *pci_dev);
236pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num);
237
238int pci_add_capability(PCIDevice *pdev, uint8_t cap_id,
239 uint8_t offset, uint8_t size,
240 Error **errp);
241
242void pci_del_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_size);
243
244uint8_t pci_find_capability(PCIDevice *pci_dev, uint8_t cap_id);
245
246
247uint32_t pci_default_read_config(PCIDevice *d,
248 uint32_t address, int len);
249void pci_default_write_config(PCIDevice *d,
250 uint32_t address, uint32_t val, int len);
251void pci_device_save(PCIDevice *s, QEMUFile *f);
252int pci_device_load(PCIDevice *s, QEMUFile *f);
253MemoryRegion *pci_address_space(PCIDevice *dev);
254MemoryRegion *pci_address_space_io(PCIDevice *dev);
255
256
257
258
259
260int pci_bar(PCIDevice *d, int reg);
261
262typedef void (*pci_set_irq_fn)(void *opaque, int irq_num, int level);
263typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num);
264typedef PCIINTxRoute (*pci_route_irq_fn)(void *opaque, int pin);
265
266#define TYPE_PCI_BUS "PCI"
267OBJECT_DECLARE_TYPE(PCIBus, PCIBusClass, PCI_BUS)
268#define TYPE_PCIE_BUS "PCIE"
269#define TYPE_CXL_BUS "CXL"
270
271typedef void (*pci_bus_dev_fn)(PCIBus *b, PCIDevice *d, void *opaque);
272typedef void (*pci_bus_fn)(PCIBus *b, void *opaque);
273typedef void *(*pci_bus_ret_fn)(PCIBus *b, void *opaque);
274
275bool pci_bus_is_express(const PCIBus *bus);
276
277void pci_root_bus_init(PCIBus *bus, size_t bus_size, DeviceState *parent,
278 const char *name,
279 MemoryRegion *address_space_mem,
280 MemoryRegion *address_space_io,
281 uint8_t devfn_min, const char *typename);
282PCIBus *pci_root_bus_new(DeviceState *parent, const char *name,
283 MemoryRegion *address_space_mem,
284 MemoryRegion *address_space_io,
285 uint8_t devfn_min, const char *typename);
286void pci_root_bus_cleanup(PCIBus *bus);
287void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq,
288 void *irq_opaque, int nirq);
289void pci_bus_map_irqs(PCIBus *bus, pci_map_irq_fn map_irq);
290void pci_bus_irqs_cleanup(PCIBus *bus);
291int pci_bus_get_irq_level(PCIBus *bus, int irq_num);
292
293static inline int pci_swizzle(int slot, int pin)
294{
295 return (slot + pin) % PCI_NUM_PINS;
296}
297int pci_swizzle_map_irq_fn(PCIDevice *pci_dev, int pin);
298PCIBus *pci_register_root_bus(DeviceState *parent, const char *name,
299 pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
300 void *irq_opaque,
301 MemoryRegion *address_space_mem,
302 MemoryRegion *address_space_io,
303 uint8_t devfn_min, int nirq,
304 const char *typename);
305void pci_unregister_root_bus(PCIBus *bus);
306void pci_bus_set_route_irq_fn(PCIBus *, pci_route_irq_fn);
307PCIINTxRoute pci_device_route_intx_to_irq(PCIDevice *dev, int pin);
308bool pci_intx_route_changed(PCIINTxRoute *old, PCIINTxRoute *new);
309void pci_bus_fire_intx_routing_notifier(PCIBus *bus);
310void pci_device_set_intx_routing_notifier(PCIDevice *dev,
311 PCIINTxRoutingNotifier notifier);
312void pci_device_reset(PCIDevice *dev);
313
314PCIDevice *pci_nic_init_nofail(NICInfo *nd, PCIBus *rootbus,
315 const char *default_model,
316 const char *default_devaddr);
317
318PCIDevice *pci_vga_init(PCIBus *bus);
319
320static inline PCIBus *pci_get_bus(const PCIDevice *dev)
321{
322 return PCI_BUS(qdev_get_parent_bus(DEVICE(dev)));
323}
324int pci_bus_num(PCIBus *s);
325void pci_bus_range(PCIBus *bus, int *min_bus, int *max_bus);
326static inline int pci_dev_bus_num(const PCIDevice *dev)
327{
328 return pci_bus_num(pci_get_bus(dev));
329}
330
331int pci_bus_numa_node(PCIBus *bus);
332void pci_for_each_device(PCIBus *bus, int bus_num,
333 pci_bus_dev_fn fn,
334 void *opaque);
335void pci_for_each_device_reverse(PCIBus *bus, int bus_num,
336 pci_bus_dev_fn fn,
337 void *opaque);
338void pci_for_each_device_under_bus(PCIBus *bus,
339 pci_bus_dev_fn fn, void *opaque);
340void pci_for_each_device_under_bus_reverse(PCIBus *bus,
341 pci_bus_dev_fn fn,
342 void *opaque);
343void pci_for_each_bus_depth_first(PCIBus *bus, pci_bus_ret_fn begin,
344 pci_bus_fn end, void *parent_state);
345PCIDevice *pci_get_function_0(PCIDevice *pci_dev);
346
347
348static inline
349void pci_for_each_bus(PCIBus *bus, pci_bus_fn fn, void *opaque)
350{
351 pci_for_each_bus_depth_first(bus, NULL, fn, opaque);
352}
353
354PCIBus *pci_device_root_bus(const PCIDevice *d);
355const char *pci_root_bus_path(PCIDevice *dev);
356bool pci_bus_bypass_iommu(PCIBus *bus);
357PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn);
358int pci_qdev_find_device(const char *id, PCIDevice **pdev);
359void pci_bus_get_w64_range(PCIBus *bus, Range *range);
360
361void pci_device_deassert_intx(PCIDevice *dev);
362
363typedef AddressSpace *(*PCIIOMMUFunc)(PCIBus *, void *, int);
364
365AddressSpace *pci_device_iommu_address_space(PCIDevice *dev);
366void pci_setup_iommu(PCIBus *bus, PCIIOMMUFunc fn, void *opaque);
367
368pcibus_t pci_bar_address(PCIDevice *d,
369 int reg, uint8_t type, pcibus_t size);
370
371static inline void
372pci_set_byte(uint8_t *config, uint8_t val)
373{
374 *config = val;
375}
376
377static inline uint8_t
378pci_get_byte(const uint8_t *config)
379{
380 return *config;
381}
382
383static inline void
384pci_set_word(uint8_t *config, uint16_t val)
385{
386 stw_le_p(config, val);
387}
388
389static inline uint16_t
390pci_get_word(const uint8_t *config)
391{
392 return lduw_le_p(config);
393}
394
395static inline void
396pci_set_long(uint8_t *config, uint32_t val)
397{
398 stl_le_p(config, val);
399}
400
401static inline uint32_t
402pci_get_long(const uint8_t *config)
403{
404 return ldl_le_p(config);
405}
406
407
408
409
410
411
412
413
414static inline void
415pci_set_quad(uint8_t *config, uint64_t val)
416{
417 stq_le_p(config, val);
418}
419
420static inline uint64_t
421pci_get_quad(const uint8_t *config)
422{
423 return ldq_le_p(config);
424}
425
426static inline void
427pci_config_set_vendor_id(uint8_t *pci_config, uint16_t val)
428{
429 pci_set_word(&pci_config[PCI_VENDOR_ID], val);
430}
431
432static inline void
433pci_config_set_device_id(uint8_t *pci_config, uint16_t val)
434{
435 pci_set_word(&pci_config[PCI_DEVICE_ID], val);
436}
437
438static inline void
439pci_config_set_revision(uint8_t *pci_config, uint8_t val)
440{
441 pci_set_byte(&pci_config[PCI_REVISION_ID], val);
442}
443
444static inline void
445pci_config_set_class(uint8_t *pci_config, uint16_t val)
446{
447 pci_set_word(&pci_config[PCI_CLASS_DEVICE], val);
448}
449
450static inline void
451pci_config_set_prog_interface(uint8_t *pci_config, uint8_t val)
452{
453 pci_set_byte(&pci_config[PCI_CLASS_PROG], val);
454}
455
456static inline void
457pci_config_set_interrupt_pin(uint8_t *pci_config, uint8_t val)
458{
459 pci_set_byte(&pci_config[PCI_INTERRUPT_PIN], val);
460}
461
462
463
464
465
466
467
468static inline uint8_t
469pci_byte_test_and_clear_mask(uint8_t *config, uint8_t mask)
470{
471 uint8_t val = pci_get_byte(config);
472 pci_set_byte(config, val & ~mask);
473 return val & mask;
474}
475
476static inline uint8_t
477pci_byte_test_and_set_mask(uint8_t *config, uint8_t mask)
478{
479 uint8_t val = pci_get_byte(config);
480 pci_set_byte(config, val | mask);
481 return val & mask;
482}
483
484static inline uint16_t
485pci_word_test_and_clear_mask(uint8_t *config, uint16_t mask)
486{
487 uint16_t val = pci_get_word(config);
488 pci_set_word(config, val & ~mask);
489 return val & mask;
490}
491
492static inline uint16_t
493pci_word_test_and_set_mask(uint8_t *config, uint16_t mask)
494{
495 uint16_t val = pci_get_word(config);
496 pci_set_word(config, val | mask);
497 return val & mask;
498}
499
500static inline uint32_t
501pci_long_test_and_clear_mask(uint8_t *config, uint32_t mask)
502{
503 uint32_t val = pci_get_long(config);
504 pci_set_long(config, val & ~mask);
505 return val & mask;
506}
507
508static inline uint32_t
509pci_long_test_and_set_mask(uint8_t *config, uint32_t mask)
510{
511 uint32_t val = pci_get_long(config);
512 pci_set_long(config, val | mask);
513 return val & mask;
514}
515
516static inline uint64_t
517pci_quad_test_and_clear_mask(uint8_t *config, uint64_t mask)
518{
519 uint64_t val = pci_get_quad(config);
520 pci_set_quad(config, val & ~mask);
521 return val & mask;
522}
523
524static inline uint64_t
525pci_quad_test_and_set_mask(uint8_t *config, uint64_t mask)
526{
527 uint64_t val = pci_get_quad(config);
528 pci_set_quad(config, val | mask);
529 return val & mask;
530}
531
532
533static inline void
534pci_set_byte_by_mask(uint8_t *config, uint8_t mask, uint8_t reg)
535{
536 uint8_t val = pci_get_byte(config);
537 uint8_t rval;
538
539 assert(mask);
540 rval = reg << ctz32(mask);
541 pci_set_byte(config, (~mask & val) | (mask & rval));
542}
543
544static inline void
545pci_set_word_by_mask(uint8_t *config, uint16_t mask, uint16_t reg)
546{
547 uint16_t val = pci_get_word(config);
548 uint16_t rval;
549
550 assert(mask);
551 rval = reg << ctz32(mask);
552 pci_set_word(config, (~mask & val) | (mask & rval));
553}
554
555static inline void
556pci_set_long_by_mask(uint8_t *config, uint32_t mask, uint32_t reg)
557{
558 uint32_t val = pci_get_long(config);
559 uint32_t rval;
560
561 assert(mask);
562 rval = reg << ctz32(mask);
563 pci_set_long(config, (~mask & val) | (mask & rval));
564}
565
566static inline void
567pci_set_quad_by_mask(uint8_t *config, uint64_t mask, uint64_t reg)
568{
569 uint64_t val = pci_get_quad(config);
570 uint64_t rval;
571
572 assert(mask);
573 rval = reg << ctz32(mask);
574 pci_set_quad(config, (~mask & val) | (mask & rval));
575}
576
577PCIDevice *pci_new_multifunction(int devfn, bool multifunction,
578 const char *name);
579PCIDevice *pci_new(int devfn, const char *name);
580bool pci_realize_and_unref(PCIDevice *dev, PCIBus *bus, Error **errp);
581
582PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn,
583 bool multifunction,
584 const char *name);
585PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name);
586
587void lsi53c8xx_handle_legacy_cmdline(DeviceState *lsi_dev);
588
589qemu_irq pci_allocate_irq(PCIDevice *pci_dev);
590void pci_set_irq(PCIDevice *pci_dev, int level);
591
592static inline void pci_irq_assert(PCIDevice *pci_dev)
593{
594 pci_set_irq(pci_dev, 1);
595}
596
597static inline void pci_irq_deassert(PCIDevice *pci_dev)
598{
599 pci_set_irq(pci_dev, 0);
600}
601
602
603
604
605
606static inline void pci_irq_pulse(PCIDevice *pci_dev)
607{
608 pci_irq_assert(pci_dev);
609 pci_irq_deassert(pci_dev);
610}
611
612MSIMessage pci_get_msi_message(PCIDevice *dev, int vector);
613void pci_set_power(PCIDevice *pci_dev, bool state);
614
615#endif
616