1/* 2 * sPAPR CPU core device. 3 * 4 * Copyright (C) 2016 Bharata B Rao <bharata@linux.vnet.ibm.com> 5 * 6 * This work is licensed under the terms of the GNU GPL, version 2 or later. 7 * See the COPYING file in the top-level directory. 8 */ 9#ifndef HW_SPAPR_CPU_CORE_H 10#define HW_SPAPR_CPU_CORE_H 11 12#include "hw/cpu/core.h" 13#include "hw/qdev-core.h" 14#include "target/ppc/cpu-qom.h" 15#include "target/ppc/cpu.h" 16#include "qom/object.h" 17 18#define TYPE_SPAPR_CPU_CORE "spapr-cpu-core" 19OBJECT_DECLARE_TYPE(SpaprCpuCore, SpaprCpuCoreClass, 20 SPAPR_CPU_CORE) 21 22#define SPAPR_CPU_CORE_TYPE_NAME(model) model "-" TYPE_SPAPR_CPU_CORE 23 24struct SpaprCpuCore { 25 /*< private >*/ 26 CPUCore parent_obj; 27 28 /*< public >*/ 29 PowerPCCPU **threads; 30 int node_id; 31 bool pre_3_0_migration; /* older machine don't know about SpaprCpuState */ 32}; 33 34struct SpaprCpuCoreClass { 35 DeviceClass parent_class; 36 const char *cpu_type; 37}; 38 39const char *spapr_get_cpu_core_type(const char *cpu_type); 40void spapr_cpu_set_entry_state(PowerPCCPU *cpu, target_ulong nip, 41 target_ulong r1, target_ulong r3, 42 target_ulong r4); 43 44typedef struct SpaprCpuState { 45 uint64_t vpa_addr; 46 uint64_t slb_shadow_addr, slb_shadow_size; 47 uint64_t dtl_addr, dtl_size; 48 bool prod; /* not migrated, only used to improve dispatch latencies */ 49 struct ICPState *icp; 50 struct XiveTCTX *tctx; 51 52 /* Fields for nested-HV support */ 53 bool in_nested; /* true while the L2 is executing */ 54 CPUPPCState *nested_host_state; /* holds the L1 state while L2 executes */ 55 int64_t nested_tb_offset; /* L1->L2 TB offset */ 56} SpaprCpuState; 57 58static inline SpaprCpuState *spapr_cpu_state(PowerPCCPU *cpu) 59{ 60 return (SpaprCpuState *)cpu->machine_data; 61} 62 63#endif 64